cresample: Added active cresample_v4_0.
Deprecated cresample_v3_0. Signed-off-by: Durga challa <vnsldurg@xilinx.com> Acked-by: Srikanth Vemula <svemula@xilinx.com>
This commit is contained in:
Durga challa
Jagannadha Sutradharudu Teki
parent
495a93a1fb
commit
e1a1830adf
7 changed files with 1291 additions and 0 deletions
45
XilinxProcessorIPLib/drivers/cresample/data/cresample.mdd
Executable file
45
XilinxProcessorIPLib/drivers/cresample/data/cresample.mdd
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@ -0,0 +1,45 @@
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###############################################################################
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#
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# Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
# of this software and associated documentation files (the "Software"), to deal
|
||||
# in the Software without restriction, including without limitation the rights
|
||||
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
# copies of the Software, and to permit persons to whom the Software is
|
||||
# furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice shall be included in
|
||||
# all copies or substantial portions of the Software.
|
||||
#
|
||||
# Use of the Software is limited solely to applications:
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# (a) running on a Xilinx device, or
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# (b) that interact with a Xilinx device through a bus or interconnect.
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||||
#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
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# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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||||
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
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# SOFTWARE.
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#
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||||
# Except as contained in this notice, the name of the Xilinx shall not be used
|
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# in advertising or otherwise to promote the sale, use or other dealings in
|
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# this Software without prior written authorization from Xilinx.
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#
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###############################################################################
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OPTION psf_version = 2.1;
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BEGIN driver cresample
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OPTION supported_peripherals = (v_cresample);
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OPTION driver_state = ACTIVE;
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OPTION copyfiles = all;
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OPTION VERSION = 4.0;
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OPTION NAME = cresample;
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END driver
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37
XilinxProcessorIPLib/drivers/cresample/data/cresample.tcl
Executable file
37
XilinxProcessorIPLib/drivers/cresample/data/cresample.tcl
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###############################################################################
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#
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# Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
|
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# of this software and associated documentation files (the "Software"), to deal
|
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# in the Software without restriction, including without limitation the rights
|
||||
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
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# copies of the Software, and to permit persons to whom the Software is
|
||||
# furnished to do so, subject to the following conditions:
|
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#
|
||||
# The above copyright notice and this permission notice shall be included in
|
||||
# all copies or substantial portions of the Software.
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||||
#
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# Use of the Software is limited solely to applications:
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# (a) running on a Xilinx device, or
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# (b) that interact with a Xilinx device through a bus or interconnect.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
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# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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# SOFTWARE.
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#
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# Except as contained in this notice, the name of the Xilinx shall not be used
|
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# in advertising or otherwise to promote the sale, use or other dealings in
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# this Software without prior written authorization from Xilinx.
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#
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###############################################################################
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proc generate {drv_handle} {
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xdefine_include_file $drv_handle "xparameters.h" "CRESAMPLE" "NUM_INSTANCES" "C_BASEADDR" "C_HIGHADDR" "DEVICE_ID" "C_S_AXIS_VIDEO_DATA_WIDTH" "C_S_AXIS_VIDEO_FORMAT" "C_S_AXIS_VIDEO_TDATA_WIDTH" "C_M_AXIS_VIDEO_DATA_WIDTH" "C_M_AXIS_VIDEO_FORMAT" "C_M_AXIS_VIDEO_TDATA_WIDTH" "C_HAS_AXI4_LITE" "C_HAS_DEBUG" "C_HAS_INTC_IF" "C_MAX_COLS" "C_ACTIVE_COLS" "C_ACTIVE_ROWS" "C_CHROMA_PARITY" "C_FIELD_PARITY" "C_INTERLACED" "C_NUM_H_TAPS" "C_NUM_V_TAPS" "C_CONVERT_TYPE" "C_COEF_WIDTH"
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xdefine_canonical_xpars $drv_handle "xparameters.h" "CRESAMPLE" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_S_AXIS_VIDEO_DATA_WIDTH" "C_S_AXIS_VIDEO_FORMAT" "C_S_AXIS_VIDEO_TDATA_WIDTH" "C_M_AXIS_VIDEO_DATA_WIDTH" "C_M_AXIS_VIDEO_FORMAT" "C_M_AXIS_VIDEO_TDATA_WIDTH" "C_HAS_AXI4_LITE" "C_HAS_DEBUG" "C_HAS_INTC_IF" "C_MAX_COLS" "C_ACTIVE_COLS" "C_ACTIVE_ROWS" "C_CHROMA_PARITY" "C_FIELD_PARITY" "C_INTERLACED" "C_NUM_H_TAPS" "C_NUM_V_TAPS" "C_CONVERT_TYPE" "C_COEF_WIDTH"
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}
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222
XilinxProcessorIPLib/drivers/cresample/examples/example.c
Executable file
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XilinxProcessorIPLib/drivers/cresample/examples/example.c
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/******************************************************************************
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*
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* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
|
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* of this software and associated documentation files (the "Software"), to deal
|
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* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file example.c
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*
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* This file demonstrates how to use Xilinx Chroma Resampler (cresample)
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* driver of the Xilinx Chroma Resampler core. This code does not
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* cover the core setup and any other configuration which might be
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* required to get the Chroma Resampler device working properly.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 2.00a vc 04/24/12 Updated for v2.00.a
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* 2.00a vc 10/16/12 Switched from Xuint32 to u32
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* Renamed example function to main()
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* Renamed reference to XPAR_CRESAMPLE_0_BASEADDR
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* </pre>
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*
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* ***************************************************************************
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*/
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#include "cresample.h"
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#include "xparameters.h"
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/***************************************************************************/
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// Chroma Resampler Register Reading Example
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// This function provides an example of how to read the current configuration
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// settings of the Chroma Resampler core.
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/***************************************************************************/
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void report_cresample_settings(u32 BaseAddress) {
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u32 reg_val;
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unsigned char inchar=0;
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xil_printf("Chroma Resampler Core Configuration:\r\n");
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xil_printf(" Enable Bit: %1d\r\n", CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_CONTROL) & CRESAMPLE_CTL_EN_MASK);
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xil_printf(" Register Update Bit: %1d\r\n", (CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_CONTROL) & CRESAMPLE_CTL_RU_MASK) >> 1);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_CONTROL );
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xil_printf("CRESAMPLE_CONTROL : %8x\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF00_HPHASE0 );
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xil_printf("CRESAMPLE6_COEF00_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF01_HPHASE0 );
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xil_printf("CRESAMPLE_COEF01_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF02_HPHASE0 );
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xil_printf("CRESAMPLE_COEF02_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF03_HPHASE0 );
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xil_printf("CRESAMPLE_COEF03_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF04_HPHASE0 );
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xil_printf("CRESAMPLE_COEF04_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF05_HPHASE0 );
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xil_printf("CRESAMPLECOEF05_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF06_HPHASE0 );
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xil_printf("CRESAMPLE_COEF06_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF07_HPHASE0 );
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xil_printf("CRESAMPLE_COEF07_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF08_HPHASE0 );
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xil_printf("CRESAMPLE_COEF08_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF09_HPHASE0 );
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xil_printf("CRESAMPLE_COEF09_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF10_HPHASE0 );
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xil_printf("CRESAMPLE_COEF10_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF11_HPHASE0 );
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xil_printf("CRESAMPLE_COEF11_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF12_HPHASE0 );
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xil_printf("CRESAMPLE_COEF12_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF13_HPHASE0 );
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xil_printf("CRESAMPLE_COEF13_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF14_HPHASE0 );
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xil_printf("CRESAMPLE_COEF14_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF15_HPHASE0 );
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xil_printf("CRESAMPLE_COEF15_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF16_HPHASE0 );
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xil_printf("CRESAMPLE_COEF16_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF17_HPHASE0 );
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xil_printf("CRESAMPLE_COEF17_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF18_HPHASE0 );
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xil_printf("CRESAMPLE_COEF18_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF19_HPHASE0 );
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xil_printf("CRESAMPLE_COEF19_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF20_HPHASE0 );
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xil_printf("CRESAMPLE_COEF20_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF21_HPHASE0 );
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xil_printf("CRESAMPLE_COEF21_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF22_HPHASE0 );
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xil_printf("CRESAMPLE_COEF22_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF23_HPHASE0 );
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xil_printf("CRESAMPLE_COEF23_HPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF00_HPHASE1 );
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xil_printf("CRESAMPLE_COEF00_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF01_HPHASE1 );
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xil_printf("CRESAMPLE_COEF01_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF02_HPHASE1 );
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xil_printf("CRESAMPLE_COEF02_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF03_HPHASE1 );
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xil_printf("CRESAMPLE_COEF03_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF04_HPHASE1 );
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xil_printf("CRESAMPLE_COEF04_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF05_HPHASE1 );
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xil_printf("CRESAMPLE_COEF05_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF06_HPHASE1 );
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xil_printf("CRESAMPLE_COEF06_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF07_HPHASE1 );
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xil_printf("CRESAMPLE_COEF07_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF08_HPHASE1 );
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xil_printf("CRESAMPLE_COEF08_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF09_HPHASE1 );
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xil_printf("CRESAMPLE_COEF09_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF10_HPHASE1 );
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xil_printf("CRESAMPLE_COEF10_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF11_HPHASE1 );
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xil_printf("CRESAMPLE_COEF11_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF12_HPHASE1 );
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xil_printf("CRESAMPLE_COEF12_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF13_HPHASE1 );
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xil_printf("CRESAMPLE_COEF13_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF14_HPHASE1 );
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xil_printf("CRESAMPLE_COEF14_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF15_HPHASE1 );
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xil_printf("CRESAMPLE_COEF15_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF16_HPHASE1 );
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xil_printf("CRESAMPLE_COEF16_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF17_HPHASE1 );
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xil_printf("CRESAMPLE_COEF17_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF18_HPHASE1 );
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xil_printf("CRESAMPLE_COEF18_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF19_HPHASE1 );
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xil_printf("CRESAMPLE_COEF19_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF20_HPHASE1 );
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xil_printf("CRESAMPLE_COEF20_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF21_HPHASE1 );
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xil_printf("CRESAMPLE_COEF21_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF22_HPHASE1 );
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xil_printf("CRESAMPLE_COEF22_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF23_HPHASE1 );
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xil_printf("CRESAMPLE_COEF23_HPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF00_VPHASE0 );
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xil_printf("CRESAMPLE_COEF00_VPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF01_VPHASE0 );
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xil_printf("CRESAMPLE_COEF01_VPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF02_VPHASE0 );
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xil_printf("CRESAMPLE_COEF02_VPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF03_VPHASE0 );
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xil_printf("CRESAMPLE_COEF03_VPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF04_VPHASE0 );
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xil_printf("CRESAMPLE_COEF04_VPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF05_VPHASE0 );
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xil_printf("CRESAMPLE_COEF05_VPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF06_VPHASE0 );
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xil_printf("CRESAMPLE_COEF06_VPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF07_VPHASE0 );
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xil_printf("CRESAMPLE_COEF07_VPHASE0 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF00_VPHASE1 );
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xil_printf("CRESAMPLE_COEF00_VPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF01_VPHASE1 );
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xil_printf("CRESAMPLE_COEF01_VPHASE1 : %8d\r\n", reg_val);
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reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF02_VPHASE1 );
|
||||
xil_printf("CRESAMPLE_COEF02_VPHASE1 : %8d\r\n", reg_val);
|
||||
reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF03_VPHASE1 );
|
||||
xil_printf("CRESAMPLE_COEF03_VPHASE1 : %8d\r\n", reg_val);
|
||||
reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF04_VPHASE1 );
|
||||
xil_printf("CRESAMPLE_COEF04_VPHASE1 : %8d\r\n", reg_val);
|
||||
reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF05_VPHASE1 );
|
||||
xil_printf("CRESAMPLE_COEF05_VPHASE1 : %8d\r\n", reg_val);
|
||||
reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF06_VPHASE1 );
|
||||
xil_printf("CRESAMPLE_COEF06_VPHASE1 : %8d\r\n", reg_val);
|
||||
reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF07_VPHASE1 );
|
||||
xil_printf("CRESAMPLE_COEF07_VPHASE1 : %8d\r\n", reg_val);
|
||||
|
||||
xil_printf("Press Space to continue!\r\n", reg_val);
|
||||
while (inchar != ' ') inchar = inbyte();
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
//
|
||||
// This is the main function for the Chroma Resampler example.
|
||||
//
|
||||
/*****************************************************************************/
|
||||
int main(void)
|
||||
{
|
||||
//Print the current settings for the Chroma Resampler core
|
||||
report_cresample_settings(XPAR_CRESAMPLE_0_BASEADDR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
17
XilinxProcessorIPLib/drivers/cresample/examples/index.html
Executable file
17
XilinxProcessorIPLib/drivers/cresample/examples/index.html
Executable file
|
|
@ -0,0 +1,17 @@
|
|||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
|
||||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Language" content="en-us">
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
|
||||
<title>Driver example applications</title>
|
||||
<link rel="stylesheet" type="text/css" href="../help.css">
|
||||
</head>
|
||||
<body bgcolor="#FFFFFF">
|
||||
<h1> Example Applications for the driver cresample_v3_0 </h1>
|
||||
<HR>
|
||||
<ul>
|
||||
<li>example.c <a href="example.c">(source)</a> </li>
|
||||
</ul>
|
||||
<p><font face="Times New Roman" color="#800000">Copyright © 1995-2014 Xilinx, Inc. All rights reserved.</font></p>
|
||||
</body>
|
||||
</html>
|
||||
29
XilinxProcessorIPLib/drivers/cresample/src/Makefile
Executable file
29
XilinxProcessorIPLib/drivers/cresample/src/Makefile
Executable file
|
|
@ -0,0 +1,29 @@
|
|||
COMPILER=
|
||||
ARCHIVER=
|
||||
CP=cp
|
||||
COMPILER_FLAGS=
|
||||
EXTRA_COMPILER_FLAGS=
|
||||
LIB=libxil.a
|
||||
LEVEL=0
|
||||
|
||||
RELEASEDIR=../../../lib
|
||||
INCLUDEDIR=../../../include
|
||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
||||
|
||||
INCLUDEFILES=*.h
|
||||
LIBSOURCES=*.c
|
||||
|
||||
OUTS = *.o
|
||||
|
||||
libs:
|
||||
echo "Compiling cresample"
|
||||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
|
||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
||||
make clean
|
||||
|
||||
include:
|
||||
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
|
||||
|
||||
clean:
|
||||
rm -rf ${OUTS}
|
||||
|
||||
582
XilinxProcessorIPLib/drivers/cresample/src/cresample.c
Executable file
582
XilinxProcessorIPLib/drivers/cresample/src/cresample.c
Executable file
|
|
@ -0,0 +1,582 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
*
|
||||
* @file cresample.c
|
||||
*
|
||||
* This is main code of Xilinx Chroma Resampler (CRESAMPLE)
|
||||
* device driver. Please see cresample.h for more details of the driver.
|
||||
*
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a gaborz 08/04/11 Updated for CRESAMPLE V1.0
|
||||
* 2.00a vyc 04/24/12 Updated for CRESAMPLE V2.00.a
|
||||
* 2.00a vyc 07/25/12 Switched from Xuint32 to u32
|
||||
* 2.00a vyc 10/16/12 Switch order of functions to remove compile warning
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "cresample.h"
|
||||
#include "xenv.h"
|
||||
|
||||
/*****************************************************************************/
|
||||
// Note: Many functions are currently implemented as high-performance macros
|
||||
// within cresample.h
|
||||
/*****************************************************************************/
|
||||
|
||||
void clear_coef_values(u32 BaseAddress)
|
||||
{
|
||||
// set all coefficient values to 0
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF08_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF09_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF10_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF11_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF12_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF13_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF14_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF15_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF16_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF17_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF18_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF19_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF20_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF21_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF22_HPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF23_HPHASE0, 0);
|
||||
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF08_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF09_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF10_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF11_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF12_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF13_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF14_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF15_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF16_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF17_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF18_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF19_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF20_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF21_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF22_HPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF23_HPHASE1, 0);
|
||||
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_VPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_VPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_VPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_VPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_VPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_VPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_VPHASE0, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_VPHASE0, 0);
|
||||
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_VPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_VPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_VPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_VPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_VPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_VPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_VPHASE1, 0);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_VPHASE1, 0);
|
||||
}
|
||||
|
||||
void configure_444_to_422(u32 BaseAddress, int NUM_H_TAPS, int *coef_vector )
|
||||
{
|
||||
// clear out existing coefficient register values
|
||||
clear_coef_values(BaseAddress);
|
||||
|
||||
// set new coefficient register values from coef_vector
|
||||
if (NUM_H_TAPS > 0) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_HPHASE0, coef_vector[0]);
|
||||
}
|
||||
if (NUM_H_TAPS > 1) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_HPHASE0, coef_vector[1]);
|
||||
}
|
||||
if (NUM_H_TAPS > 2) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_HPHASE0, coef_vector[2]);
|
||||
}
|
||||
if (NUM_H_TAPS > 3) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_HPHASE0, coef_vector[3]);
|
||||
}
|
||||
if (NUM_H_TAPS > 4) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_HPHASE0, coef_vector[4]);
|
||||
}
|
||||
if (NUM_H_TAPS > 5) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_HPHASE0, coef_vector[5]);
|
||||
}
|
||||
if (NUM_H_TAPS > 6) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_HPHASE0, coef_vector[6]);
|
||||
}
|
||||
if (NUM_H_TAPS > 7) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_HPHASE0, coef_vector[7]);
|
||||
}
|
||||
if (NUM_H_TAPS > 8) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF08_HPHASE0, coef_vector[8]);
|
||||
}
|
||||
if (NUM_H_TAPS > 9) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF09_HPHASE0, coef_vector[9]);
|
||||
}
|
||||
if (NUM_H_TAPS > 10) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF10_HPHASE0, coef_vector[10]);
|
||||
}
|
||||
if (NUM_H_TAPS > 11) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF11_HPHASE0, coef_vector[11]);
|
||||
}
|
||||
if (NUM_H_TAPS > 12) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF12_HPHASE0, coef_vector[12]);
|
||||
}
|
||||
if (NUM_H_TAPS > 13) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF13_HPHASE0, coef_vector[13]);
|
||||
}
|
||||
if (NUM_H_TAPS > 14) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF14_HPHASE0, coef_vector[14]);
|
||||
}
|
||||
if (NUM_H_TAPS > 15) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF15_HPHASE0, coef_vector[15]);
|
||||
}
|
||||
if (NUM_H_TAPS > 16) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF16_HPHASE0, coef_vector[16]);
|
||||
}
|
||||
if (NUM_H_TAPS > 17) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF17_HPHASE0, coef_vector[17]);
|
||||
}
|
||||
if (NUM_H_TAPS > 18) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF18_HPHASE0, coef_vector[18]);
|
||||
}
|
||||
if (NUM_H_TAPS > 19) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF19_HPHASE0, coef_vector[19]);
|
||||
}
|
||||
if (NUM_H_TAPS > 20) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF20_HPHASE0, coef_vector[20]);
|
||||
}
|
||||
if (NUM_H_TAPS > 21) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF21_HPHASE0, coef_vector[21]);
|
||||
}
|
||||
if (NUM_H_TAPS > 22) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF22_HPHASE0, coef_vector[22]);
|
||||
}
|
||||
if (NUM_H_TAPS > 23) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF23_HPHASE0, coef_vector[23]);
|
||||
}
|
||||
}
|
||||
|
||||
void configure_422_to_444(u32 BaseAddress, int NUM_H_TAPS, int *coef_phase1_vector )
|
||||
{
|
||||
// clear out existing coefficient register values
|
||||
clear_coef_values(BaseAddress);
|
||||
|
||||
// set new coefficient register values from coef_vector
|
||||
if (NUM_H_TAPS > 0) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_HPHASE1, coef_phase1_vector[0]);
|
||||
}
|
||||
if (NUM_H_TAPS > 1) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_HPHASE1, coef_phase1_vector[1]);
|
||||
}
|
||||
if (NUM_H_TAPS > 2) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_HPHASE1, coef_phase1_vector[2]);
|
||||
}
|
||||
if (NUM_H_TAPS > 3) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_HPHASE1, coef_phase1_vector[3]);
|
||||
}
|
||||
if (NUM_H_TAPS > 4) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_HPHASE1, coef_phase1_vector[4]);
|
||||
}
|
||||
if (NUM_H_TAPS > 5) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_HPHASE1, coef_phase1_vector[5]);
|
||||
}
|
||||
if (NUM_H_TAPS > 6) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_HPHASE1, coef_phase1_vector[6]);
|
||||
}
|
||||
if (NUM_H_TAPS > 7) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_HPHASE1, coef_phase1_vector[7]);
|
||||
}
|
||||
if (NUM_H_TAPS > 8) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF08_HPHASE1, coef_phase1_vector[8]);
|
||||
}
|
||||
if (NUM_H_TAPS > 9) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF09_HPHASE1, coef_phase1_vector[9]);
|
||||
}
|
||||
if (NUM_H_TAPS > 10) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF10_HPHASE1, coef_phase1_vector[10]);
|
||||
}
|
||||
if (NUM_H_TAPS > 11) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF11_HPHASE1, coef_phase1_vector[11]);
|
||||
}
|
||||
if (NUM_H_TAPS > 12) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF12_HPHASE1, coef_phase1_vector[12]);
|
||||
}
|
||||
if (NUM_H_TAPS > 13) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF13_HPHASE1, coef_phase1_vector[13]);
|
||||
}
|
||||
if (NUM_H_TAPS > 14) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF14_HPHASE1, coef_phase1_vector[14]);
|
||||
}
|
||||
if (NUM_H_TAPS > 15) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF15_HPHASE1, coef_phase1_vector[15]);
|
||||
}
|
||||
if (NUM_H_TAPS > 16) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF16_HPHASE1, coef_phase1_vector[16]);
|
||||
}
|
||||
if (NUM_H_TAPS > 17) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF17_HPHASE1, coef_phase1_vector[17]);
|
||||
}
|
||||
if (NUM_H_TAPS > 18) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF18_HPHASE1, coef_phase1_vector[18]);
|
||||
}
|
||||
if (NUM_H_TAPS > 19) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF19_HPHASE1, coef_phase1_vector[19]);
|
||||
}
|
||||
if (NUM_H_TAPS > 20) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF20_HPHASE1, coef_phase1_vector[20]);
|
||||
}
|
||||
if (NUM_H_TAPS > 21) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF21_HPHASE1, coef_phase1_vector[21]);
|
||||
}
|
||||
if (NUM_H_TAPS > 22) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF22_HPHASE1, coef_phase1_vector[22]);
|
||||
}
|
||||
if (NUM_H_TAPS > 23) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF23_HPHASE1, coef_phase1_vector[23]);
|
||||
}
|
||||
}
|
||||
|
||||
void configure_422_to_420(u32 BaseAddress, int NUM_V_TAPS, int *coef_vector )
|
||||
{
|
||||
// clear out existing coefficient register values
|
||||
clear_coef_values(BaseAddress);
|
||||
|
||||
// set new coefficient register values from coef_vector
|
||||
if (NUM_V_TAPS > 0) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_VPHASE0, coef_vector[0]);
|
||||
}
|
||||
if (NUM_V_TAPS > 1) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_VPHASE0, coef_vector[1]);
|
||||
}
|
||||
if (NUM_V_TAPS > 2) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_VPHASE0, coef_vector[2]);
|
||||
}
|
||||
if (NUM_V_TAPS > 3) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_VPHASE0, coef_vector[3]);
|
||||
}
|
||||
if (NUM_V_TAPS > 4) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_VPHASE0, coef_vector[4]);
|
||||
}
|
||||
if (NUM_V_TAPS > 5) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_VPHASE0, coef_vector[5]);
|
||||
}
|
||||
if (NUM_V_TAPS > 6) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_VPHASE0, coef_vector[6]);
|
||||
}
|
||||
if (NUM_V_TAPS > 7) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_VPHASE0, coef_vector[7]);
|
||||
}
|
||||
}
|
||||
|
||||
void configure_420_to_422(u32 BaseAddress, int NUM_V_TAPS, int *coef_phase0_vector, int *coef_phase1_vector )
|
||||
{
|
||||
// clear out existing coefficient register values
|
||||
clear_coef_values(BaseAddress);
|
||||
|
||||
// set new coefficient register values from coef_vector
|
||||
if (NUM_V_TAPS > 0) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_VPHASE0, coef_phase0_vector[0]);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_VPHASE1, coef_phase1_vector[0]);
|
||||
}
|
||||
if (NUM_V_TAPS > 1) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_VPHASE0, coef_phase0_vector[1]);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_VPHASE1, coef_phase1_vector[1]);
|
||||
}
|
||||
if (NUM_V_TAPS > 2) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_VPHASE0, coef_phase0_vector[2]);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_VPHASE1, coef_phase1_vector[2]);
|
||||
}
|
||||
if (NUM_V_TAPS > 3) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_VPHASE0, coef_phase0_vector[3]);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_VPHASE1, coef_phase1_vector[3]);
|
||||
}
|
||||
if (NUM_V_TAPS > 4) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_VPHASE0, coef_phase0_vector[4]);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_VPHASE1, coef_phase1_vector[4]);
|
||||
}
|
||||
if (NUM_V_TAPS > 5) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_VPHASE0, coef_phase0_vector[5]);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_VPHASE1, coef_phase1_vector[5]);
|
||||
}
|
||||
if (NUM_V_TAPS > 6) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_VPHASE0, coef_phase0_vector[6]);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_VPHASE1, coef_phase1_vector[6]);
|
||||
}
|
||||
if (NUM_V_TAPS > 7) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_VPHASE0, coef_phase0_vector[7]);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_VPHASE1, coef_phase1_vector[7]);
|
||||
}
|
||||
}
|
||||
|
||||
void configure_444_to_420(u32 BaseAddress, int NUM_H_TAPS, int NUM_V_TAPS, int *hcoef_vector, int *vcoef_vector )
|
||||
{
|
||||
// clear out existing coefficient register values
|
||||
clear_coef_values(BaseAddress);
|
||||
|
||||
// set new coefficient register values from coef_vector
|
||||
if (NUM_H_TAPS > 0) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_HPHASE0, hcoef_vector[0]);
|
||||
}
|
||||
if (NUM_H_TAPS > 1) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_HPHASE0, hcoef_vector[1]);
|
||||
}
|
||||
if (NUM_H_TAPS > 2) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_HPHASE0, hcoef_vector[2]);
|
||||
}
|
||||
if (NUM_H_TAPS > 3) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_HPHASE0, hcoef_vector[3]);
|
||||
}
|
||||
if (NUM_H_TAPS > 4) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_HPHASE0, hcoef_vector[4]);
|
||||
}
|
||||
if (NUM_H_TAPS > 5) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_HPHASE0, hcoef_vector[5]);
|
||||
}
|
||||
if (NUM_H_TAPS > 6) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_HPHASE0, hcoef_vector[6]);
|
||||
}
|
||||
if (NUM_H_TAPS > 7) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_HPHASE0, hcoef_vector[7]);
|
||||
}
|
||||
if (NUM_H_TAPS > 8) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF08_HPHASE0, hcoef_vector[8]);
|
||||
}
|
||||
if (NUM_H_TAPS > 9) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF09_HPHASE0, hcoef_vector[9]);
|
||||
}
|
||||
if (NUM_H_TAPS > 10) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF10_HPHASE0, hcoef_vector[10]);
|
||||
}
|
||||
if (NUM_H_TAPS > 11) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF11_HPHASE0, hcoef_vector[11]);
|
||||
}
|
||||
if (NUM_H_TAPS > 12) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF12_HPHASE0, hcoef_vector[12]);
|
||||
}
|
||||
if (NUM_H_TAPS > 13) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF13_HPHASE0, hcoef_vector[13]);
|
||||
}
|
||||
if (NUM_H_TAPS > 14) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF14_HPHASE0, hcoef_vector[14]);
|
||||
}
|
||||
if (NUM_H_TAPS > 15) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF15_HPHASE0, hcoef_vector[15]);
|
||||
}
|
||||
if (NUM_H_TAPS > 16) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF16_HPHASE0, hcoef_vector[16]);
|
||||
}
|
||||
if (NUM_H_TAPS > 17) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF17_HPHASE0, hcoef_vector[17]);
|
||||
}
|
||||
if (NUM_H_TAPS > 18) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF18_HPHASE0, hcoef_vector[18]);
|
||||
}
|
||||
if (NUM_H_TAPS > 19) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF19_HPHASE0, hcoef_vector[19]);
|
||||
}
|
||||
if (NUM_H_TAPS > 20) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF20_HPHASE0, hcoef_vector[20]);
|
||||
}
|
||||
if (NUM_H_TAPS > 21) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF21_HPHASE0, hcoef_vector[21]);
|
||||
}
|
||||
if (NUM_H_TAPS > 22) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF22_HPHASE0, hcoef_vector[22]);
|
||||
}
|
||||
if (NUM_H_TAPS > 23) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF23_HPHASE0, hcoef_vector[23]);
|
||||
}
|
||||
|
||||
if (NUM_V_TAPS > 0) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_VPHASE0, vcoef_vector[0]);
|
||||
}
|
||||
if (NUM_V_TAPS > 1) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_VPHASE0, vcoef_vector[1]);
|
||||
}
|
||||
if (NUM_V_TAPS > 2) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_VPHASE0, vcoef_vector[2]);
|
||||
}
|
||||
if (NUM_V_TAPS > 3) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_VPHASE0, vcoef_vector[3]);
|
||||
}
|
||||
if (NUM_V_TAPS > 4) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_VPHASE0, vcoef_vector[4]);
|
||||
}
|
||||
if (NUM_V_TAPS > 5) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_VPHASE0, vcoef_vector[5]);
|
||||
}
|
||||
if (NUM_V_TAPS > 6) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_VPHASE0, vcoef_vector[6]);
|
||||
}
|
||||
if (NUM_V_TAPS > 7) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_VPHASE0, vcoef_vector[7]);
|
||||
}
|
||||
}
|
||||
|
||||
void configure_420_to_444(u32 BaseAddress, int NUM_H_TAPS, int NUM_V_TAPS, int *hcoef_phase1_vector, int *vcoef_phase0_vector, int *vcoef_phase1_vector )
|
||||
{
|
||||
// clear out existing coefficient register values
|
||||
clear_coef_values(BaseAddress);
|
||||
|
||||
// set new coefficient register values from coef_vector
|
||||
if (NUM_V_TAPS > 0) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_VPHASE0, vcoef_phase0_vector[0]);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_VPHASE1, vcoef_phase1_vector[0]);
|
||||
}
|
||||
if (NUM_V_TAPS > 1) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_VPHASE0, vcoef_phase0_vector[1]);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_VPHASE1, vcoef_phase1_vector[1]);
|
||||
}
|
||||
if (NUM_V_TAPS > 2) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_VPHASE0, vcoef_phase0_vector[2]);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_VPHASE1, vcoef_phase1_vector[2]);
|
||||
}
|
||||
if (NUM_V_TAPS > 3) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_VPHASE0, vcoef_phase0_vector[3]);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_VPHASE1, vcoef_phase1_vector[3]);
|
||||
}
|
||||
if (NUM_V_TAPS > 4) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_VPHASE0, vcoef_phase0_vector[4]);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_VPHASE1, vcoef_phase1_vector[4]);
|
||||
}
|
||||
if (NUM_V_TAPS > 5) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_VPHASE0, vcoef_phase0_vector[5]);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_VPHASE1, vcoef_phase1_vector[5]);
|
||||
}
|
||||
if (NUM_V_TAPS > 6) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_VPHASE0, vcoef_phase0_vector[6]);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_VPHASE1, vcoef_phase1_vector[6]);
|
||||
}
|
||||
if (NUM_V_TAPS > 7) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_VPHASE0, vcoef_phase0_vector[7]);
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_VPHASE1, vcoef_phase1_vector[7]);
|
||||
}
|
||||
|
||||
if (NUM_H_TAPS > 0) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_HPHASE1, hcoef_phase1_vector[0]);
|
||||
}
|
||||
if (NUM_H_TAPS > 1) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_HPHASE1, hcoef_phase1_vector[1]);
|
||||
}
|
||||
if (NUM_H_TAPS > 2) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_HPHASE1, hcoef_phase1_vector[2]);
|
||||
}
|
||||
if (NUM_H_TAPS > 3) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_HPHASE1, hcoef_phase1_vector[3]);
|
||||
}
|
||||
if (NUM_H_TAPS > 4) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_HPHASE1, hcoef_phase1_vector[4]);
|
||||
}
|
||||
if (NUM_H_TAPS > 5) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_HPHASE1, hcoef_phase1_vector[5]);
|
||||
}
|
||||
if (NUM_H_TAPS > 6) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_HPHASE1, hcoef_phase1_vector[6]);
|
||||
}
|
||||
if (NUM_H_TAPS > 7) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_HPHASE1, hcoef_phase1_vector[7]);
|
||||
}
|
||||
if (NUM_H_TAPS > 8) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF08_HPHASE1, hcoef_phase1_vector[8]);
|
||||
}
|
||||
if (NUM_H_TAPS > 9) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF09_HPHASE1, hcoef_phase1_vector[9]);
|
||||
}
|
||||
if (NUM_H_TAPS > 10) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF10_HPHASE1, hcoef_phase1_vector[10]);
|
||||
}
|
||||
if (NUM_H_TAPS > 11) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF11_HPHASE1, hcoef_phase1_vector[11]);
|
||||
}
|
||||
if (NUM_H_TAPS > 12) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF12_HPHASE1, hcoef_phase1_vector[12]);
|
||||
}
|
||||
if (NUM_H_TAPS > 13) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF13_HPHASE1, hcoef_phase1_vector[13]);
|
||||
}
|
||||
if (NUM_H_TAPS > 14) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF14_HPHASE1, hcoef_phase1_vector[14]);
|
||||
}
|
||||
if (NUM_H_TAPS > 15) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF15_HPHASE1, hcoef_phase1_vector[15]);
|
||||
}
|
||||
if (NUM_H_TAPS > 16) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF16_HPHASE1, hcoef_phase1_vector[16]);
|
||||
}
|
||||
if (NUM_H_TAPS > 17) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF17_HPHASE1, hcoef_phase1_vector[17]);
|
||||
}
|
||||
if (NUM_H_TAPS > 18) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF18_HPHASE1, hcoef_phase1_vector[18]);
|
||||
}
|
||||
if (NUM_H_TAPS > 19) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF19_HPHASE1, hcoef_phase1_vector[19]);
|
||||
}
|
||||
if (NUM_H_TAPS > 20) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF20_HPHASE1, hcoef_phase1_vector[20]);
|
||||
}
|
||||
if (NUM_H_TAPS > 21) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF21_HPHASE1, hcoef_phase1_vector[21]);
|
||||
}
|
||||
if (NUM_H_TAPS > 22) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF22_HPHASE1, hcoef_phase1_vector[22]);
|
||||
}
|
||||
if (NUM_H_TAPS > 23) {
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF23_HPHASE1, hcoef_phase1_vector[23]);
|
||||
}
|
||||
}
|
||||
|
||||
359
XilinxProcessorIPLib/drivers/cresample/src/cresample.h
Executable file
359
XilinxProcessorIPLib/drivers/cresample/src/cresample.h
Executable file
|
|
@ -0,0 +1,359 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
*
|
||||
* @file cresample.h
|
||||
*
|
||||
* This header file contains identifiers and register-level driver functions (or
|
||||
* macros) that can be used to access the Xilinx Chroma Resampler core instance.
|
||||
*
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 2.00a vy 04/24/12 Updated for version 2.00.a
|
||||
* Converted from xio.h to xil_io.h, translating
|
||||
* basic type, MB cache functions, exceptions and
|
||||
* assertion to xil_io format.
|
||||
* 1.00a vy 10/22/10 Initial version
|
||||
* 3.0 adk 19/12/13 Updated as per the New Tcl API's
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef CRESAMPLE_DRIVER_H /* prevent circular inclusions */
|
||||
#define CRESAMPLE_DRIVER_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_io.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**
|
||||
* Register Offsets
|
||||
*/
|
||||
/* General Control Registers */
|
||||
#define CRESAMPLE_CONTROL 0x0000 /**< Control */
|
||||
#define CRESAMPLE_STATUS 0x0004 /**< Status */
|
||||
#define CRESAMPLE_ERROR 0x0008 /**< Error */
|
||||
#define CRESAMPLE_IRQ_ENABLE 0x000C /**< IRQ Enable */
|
||||
#define CRESAMPLE_VERSION 0x0010 /**< Version */
|
||||
#define CRESAMPLE_SYSDEBUG0 0x0014 /**< System Debug 0 */
|
||||
#define CRESAMPLE_SYSDEBUG1 0x0018 /**< System Debug 1 */
|
||||
#define CRESAMPLE_SYSDEBUG2 0x001C /**< System Debug 2 */
|
||||
/* Timing Control Registers */
|
||||
#define CRESAMPLE_ACTIVE_SIZE 0x0020 /**< Horizontal and Vertical Active Frame Size */
|
||||
#define CRESAMPLE_ENCODING 0x0028 /**< Frame Encoding */
|
||||
/* Core Specific Registers */
|
||||
#define CRESAMPLE_COEF00_HPHASE0 0x0100 /**< Coefficient 00 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF01_HPHASE0 0x0104 /**< Coefficient 01 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF02_HPHASE0 0x0108 /**< Coefficient 02 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF03_HPHASE0 0x010C /**< Coefficient 03 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF04_HPHASE0 0x0110 /**< Coefficient 04 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF05_HPHASE0 0x0114 /**< Coefficient 05 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF06_HPHASE0 0x0118 /**< Coefficient 06 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF07_HPHASE0 0x011C /**< Coefficient 07 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF08_HPHASE0 0x0120 /**< Coefficient 08 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF09_HPHASE0 0x0124 /**< Coefficient 09 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF10_HPHASE0 0x0128 /**< Coefficient 10 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF11_HPHASE0 0x012C /**< Coefficient 11 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF12_HPHASE0 0x0130 /**< Coefficient 12 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF13_HPHASE0 0x0134 /**< Coefficient 13 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF14_HPHASE0 0x0138 /**< Coefficient 14 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF15_HPHASE0 0x013C /**< Coefficient 15 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF16_HPHASE0 0x0140 /**< Coefficient 16 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF17_HPHASE0 0x0144 /**< Coefficient 17 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF18_HPHASE0 0x0148 /**< Coefficient 18 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF19_HPHASE0 0x014C /**< Coefficient 19 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF20_HPHASE0 0x0150 /**< Coefficient 20 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF21_HPHASE0 0x0154 /**< Coefficient 21 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF22_HPHASE0 0x0158 /**< Coefficient 22 of Horizontal Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF23_HPHASE0 0x015C /**< Coefficient 23 of Horizontal Phase 0 Filter */
|
||||
|
||||
#define CRESAMPLE_COEF00_HPHASE1 0x0160 /**< Coefficient 00 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF01_HPHASE1 0x0164 /**< Coefficient 01 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF02_HPHASE1 0x0168 /**< Coefficient 02 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF03_HPHASE1 0x016C /**< Coefficient 03 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF04_HPHASE1 0x0170 /**< Coefficient 04 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF05_HPHASE1 0x0174 /**< Coefficient 05 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF06_HPHASE1 0x0178 /**< Coefficient 06 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF07_HPHASE1 0x017C /**< Coefficient 07 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF08_HPHASE1 0x0180 /**< Coefficient 08 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF09_HPHASE1 0x0184 /**< Coefficient 09 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF10_HPHASE1 0x0188 /**< Coefficient 10 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF11_HPHASE1 0x018C /**< Coefficient 11 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF12_HPHASE1 0x0190 /**< Coefficient 12 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF13_HPHASE1 0x0194 /**< Coefficient 13 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF14_HPHASE1 0x0198 /**< Coefficient 14 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF15_HPHASE1 0x019C /**< Coefficient 15 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF16_HPHASE1 0x01A0 /**< Coefficient 16 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF17_HPHASE1 0x01A4 /**< Coefficient 17 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF18_HPHASE1 0x01A8 /**< Coefficient 18 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF19_HPHASE1 0x01AC /**< Coefficient 19 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF20_HPHASE1 0x01B0 /**< Coefficient 20 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF21_HPHASE1 0x01B4 /**< Coefficient 21 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF22_HPHASE1 0x01B8 /**< Coefficient 22 of Horizontal Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF23_HPHASE1 0x01BC /**< Coefficient 23 of Horizontal Phase 1 Filter */
|
||||
|
||||
#define CRESAMPLE_COEF00_VPHASE0 0x01C0 /**< Coefficient 00 of Vertical Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF01_VPHASE0 0x01C4 /**< Coefficient 01 of Vertical Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF02_VPHASE0 0x01C8 /**< Coefficient 02 of Vertical Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF03_VPHASE0 0x01CC /**< Coefficient 03 of Vertical Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF04_VPHASE0 0x01D0 /**< Coefficient 04 of Vertical Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF05_VPHASE0 0x01D4 /**< Coefficient 05 of Vertical Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF06_VPHASE0 0x01D8 /**< Coefficient 06 of Vertical Phase 0 Filter */
|
||||
#define CRESAMPLE_COEF07_VPHASE0 0x01DC /**< Coefficient 07 of Vertical Phase 0 Filter */
|
||||
|
||||
#define CRESAMPLE_COEF00_VPHASE1 0x01E0 /**< Coefficient 00 of Vertical Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF01_VPHASE1 0x01E4 /**< Coefficient 01 of Vertical Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF02_VPHASE1 0x01E8 /**< Coefficient 02 of Vertical Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF03_VPHASE1 0x01EC /**< Coefficient 03 of Vertical Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF04_VPHASE1 0x01F0 /**< Coefficient 04 of Vertical Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF05_VPHASE1 0x01F4 /**< Coefficient 05 of Vertical Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF06_VPHASE1 0x01F8 /**< Coefficient 06 of Vertical Phase 1 Filter */
|
||||
#define CRESAMPLE_COEF07_VPHASE1 0x01FC /**< Coefficient 07 of Vertical Phase 1 Filter */
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* Control Register bit definition
|
||||
*/
|
||||
#define CRESAMPLE_CTL_EN_MASK 0x00000001 /**< Enable */
|
||||
#define CRESAMPLE_CTL_RU_MASK 0x00000002 /**< Register Update */
|
||||
#define CRESAMPLE_CTL_AUTORESET 0x40000000 /**< Software Reset - Auto-synchronize to SOF */
|
||||
#define CRESAMPLE_CTL_RESET 0x80000000 /**< Software Reset - Instantaneous */
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
#define CRESAMPLE_In32 Xil_In32
|
||||
#define CRESAMPLE_Out32 Xil_Out32
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Read the given register.
|
||||
*
|
||||
* @param BaseAddress is the Xilinx EDK base address of the Chroma Resampler core (from xparameters.h)
|
||||
* @param RegOffset is the register offset of the register (defined at top of this file)
|
||||
*
|
||||
* @return The 32-bit value of the register
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* u32 CRESAMPLE_ReadReg(u32 BaseAddress, u32 RegOffset)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define CRESAMPLE_ReadReg(BaseAddress, RegOffset) \
|
||||
CRESAMPLE_In32((BaseAddress) + (RegOffset))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Write the given register.
|
||||
*
|
||||
* @param BaseAddress is the Xilinx EDK base address of the Chroma Resampler core (from xparameters.h)
|
||||
* @param RegOffset is the register offset of the register (defined at top of this file)
|
||||
* @param Data is the 32-bit value to write to the register
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void CRESAMPLE_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define CRESAMPLE_WriteReg(BaseAddress, RegOffset, Data) \
|
||||
CRESAMPLE_Out32((BaseAddress) + (RegOffset), (Data))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro enables a Chroma Resampler core instance.
|
||||
*
|
||||
* @param BaseAddress is the Xilinx EDK base address of the Chroma Resampler core (from xparameters.h)
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void CRESAMPLE_Enable(u32 BaseAddress);
|
||||
*
|
||||
******************************************************************************/
|
||||
#define CRESAMPLE_Enable(BaseAddress) \
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_CONTROL, \
|
||||
CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_CONTROL) | \
|
||||
CRESAMPLE_CTL_EN_MASK)
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro disables a Chroma Resampler core instance.
|
||||
*
|
||||
* @param BaseAddress is the Xilinx EDK base address of the Chroma Resampler core (from xparameters.h)
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void CRESAMPLE_Disable(u32 BaseAddress);
|
||||
*
|
||||
******************************************************************************/
|
||||
#define CRESAMPLE_Disable(BaseAddress) \
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_CONTROL, \
|
||||
CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_CONTROL) & \
|
||||
~CRESAMPLE_CTL_EN_MASK)
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro commits all the register value changes made so far by the software
|
||||
* to the Chroma Resampler core instance. The registers will be automatically updated
|
||||
* on the next rising-edge of the SOF signal on the core.
|
||||
* It is up to the user to manually disable the register update after a sufficient
|
||||
* amount of time.
|
||||
*
|
||||
* This function only works when the Chroma Resampler core is enabled.
|
||||
*
|
||||
* @param BaseAddress is the Xilinx EDK base address of the Chroma Resampler core (from xparameters.h)
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void CRESAMPLE_RegUpdateEnable(u32 BaseAddress);
|
||||
*
|
||||
******************************************************************************/
|
||||
#define CRESAMPLE_RegUpdateEnable(BaseAddress) \
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_CONTROL, \
|
||||
CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_CONTROL) | \
|
||||
CRESAMPLE_CTL_RU_MASK)
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro prevents the Chroma Resampler core instance from committing recent changes made
|
||||
* so far by the software. When disabled, changes to other configuration registers
|
||||
* are stored, but do not effect the behavior of the core.
|
||||
*
|
||||
* This function only works when the Chroma Resampler core is enabled.
|
||||
*
|
||||
* @param BaseAddress is the Xilinx EDK base address of the Chroma Resampler core (from xparameters.h)
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void CRESAMPLE_RegUpdateDisable(u32 BaseAddress);
|
||||
*
|
||||
******************************************************************************/
|
||||
#define CRESAMPLE_RegUpdateDisable(BaseAddress) \
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_CONTROL, \
|
||||
CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_CONTROL) & \
|
||||
~CRESAMPLE_CTL_RU_MASK)
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
/**
|
||||
*
|
||||
* This macro resets a Chroma Resampler core instance. This reset effects the core immediately,
|
||||
* and may cause image tearing.
|
||||
*
|
||||
* This reset resets the Chroma Resampler's configuration registers, and holds the core's outputs
|
||||
* in their reset state until CRESAMPLE_ClearReset() is called.
|
||||
*
|
||||
*
|
||||
* @param BaseAddress is the Xilinx EDK base address of the Chroma Resampler core (from xparameters.h)
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void CRESAMPLE_Reset(u32 BaseAddress);
|
||||
*
|
||||
******************************************************************************/
|
||||
#define CRESAMPLE_Reset(BaseAddress) \
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_CONTROL, CRESAMPLE_CTL_RESET) \
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro clears the Chroma Resampler's reset flag (which is set using CRESAMPLE_Reset(), and
|
||||
* returns it to normal operation. This ClearReset effects the core immediately,
|
||||
* and may cause image tearing.
|
||||
*
|
||||
*
|
||||
* @param BaseAddress is the Xilinx EDK base address of the Chroma Resampler core (from xparameters.h)
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void CRESAMPLE_ClearReset(u32 BaseAddress);
|
||||
*
|
||||
******************************************************************************/
|
||||
#define CRESAMPLE_ClearReset(BaseAddress) \
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_CONTROL, 0) \
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro resets a Chroma Resampler core instance, but differs from CRESAMPLE_Reset() in that it
|
||||
* automatically synchronizes to the SOF input of the core to prevent tearing.
|
||||
*
|
||||
* On the next SOF following a call to CRESAMPLE_AutoSyncReset(),
|
||||
* all of the core's configuration registers and outputs will be reset, then the
|
||||
* reset flag will be immediately released, allowing the core to immediately resume
|
||||
* default operation.
|
||||
*
|
||||
* @param BaseAddress is the Xilinx EDK base address of the Chroma Resampler core (from xparameters.h)
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void CRESAMPLE_AutoSyncReset(u32 BaseAddress);
|
||||
*
|
||||
******************************************************************************/
|
||||
#define CRESAMPLE_AutoSyncReset(BaseAddress) \
|
||||
CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_CONTROL, CRESAMPLE_CTL_AUTORESET) \
|
||||
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
Loading…
Add table
Reference in a new issue