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dp: Added new register definitions.

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New registers in the DP v6.1 IP.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: K Krishna Deepak <kde@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion 2015-09-01 13:56:28 -07:00 • committed by Nava kishore Manne
parent 7247a49431
commit e1ce03e43a
1 changed files with 23 additions and 1 deletions
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24
XilinxProcessorIPLib/drivers/dp/src/xdp_hw.h
View file

@ -101,6 +101,7 @@
secondary link info. */ secondary link info. */
#define XDP_TX_FORCE_SCRAMBLER_RESET 0x0C0 /**< Force a scrambler reset. */ #define XDP_TX_FORCE_SCRAMBLER_RESET 0x0C0 /**< Force a scrambler reset. */
#define XDP_TX_MST_CONFIG 0x0D0 /**< Enable MST. */ #define XDP_TX_MST_CONFIG 0x0D0 /**< Enable MST. */
#define XDP_TX_LINE_RESET_DISABLE 0x0F0 /**< TX line reset disable. */
/* @} */ /* @} */
/** @name DPTX core registers: Core ID. /** @name DPTX core registers: Core ID.
@ -396,6 +397,10 @@
#define XDP_TX_MST_CONFIG_VCP_UPDATED_MASK \ #define XDP_TX_MST_CONFIG_VCP_UPDATED_MASK \
0x00000002 /**< The VC payload has been 0x00000002 /**< The VC payload has been
updated in the sink. */ updated in the sink. */
/* 0x0F0: TX_LINE_RESET_DISABLE */
#define XDP_TX_LINE_RESET_DISABLE_MASK 0x1 /**< Used to disable the end of
the line reset to the
internal video pipe. */
/* 0x0F8: VERSION */ /* 0x0F8: VERSION */
#define XDP_TX_VERSION_INTER_REV_MASK \ #define XDP_TX_VERSION_INTER_REV_MASK \
0x0000000F /**< Internal revision. */ 0x0000000F /**< Internal revision. */
@ -780,6 +785,7 @@
#define XDP_RX_AUX_CLK_DIVIDER 0x004 /**< Clock divider value for #define XDP_RX_AUX_CLK_DIVIDER 0x004 /**< Clock divider value for
generating the internal generating the internal
1MHz clock. */ 1MHz clock. */
#define XDP_RX_LINE_RESET_DISABLE 0x008 /**< RX line reset disable. */
#define XDP_RX_DTG_ENABLE 0x00C /**< Enables the display timing #define XDP_RX_DTG_ENABLE 0x00C /**< Enables the display timing
generator (DTG). */ generator (DTG). */
#define XDP_RX_USER_PIXEL_WIDTH 0x010 /**< Selects the width of the #define XDP_RX_USER_PIXEL_WIDTH 0x010 /**< Selects the width of the
@ -834,18 +840,24 @@
#define XDP_RX_INTERRUPT_CAUSE_1 0x048 /**< Indicates the cause of a #define XDP_RX_INTERRUPT_CAUSE_1 0x048 /**< Indicates the cause of a
pending host interrupts pending host interrupts
for streams 2, 3, 4. */ for streams 2, 3, 4. */
/* @} */
#define XDP_RX_HSYNC_WIDTH 0x050 /**< Controls the timing of the #define XDP_RX_HSYNC_WIDTH 0x050 /**< Controls the timing of the
active-high horizontal active-high horizontal
sync pulse generated sync pulse generated
by the display timing by the display timing
generator (DTG). */ generator (DTG). */
#define XDP_RX_VSYNC_WIDTH 0x058 /**< Controls the timing of the
active-high vertical
sync pulse generated
by the display timing
generator (DTG). */
#define XDP_RX_FAST_I2C_DIVIDER 0x060 /**< Fast I2C mode clock divider #define XDP_RX_FAST_I2C_DIVIDER 0x060 /**< Fast I2C mode clock divider
value. */ value. */
#define XDP_RX_MST_ALLOC 0x06C /**< Represents the content from #define XDP_RX_MST_ALLOC 0x06C /**< Represents the content from
the DPCD registers the DPCD registers
related to payload related to payload
allocation. */ allocation. */
/* @} */
/** @name DPRX core registers: DPCD fields. /** @name DPRX core registers: DPCD fields.
* @{ * @{
@ -962,6 +974,12 @@
#define XDP_RX_CDR_CONTROL_CONFIG 0x21C /**< Control the configuration #define XDP_RX_CDR_CONTROL_CONFIG 0x21C /**< Control the configuration
for clock and data for clock and data
recovery. */ recovery. */
#define XDP_RX_BS_IDLE_TIME 0x220 /**< Blanking start symbol idle
time - this value is
loaded as a timeout
counter for detecting
cable disconnect or
unplug events. */
#define XDP_RX_GT_DRP_COMMAND 0x2A0 /**< Provides access to the GT #define XDP_RX_GT_DRP_COMMAND 0x2A0 /**< Provides access to the GT
DRP ports. */ DRP ports. */
#define XDP_RX_GT_DRP_READ_DATA 0x2A4 /**< Provides access to GT DRP #define XDP_RX_GT_DRP_READ_DATA 0x2A4 /**< Provides access to GT DRP
@ -1193,6 +1211,10 @@
#define XDP_RX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT \ #define XDP_RX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT \
8 /**< Shift bits for AUX signal 8 /**< Shift bits for AUX signal
width filter. */ width filter. */
/* 0x008: RX_LINE_RESET_DISABLE */
#define XDP_RX_LINE_RESET_DISABLE_MASK 0x1 /**< Used to disable the end of
the line reset to the
internal video pipe. */
/* 0x010: USER_PIXEL_WIDTH */ /* 0x010: USER_PIXEL_WIDTH */
#define XDP_RX_USER_PIXEL_WIDTH_1 0x1 /**< Single pixel wide #define XDP_RX_USER_PIXEL_WIDTH_1 0x1 /**< Single pixel wide
interface. */ interface. */