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Update Tcl files to support MultiBd and Packaged Bd Designs

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Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Acked-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
This commit is contained in:
Nava kishore Manne 2015-07-28 17:03:55 +05:30 • committed by Nava kishore Manne
parent 5b9d1a3f61
commit e35699808d
45 changed files with 191 additions and 191 deletions
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50
ThirdParty/sw_services/lwip141/data/lwip141.tcl vendored
View file

@ -4,7 +4,7 @@ set use_emaclite_on_zynq 0
# emaclite hw requirements - interrupt needs to be connected
proc lwip_elite_hw_drc {libhandle emac} {
set emacname [common::get_property NAME $emac]
set intr_port [hsi::get_pins -of_objects [hsi::get_cells $emac] IP2INTC_Irpt]
set intr_port [hsi::get_pins -of_objects [hsi::get_cells -hier $emac] IP2INTC_Irpt]
if {[string compare -nocase $intr_port ""] == 0} {
error "ERROR: xps_ethernetlite core $emacname does not have its interrupt connected to interrupt controller. \
lwIP operates only in interrupt mode, so please connect the interrupt port to \
@ -42,9 +42,9 @@ proc lwip_elite_hw_drc {libhandle emac} {
# - if fifo, fifo intr (not verified)
proc lwip_temac_channel_hw_drc {libhandle emac irpt_name llink_name tx_csum_name rx_csum_name} {
set emacname [common::get_property NAME $emac]
set mhs_handle [hsi::get_cells $emac]
set mhs_handle [hsi::get_cells -hier $emac]
set intr_port [hsi::get_pins -of_objects [hsi::get_cells $emac] irpt_name]
set intr_port [hsi::get_pins -of_objects [hsi::get_cells -hier $emac] irpt_name]
if {[string compare -nocase $intr_port ""] == 0} {
error "ERROR: xps_ll_temac core $emacname does not have its interrupt connected to interrupt controller. \
lwIP requires that this interrupt line be connected to \
@ -103,7 +103,7 @@ proc lwip_temac_channel_hw_drc {libhandle emac irpt_name llink_name tx_csum_name
}
proc lwip_temac_hw_drc {libhandle emac} {
set emac_intr_port [hsi::get_pins -of_objects [hsi::get_cells $emac] TemacIntc0_Irpt]
set emac_intr_port [hsi::get_pins -of_objects [hsi::get_cells -hier $emac] TemacIntc0_Irpt]
set emac0_enabled "0"
if {$emac_intr_port != ""} { set emac0_enabled "1" }
if {$emac0_enabled == "1"} {
@ -123,9 +123,9 @@ proc lwip_temac_hw_drc {libhandle emac} {
proc lwip_axi_ethernet_hw_drc {libhandle emac} {
set emacname $emac
set mhs_handle [hsi::get_cells $emac]
set mhs_handle [hsi::get_cells -hier $emac]
set intr_port [hsi::get_pins -of_objects [hsi::get_cells $emac] INTERRUPT]
set intr_port [hsi::get_pins -of_objects [hsi::get_cells -hier $emac] INTERRUPT]
if {[string compare -nocase $intr_port ""] == 0} {
error "ERROR: axi_ethernet core $emacname does not have its interrupt connected to interrupt controller. \
lwIP requires that this interrupt line be connected to \
@ -204,7 +204,7 @@ proc lwip_axi_ethernet_hw_drc {libhandle emac} {
#--
proc lwip_hw_drc {libhandle emacs_list} {
foreach ip $emacs_list {
set iptype [common::get_property IP_NAME [get_cells $ip]]
set iptype [common::get_property IP_NAME [get_cells -hier $ip]]
if {$iptype == "xps_ethernetlite" || $iptype == "axi_ethernetlite"} {
lwip_elite_hw_drc $libhandle $ip
} elseif {$iptype == "xps_ll_temac"} {
@ -254,7 +254,7 @@ proc get_emac_periphs {processor} {
set emac_name [common::get_property NAME $periph]
# emac 0 is always enabled. just check for its interrupt port
set emac_intr_port [hsi::get_pins -of_objects [hsi::get_cells $periph] TemacIntc0_Irpt]
set emac_intr_port [hsi::get_pins -of_objects [hsi::get_cells -hier $periph] TemacIntc0_Irpt]
if {$emac_intr_port != ""} {
set emac0_enabled "1"
} else {
@ -265,7 +265,7 @@ proc get_emac_periphs {processor} {
# for emac 1, check C_TEMAC1_ENABLED and then its interrupt port
set emac1_on [common::get_property CONFIG.C_TEMAC1_ENABLED $periph "PARAMETER"]
if {$emac1_on == "1"} {
set emac_intr_port2 [hsi::get_pins -of_objects [hsi::get_cells $periph] TemacIntc1_Irpt]
set emac_intr_port2 [hsi::get_pins -of_objects [hsi::get_cells -hier $periph] TemacIntc1_Irpt]
if {$emac_intr_port2 != ""} {
set emac1_enabled "1"
} else {
@ -293,7 +293,7 @@ proc lwip_drc {libhandle} {
# find the list of xps_ethernetlite, xps_ll_temac, or axi_ethernet cores
set sw_processor [hsi::get_sw_processor]
set processor [hsi::get_cells [common::get_property HW_INSTANCE $sw_processor]]
set processor [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_processor]]
set emac_periphs_list [get_emac_periphs $processor]
@ -324,7 +324,7 @@ proc generate_lwip_opts {libhandle} {
global use_emaclite_on_zynq
set lwipopts_file "src/contrib/ports/xilinx/include/lwipopts.h"
set sw_processor [hsi::get_sw_processor]
set processor [hsi::get_cells [common::get_property HW_INSTANCE $sw_processor]]
set processor [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_processor]]
set processor_type [common::get_property IP_NAME $processor]
set emac_periphs_list [get_emac_periphs $processor]
@ -744,8 +744,8 @@ proc update_temac_topology {emac processor topologyvar} {
set topology(emac_type) "xemac_type_xps_ll_temac"
# find intc to which the interrupt line is connected
set emac_intr_port [hsi::get_pins -of_objects [hsi::get_cells $emac] TemacIntc0_Irpt]
set intr_ports [::hsm::utils::get_sink_pins [hsi::get_pins -of_objects [hsi::get_cells $emac] TemacIntc0_Irpt]]
set emac_intr_port [hsi::get_pins -of_objects [hsi::get_cells -hier $emac] TemacIntc0_Irpt]
set intr_ports [::hsm::utils::get_sink_pins [hsi::get_pins -of_objects [hsi::get_cells -hier $emac] TemacIntc0_Irpt]]
set l [llength $intr_ports]
@ -783,8 +783,8 @@ proc update_temac1_topology {emac processor topologyvar} {
set topology(emac_type) "xemac_type_xps_ll_temac"
# find intc to which the interrupt line is connected
set emac_intr_port [hsi::get_pins -of_objects [hsi::get_cells $emac] TemacIntc1_Irpt]
set mhs_handle [hsi::get_cells $emac]
set emac_intr_port [hsi::get_pins -of_objects [hsi::get_cells -hier $emac] TemacIntc1_Irpt]
set mhs_handle [hsi::get_cells -hier $emac]
set intr_ports [xget_connected_ports_handle $mhs_handle $emac_intr_port "sink"]
if { [llength $intr_ports] != 1 } {
@ -816,7 +816,7 @@ proc update_emaclite_topology {emac processor topologyvar} {
global use_emaclite_on_zynq
upvar $topologyvar topology
set sw_processor [hsi::get_sw_processor]
set processor [hsi::get_cells [common::get_property HW_INSTANCE $sw_processor]]
set processor [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_processor]]
set processor_type [common::get_property IP_NAME $processor]
set force_emaclite_on_zynq 0
@ -838,9 +838,9 @@ proc update_emaclite_topology {emac processor topologyvar} {
} else {
# find intc to which the interrupt line is connected
set emac_intr_port [hsi::get_pins -of_objects [hsi::get_cells $emac] IP2INTC_Irpt]
set mhs_handle [hsi::get_cells $emac]
set intr_ports [::hsm::utils::get_sink_pins [hsi::get_pins -of_objects [hsi::get_cells $emac] IP2INTC_Irpt]]
set emac_intr_port [hsi::get_pins -of_objects [hsi::get_cells -hier $emac] IP2INTC_Irpt]
set mhs_handle [hsi::get_cells -hier $emac]
set intr_ports [::hsm::utils::get_sink_pins [hsi::get_pins -of_objects [hsi::get_cells -hier $emac] IP2INTC_Irpt]]
if { [llength $intr_ports] != 1 } {
set emac_name [common::get_property NAME $emac]
@ -876,7 +876,7 @@ proc update_axi_ethernet_topology {emac processor topologyvar} {
set topology(emac_type) "xemac_type_axi_ethernet"
# find intc to which the interrupt line is connected
set emac_intr_port [hsi::get_pins -of_objects [hsi::get_cells $emac] INTERRUPT]
set emac_intr_port [hsi::get_pins -of_objects [hsi::get_cells -hier $emac] INTERRUPT]
set intc_handle [::hsi::utils::get_connected_intr_cntrl $emac $emac_intr_port]
set intc_periph_type [common::get_property IP_NAME $intc_handle]
set intc_name [common::get_property NAME $intc_handle]
@ -946,7 +946,7 @@ proc generate_topology_per_emac {fd topologyvar} {
proc generate_topology {libhandle} {
set sw_processor [hsi::get_sw_processor]
set processor [hsi::get_cells [common::get_property HW_INSTANCE $sw_processor]]
set processor [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_processor]]
set emac_periphs_list [get_emac_periphs $processor]
set tempcntr 0
@ -977,7 +977,7 @@ proc generate_topology {libhandle} {
generate_topology_per_emac $tfd topology
incr topology_size 1
} elseif {$iptype == "xps_ll_temac"} {
set emac_intr_port [hsi::get_pins -of_objects [hsi::get_cells $emac] TemacIntc0_Irpt]
set emac_intr_port [hsi::get_pins -of_objects [hsi::get_cells -hier $emac] TemacIntc0_Irpt]
set temac0 "0"
if {$emac_intr_port != ""} { set temac0 "1" }
if {$temac0 == "1"} {
@ -1020,7 +1020,7 @@ proc generate_adapterconfig_makefile {libhandle} {
global use_axieth_on_zynq
global use_emaclite_on_zynq
set sw_processor [hsi::get_sw_processor]
set processor [hsi::get_cells [common::get_property HW_INSTANCE $sw_processor]]
set processor [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_processor]]
set processor_type [common::get_property IP_NAME $processor]
set emac_periphs_list [get_emac_periphs $processor]
@ -1152,7 +1152,7 @@ proc generate_adapterconfig_include {libhandle} {
global use_axieth_on_zynq
global use_emaclite_on_zynq
set sw_processor [hsi::get_sw_processor]
set processor [hsi::get_cells [common::get_property HW_INSTANCE $sw_processor]]
set processor [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_processor]]
set processor_type [common::get_property IP_NAME $processor]
set emac_periphs_list [get_emac_periphs $processor]
@ -1275,7 +1275,7 @@ proc generate_adapterconfig_include {libhandle} {
}
proc axieth_target_periph {emac} {
set p2p_busifs_i [get_intf_pins -of_objects [get_cells $emac] -filter "TYPE==INITIATOR"]
set p2p_busifs_i [get_intf_pins -of_objects [get_cells -hier $emac] -filter "TYPE==INITIATOR"]
foreach p2p_busif $p2p_busifs_i {
set busif_name [string toupper [get_property NAME $p2p_busif]]
set conn_busif_handle [::hsi::utils::get_connected_intf $emac $busif_name]

6
XilinxProcessorIPLib/drivers/axicdma/data/axicdma_tapp.tcl
View file

@ -179,10 +179,10 @@ proc gen_testfunc_call {swproj mhsinst} {
set sg [get_property CONFIG.C_INCLUDE_SG $mhsinst]
if {$axicdmaintr == 1} {
set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells $ipname] -filter "TYPE==INTERRUPT"]
set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells -hier $ipname] -filter "TYPE==INTERRUPT"]
set intcname [::hsi::utils::get_connected_intr_cntrl $ipname $intr_pin_name]
set intcvar intc
set proc [get_property IP_NAME [hsi::get_cells [hsi::get_sw_processor]]]
set proc [get_property IP_NAME [hsi::get_cells -hier [hsi::get_sw_processor]]]
}
set testfunc_call ""
@ -355,7 +355,7 @@ proc gen_testfunc_call {swproj mhsinst} {
}
proc check_if_ddr_is_present {mhsinst} {
set ips [hsi::get_cells $mhsinst "*"]
set ips [hsi::get_cells -hier $mhsinst "*"]
set ddrpresent -1
set migddrpresent -1

12
XilinxProcessorIPLib/drivers/axiethernet/data/axiethernet.tcl
View file

@ -222,11 +222,11 @@ proc xdefine_axi_target_params {periphs file_handle} {
puts $file_handle [format "#define $canonical_name %s" $axi_fifo_baseaddr]
add_field_to_periph_config_struct $device_id $canonical_name
# FIFO Interrupts Handling
set int_pin [get_pins -of_objects [get_cells $tartget_per_name] INTERRUPT]
set int_pin [get_pins -of_objects [get_cells -hier $tartget_per_name] INTERRUPT]
set intc_periph_type [::hsi::utils::get_connected_intr_cntrl $tartget_per_name $int_pin]
set intc_name [get_property IP_NAME $intc_periph_type]
if { $intc_name != [format "ps7_scugic"] } {
set int_id [::hsi::utils::get_port_intr_id [get_cells $tartget_per_name] $int_pin]
set int_id [::hsi::utils::get_port_intr_id [get_cells -hier $tartget_per_name] $int_pin]
set canonical_name [format "XPAR_%s_CONNECTED_FIFO_INTR" $canonical_tag]
puts $file_handle [format "#define $canonical_name %d" $int_id]
add_field_to_periph_config_struct $device_id $canonical_name
@ -620,12 +620,12 @@ proc xdefine_temac_interrupt {file_handle periph device_id} {
# as connected to an interrupt controller
set interrupt_signal_name [get_property NAME $interrupt_port]
#set interrupt_signal [xget_hw_value $interrupt_port]
set intc_prt [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells $periph] INTERRUPT]]
set intc_prt [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $periph] INTERRUPT]]
# Make sure the interrupt signal was connected in this design. We assume
# at least one is. (could be a bug if user just wants polled mode)
if { $intc_prt != "" } {
set intc_periph [::hsi::utils::get_connected_intr_cntrl $periph [get_pins -of_objects [get_cells $periph] INTERRUPT] ]
set intc_periph [::hsi::utils::get_connected_intr_cntrl $periph [get_pins -of_objects [get_cells -hier $periph] INTERRUPT] ]
if {$intc_periph == ""} {
puts "Info: Axi Ethernet interrupt not connected to intc\n"
# No interrupts were connected, so add dummy entry to the config structure
@ -669,8 +669,8 @@ proc xdefine_temac_interrupt {file_handle periph device_id} {
proc generate_sgmii_params {drv_handle file_name} {
set file_handle [::hsi::utils::open_include_file $file_name]
set phy_type [common::get_property CONFIG.PHY_TYPE [get_cells $drv_handle]]
set phyaddr [common::get_property CONFIG.PHYADDR [get_cells $drv_handle]]
set phy_type [common::get_property CONFIG.PHY_TYPE [get_cells -hier $drv_handle]]
set phyaddr [common::get_property CONFIG.PHYADDR [get_cells -hier $drv_handle]]
set phyaddr [::hsi::utils::convert_binary_to_decimal $phyaddr]
if {[llength $phyaddr] == 0} {
set phyaddr 0

8
XilinxProcessorIPLib/drivers/axiethernet/data/axiethernet_tapp.tcl
View file

@ -175,10 +175,10 @@ proc gen_testfunc_call {swproj mhsinst} {
set dma_ipname [get_dma_info $mhsinst "name"]
if {$ifintr == 1} {
set intr_pin_name [get_pins -of_objects [get_cells $ipname] INTERRUPT]
set intr_pin_name [get_pins -of_objects [get_cells -hier $ipname] INTERRUPT]
set intcname [::hsi::utils::get_connected_intr_cntrl $ipname $intr_pin_name]
set intcvar intc
set proc [get_property IP_NAME [get_cells [get_sw_processor]]]
set proc [get_property IP_NAME [get_cells -hier [get_sw_processor]]]
}
@ -350,7 +350,7 @@ proc gen_testfunc_call {swproj mhsinst} {
proc get_fifo_info {mhsHandle type} {
set ipinst_list [get_cells $mhsHandle "*"]
set ipinst_list [get_cells -hier $mhsHandle "*"]
foreach ipinst $ipinst_list {
set coreName [get_property IP_NAME $ipinst]
@ -370,7 +370,7 @@ proc get_fifo_info {mhsHandle type} {
}
proc get_dma_info {mhsinst type} {
set ipinst_list [get_cells $mhsinst "*"]
set ipinst_list [get_cells -hier $mhsinst "*"]
set p2p_busifs_i [get_intf_pins -of_objects $mhsinst -filter "TYPE==INITIATOR"]
# Add p2p periphs

6
XilinxProcessorIPLib/drivers/bram/data/bram_tapp.tcl
View file

@ -161,7 +161,7 @@ proc gen_testfunc_call {swproj mhsinst} {
set bram_intr [::hsi::utils::is_ip_interrupting_current_proc $mhsinst]
if { ${bram_intr} == 1 } {
set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells $ipname] -filter "TYPE==INTERRUPT"]
set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells -hier $ipname] -filter "TYPE==INTERRUPT"]
set intcname [::hsi::utils::get_connected_intr_cntrl $ipname $intr_pin_name]
set intcvar intc
set proc [hsi::get_sw_processor]
@ -346,11 +346,11 @@ proc has_ecc_support {mhsinst} {
proc get_intr_port_name {mhsinst} {
set ipname [common::get_property NAME $mhsinst]
set port_intr [hsi::get_pins -of_objects [hsi::get_cells $mhsinst] "Interrupt"]
set port_intr [hsi::get_pins -of_objects [hsi::get_cells -hier $mhsinst] "Interrupt"]
if {$port_intr != ""} {
return "INTERRUPT"
}
set port_intr [hsi::get_pins -of_objects [hsi::get_cells $mhsinst] "ECC_Interrupt"]
set port_intr [hsi::get_pins -of_objects [hsi::get_cells -hier $mhsinst] "ECC_Interrupt"]
if {$port_intr != ""} {
return "ECC_INTERRUPT"
}

4
XilinxProcessorIPLib/drivers/cpu/data/cpu.tcl
View file

@ -121,7 +121,7 @@ proc generate {drv_handle} {
set libm "libm"
set sw_proc_handle [hsi::get_sw_processor]
set periph [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle]]
set periph [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle]]
set proctype [common::get_property IP_NAME $periph]
set endian [common::get_property CONFIG.C_ENDIANNESS $periph]
@ -399,7 +399,7 @@ proc generate {drv_handle} {
}
proc xdefine_addr_params_for_ext_intf {drvhandle file_name} {
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle ]]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle ]]
# Open include file
set file_handle [::hsi::utils::open_include_file $file_name]

6
XilinxProcessorIPLib/drivers/cpu_cortexa53/data/cpu_cortexa53.tcl
View file

@ -53,7 +53,7 @@ proc generate {drv_handle} {
proc xdefine_cortexa53_params {drvhandle} {
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle ]]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle ]]
set procdrv [get_sw_processor]
set archiver [common::get_property CONFIG.archiver $procdrv]
if {[string first "iarchive" $archiver] < 0 } {
@ -68,7 +68,7 @@ proc xdefine_cortexa53_params {drvhandle} {
}
}
set periphs [::hsi::utils::get_common_driver_ips $drvhandle]
set lprocs [hsi::get_cells -filter "IP_NAME==psu_cortexa53"]
set lprocs [hsi::get_cells -hier -filter "IP_NAME==psu_cortexa53"]
set lprocs [lsort $lprocs]
set config_inc [::hsi::utils::open_include_file "xparameters.h"]
@ -94,7 +94,7 @@ proc xdefine_cortexa53_params {drvhandle} {
proc xdefine_addr_params_for_ext_intf {drvhandle file_name} {
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle ]]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle ]]
# Open include file
set file_handle [::hsi::utils::open_include_file $file_name]

6
XilinxProcessorIPLib/drivers/cpu_cortexa9/data/cpu_cortexa9.tcl
View file

@ -55,7 +55,7 @@ proc generate {drv_handle} {
proc xdefine_cortexa9_params {drvhandle} {
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle ]]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle ]]
set procdrv [hsi::get_sw_processor]
set archiver [common::get_property CONFIG.archiver $procdrv]
if {[string first "iarchive" $archiver] < 0 } {
@ -70,7 +70,7 @@ proc xdefine_cortexa9_params {drvhandle} {
}
}
set periphs [::hsi::utils::get_common_driver_ips $drvhandle]
set lprocs [hsi::get_cells -filter "IP_NAME==ps7_cortexa9"]
set lprocs [hsi::get_cells -hier -filter "IP_NAME==ps7_cortexa9"]
set lprocs [lsort $lprocs]
set config_inc [::hsi::utils::open_include_file "xparameters.h"]
@ -96,7 +96,7 @@ proc xdefine_cortexa9_params {drvhandle} {
proc xdefine_addr_params_for_ext_intf {drvhandle file_name} {
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle ]]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle ]]
# Open include file
set file_handle [::hsi::utils::open_include_file $file_name]

6
XilinxProcessorIPLib/drivers/cpu_cortexr5/data/cpu_cortexr5.tcl
View file

@ -53,7 +53,7 @@ proc generate {drv_handle} {
proc xdefine_cortexr5_params {drvhandle} {
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle ]]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle ]]
set procdrv [hsi::get_sw_processor]
set archiver [common::get_property CONFIG.archiver $procdrv]
if {[string first "iarchive" $archiver] < 0 } {
@ -68,7 +68,7 @@ proc xdefine_cortexr5_params {drvhandle} {
}
}
set periphs [::hsi::utils::get_common_driver_ips $drvhandle]
set lprocs [hsi::get_cells -filter "IP_NAME==psu_cortexr5"]
set lprocs [hsi::get_cells -hier -filter "IP_NAME==psu_cortexr5"]
set lprocs [lsort $lprocs]
set config_inc [::hsi::utils::open_include_file "xparameters.h"]
@ -94,7 +94,7 @@ proc xdefine_cortexr5_params {drvhandle} {
proc xdefine_addr_params_for_ext_intf {drvhandle file_name} {
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle ]]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle ]]
# Open include file
set file_handle [::hsi::utils::open_include_file $file_name]

4
XilinxProcessorIPLib/drivers/dptxss/data/dptxss.tcl
View file

@ -63,7 +63,7 @@ proc hier_ip_define_config_file {drv_handle file_name drv_string args} {
foreach periph_g $periphs_g {
::hsi::current_hw_instance $periph_g;
set child_cells_g [::hsi::get_cells]
set child_cells_g [::hsi::get_cells -hier]
foreach child_cell_g $child_cells_g {
set child_cell_vlnv [::common::get_property VLNV $child_cell_g]
@ -115,7 +115,7 @@ proc hier_ip_define_config_file {drv_handle file_name drv_string args} {
}
::hsi::current_hw_instance $periph
set child_cells [::hsi::get_cells]
set child_cells [::hsi::get_cells -hier]
puts $config_file ",\n"
foreach child_cell $child_cells {

4
XilinxProcessorIPLib/drivers/emaclite/data/emaclite_tapp.tcl
View file

@ -136,10 +136,10 @@ proc gen_testfunc_call {swproj mhsinst} {
if {$ifemacliteintr == 1} {
set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells $ipname] -filter "TYPE==INTERRUPT"]
set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells -hier $ipname] -filter "TYPE==INTERRUPT"]
set intcname [::hsi::utils::get_connected_intr_cntrl $ipname $intr_pin_name]
set intcvar intc
set proc [common::get_property IP_NAME [hsi::get_cells [hsi::get_sw_processor]]]
set proc [common::get_property IP_NAME [hsi::get_cells -hier [hsi::get_sw_processor]]]
}
set testfunc_call ""

8
XilinxProcessorIPLib/drivers/emacps/data/emacps.tcl
View file

@ -65,7 +65,7 @@ proc generate {drv_handle} {
proc generate_gmii2rgmii_params {drv_handle file_name} {
set file_handle [::hsi::utils::open_include_file $file_name]
set ips [hsi::get_cells "*"]
set ips [hsi::get_cells -hier "*"]
foreach ip $ips {
set ipname [common::get_property NAME $ip]
set periph [common::get_property IP_NAME $ip]
@ -94,7 +94,7 @@ proc is_gmii2rgmii_conv_present {slave} {
set port_value 0
set phy_addr 0
set ipconv 0
set ips [hsi::get_cells "*"]
set ips [hsi::get_cells -hier "*"]
set enetipinstance_name [common::get_property NAME $slave]
foreach ip $ips {
@ -136,7 +136,7 @@ proc is_gmii2rgmii_conv_present {slave} {
proc generate_sgmii_params {drv_handle file_name} {
set file_handle [::hsi::utils::open_include_file $file_name]
set ips [hsi::get_cells "*"]
set ips [hsi::get_cells -hier "*"]
foreach ip $ips {
set ipname [common::get_property NAME $ip]
@ -172,7 +172,7 @@ proc is_gige_pcs_pma_ip_present {slave} {
set phy_addr 0
set ipconv 0
set ips [hsi::get_cells "*"]
set ips [hsi::get_cells -hier "*"]
set enetipinstance_name [common::get_property IP_NAME $slave]
foreach ip $ips {

2
XilinxProcessorIPLib/drivers/emacps/data/emacps_tapp.tcl
View file

@ -69,7 +69,7 @@ proc gen_include_files {swproj mhsinst} {
set ispcs_pma 0
set ipname [get_property NAME $mhsinst]
set ips [get_cells "*"]
set ips [get_cells -hier "*"]
set ipconv 0
foreach ip $ips {
set convipname [get_property NAME $ip]

4
XilinxProcessorIPLib/drivers/gpio/data/gpio_tapp.tcl
View file

@ -186,10 +186,10 @@ proc gen_testfunc_call {swproj mhsinst} {
set hasStdout 1
}
if { ${gpio_intr} == 1 && ${all_inputs} == 1 } {
set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells $ipname] -filter "TYPE==INTERRUPT"]
set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells -hier $ipname] -filter "TYPE==INTERRUPT"]
set intcname [::hsi::utils::get_connected_intr_cntrl $ipname $intr_pin_name]
set intcvar intc
set proc [common::get_property IP_NAME [hsi::get_cells [hsi::get_sw_processor]]]
set proc [common::get_property IP_NAME [hsi::get_cells -hier [hsi::get_sw_processor]]]
}
set testfunc_call ""

6
XilinxProcessorIPLib/drivers/intc/data/intc.tcl
View file

@ -294,9 +294,9 @@ proc intc_define_vector_table {periph config_inc config_file} {
for {set i 0} {$i < $total_source_intrs} {incr i} {
set source_ip $source_name($i)
if { [llength $source_ip] != 0 && [llength [hsi::get_cells $source_ip]] != 0} {
report_property [hsi::get_cells $source_ip]
set ip_name [common::get_property IP_NAME [hsi::get_cells $source_ip]]
if { [llength $source_ip] != 0 && [llength [hsi::get_cells -hier $source_ip]] != 0} {
report_property [hsi::get_cells -hier $source_ip]
set ip_name [common::get_property IP_NAME [hsi::get_cells -hier $source_ip]]
if { [string compare -nocase $ip_name "xlconstant"] == 0 } {
#do no generate interrupt handler entries for xlconstant
continue

8
XilinxProcessorIPLib/drivers/iomodule/data/iomodule.tcl
View file

@ -305,7 +305,7 @@ proc iomodule_define_vector_table {periph config_inc config_file} {
#update global array of Interrupt sources for this periph
intc_update_source_array $periph
set periph_name [common::get_property NAME $periph]
set interrupt_pin [hsi::get_pins -of_objects [get_cells $periph] -filter {TYPE==INTERRUPT&&DIRECTION==I}]
set interrupt_pin [hsi::get_pins -of_objects [get_cells -hier $periph] -filter {TYPE==INTERRUPT&&DIRECTION==I}]
# Get pins/ports that are driving the interrupt
lappend source_pins
@ -331,9 +331,9 @@ proc iomodule_define_vector_table {periph config_inc config_file} {
for {set i 0} {$i < $total_source_intrs} {incr i} {
set source_ip $source_name($i)
if { [llength $source_ip] != 0 && [llength [hsi::get_cells $source_ip]] \
if { [llength $source_ip] != 0 && [llength [hsi::get_cells -hier $source_ip]] \
!= 0} {
set ip_name [common::get_property IP_NAME [hsi::get_cells $source_ip]]
set ip_name [common::get_property IP_NAME [hsi::get_cells -hier $source_ip]]
if { [string compare -nocase $ip_name "xlconstant"] == 0 } {
#do no generate interrupt handler entries for xlconstant
continue
@ -611,7 +611,7 @@ proc xfind_instance {drvhandle instname} {
# (from external source).
##########################################################################
proc xget_port_type {periph} {
set mhs [hsi::get_cells -of_object $periph]
set mhs [hsi::get_cells -hier -of_object $periph]
if {[llength $mhs] == 0} {
return "global"
} else {

12
XilinxProcessorIPLib/drivers/ipipsu/data/ipipsu.tcl
View file

@ -47,7 +47,7 @@ proc ipi_format_hexmask {bitpos} {
proc ipi_define_xpar {inst param} {
set param_name [string range $param [string length "CONFIG."] [string length $param]]
set name [string range $param_name 2 end]
set param_value [common::get_property $param [hsi::get_cells $inst]]
set param_value [common::get_property $param [hsi::get_cells -hier $inst]]
if { [string compare $name "BIT_POSITION"] == 0} {
set name "BIT_MASK"
set param_value [ipi_format_hexmask $param_value]
@ -63,13 +63,13 @@ proc ipi_generate_config {drv_handle file_name} {
#The current processor
set sw_proc_handle [::hsi::get_sw_processor]
set hw_proc_handle [::hsi::get_cells [common::get_property hw_instance $sw_proc_handle]]
set hw_proc_handle [::hsi::get_cells -hier [common::get_property hw_instance $sw_proc_handle]]
# List of IPIs owned by this processor
set proc_ipi_list [lsearch -all -inline [get_property SLAVES $hw_proc_handle] psu_ipi_*]
# List of all IPIs on SoC
set ipi_list [get_cells -filter { IP_NAME == "psu_ipi" }]
set ipi_list [get_cells -hier -filter { IP_NAME == "psu_ipi" }]
set cfgfilename [file join "src" $file_name]
set config_file [open $cfgfilename w]
@ -127,14 +127,14 @@ proc ipi_generate_params {file_name} {
set file_handle [::hsi::utils::open_include_file $file_name]
# List of all IPIs on SoC
set ipi_list [get_cells -filter { IP_NAME == "psu_ipi" }]
set ipi_list [get_cells -hier -filter { IP_NAME == "psu_ipi" }]
#List of all processors on SoC
set proc_list [get_cells -filter { IP_TYPE == "PROCESSOR" }]
set proc_list [get_cells -hier -filter { IP_TYPE == "PROCESSOR" }]
#The current processor
set sw_proc_handle [::hsi::get_sw_processor]
set hw_proc_handle [::hsi::get_cells [common::get_property hw_instance $sw_proc_handle]]
set hw_proc_handle [::hsi::get_cells -hier [common::get_property hw_instance $sw_proc_handle]]
# List of IPIs owned by this processor

6
XilinxProcessorIPLib/drivers/mbox/data/mbox.tcl
View file

@ -63,7 +63,7 @@ proc xdefine_mbox_config_if {periph hfile_handle cfile_handle bus_if if_num dev_
# Copy over the right set of files as src based on processor type
# sw_proc_handle contains driver handle for processor for which libgen is running. Name of the sw_proc_handle will be driver name for processor[Ex:cpu for microblaze]
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells $sw_proc_handle]
set hw_proc_handle [hsi::get_cells -hier $sw_proc_handle]
set periph_name [string toupper [common::get_property NAME $periph]]
@ -167,7 +167,7 @@ proc xdefine_mbox_config_files {drv_handle hfile_name cfile_name drv_string} {
# Check whether the interface is connected or not
proc check_if_connected {periph if_num bus_if} {
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells $sw_proc_handle]
set hw_proc_handle [hsi::get_cells -hier $sw_proc_handle]
set if_isaxi 0
set if_axis_connected 0
@ -296,7 +296,7 @@ proc handle_stream {periph bus_if if_num usefsl sendfsl recfsl} {
set not_connected 0
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells $sw_proc_handle]
set hw_proc_handle [hsi::get_cells -hier $sw_proc_handle]
set periph_name [string toupper [common::get_property NAME $periph]]

2
XilinxProcessorIPLib/drivers/mutex/data/mutex.tcl
View file

@ -138,7 +138,7 @@ proc xdefine_mutex_config_files {drv_handle hfile_name cfile_name drv_string} {
proc check_if_connected {periph if_num} {
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells $sw_proc_handle]
set hw_proc_handle [hsi::get_cells -hier $sw_proc_handle]
set if_isaxi 0
set baseaddr [common::get_property CONFIG.[format "C_S%d_AXI_BASEADDR" $if_num] $periph]

10
XilinxProcessorIPLib/drivers/scugic/data/scugic.tcl
View file

@ -72,7 +72,7 @@ proc xdefine_zynq_include_file {drv_handle file_name drv_string args} {
#Get the processor instance name
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle] ]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle] ]
set proctype [common::get_property IP_NAME $hw_proc_handle]
#Get proper gic instance for periphs in case of zynqmp
foreach periph $periphs {
@ -174,7 +174,7 @@ proc xdefine_zynq_canonical_xpars {drv_handle file_name drv_string args} {
#Get the processor instance name
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle] ]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle] ]
set proctype [common::get_property IP_NAME $hw_proc_handle]
#Get proper gic instance for periphs in case of zynqmp
@ -295,7 +295,7 @@ proc xdefine_zynq_config_file {drv_handle file_name drv_string args} {
#Get the processor instance name
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle] ]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle] ]
set proctype [common::get_property IP_NAME $hw_proc_handle]
#Get proper gic instance for periphs in case of zynqmp
@ -355,7 +355,7 @@ proc xdefine_gic_params {drvhandle} {
#Get the processor instance name
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle] ]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle] ]
set proctype [common::get_property IP_NAME $hw_proc_handle]
# Fix me
# Avoid generating fabric interrupts for zynqmp till the issue is fixed
@ -423,7 +423,7 @@ proc xdefine_gic_params {drvhandle} {
set port_obj [::hsi::get_ports $port_name]
set port_intr_id [::hsi::utils::get_interrupt_id $ip_name $port_name]
if { [string compare -nocase $ip_name "system"] } {
set ip_obj [::hsi::get_cells $ip_name]
set ip_obj [::hsi::get_cells -hier $ip_name]
if {[llength $ip_obj]} {
set port_obj [::hsi::get_pins -of_objects $ip_obj $port_name]
}

2
XilinxProcessorIPLib/drivers/scugic/data/scugic_tapp.tcl
View file

@ -90,7 +90,7 @@ proc gen_testfunc_call {swproj mhsinst} {
set deviceid [::hsi::utils::get_ip_param_name $mhsinst "DEVICE_ID"]
set stdout [common::get_property CONFIG.STDOUT [hsi::get_os]]
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle] ]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle] ]
set proctype [common::get_property IP_NAME $hw_proc_handle]
if {([string compare -nocase $proctype "ps7_cortexa9"] == 0)||
(([string compare -nocase $proctype "psu_cortexa53"] == 0)&&([string compare -nocase $ipname "psu_acpu_gic"] == 0))||

2
XilinxProcessorIPLib/drivers/spi/data/spi.tcl
View file

@ -103,7 +103,7 @@ proc xdefine_axispi_include_file {drv_handle file_name drv_string} {
}
proc xdefine_axispi_params_instance {file_handle periph device_id} {
set ip [hsi::get_cells $periph]
set ip [hsi::get_cells -hier $periph]
set xip_mode_value [common::get_property CONFIG.C_XIP_MODE $ip]
if {[llength $xip_mode_value] == 0} {
set xip_mode_value 0

4
XilinxProcessorIPLib/drivers/spi/data/spi_tapp.tcl
View file

@ -147,10 +147,10 @@ proc gen_testfunc_call {swproj mhsinst} {
set spi_intr [::hsi::utils::is_ip_interrupting_current_proc $mhsinst]
if { ${spi_intr} == 1} {
set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells $ipname] -filter "TYPE==INTERRUPT"]
set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells -hier $ipname] -filter "TYPE==INTERRUPT"]
set intcname [::hsi::utils::get_connected_intr_cntrl $ipname $intr_pin_name]
set intcvar intc
set proc [common::get_property IP_NAME [hsi::get_cells [hsi::get_sw_processor]]]
set proc [common::get_property IP_NAME [hsi::get_cells -hier [hsi::get_sw_processor]]]
}
set testfunc_call ""

4
XilinxProcessorIPLib/drivers/sysmon/data/sysmon_tapp.tcl
View file

@ -126,10 +126,10 @@ proc gen_testfunc_call {swproj mhsinst} {
}
if {$ifsysmonintr == 1} {
set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells $ipname] -filter "TYPE==INTERRUPT"]
set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells -hier $ipname] -filter "TYPE==INTERRUPT"]
set intcname [::hsi::utils::get_connected_intr_cntrl $ipname $intr_pin_name]
set intcvar intc
set proc [common::get_property IP_NAME [hsi::get_cells [hsi::get_sw_processor]]]
set proc [common::get_property IP_NAME [hsi::get_cells -hier [hsi::get_sw_processor]]]
}
set testfunc_call ""

4
XilinxProcessorIPLib/drivers/tmrctr/data/tmrctr_tapp.tcl
View file

@ -133,10 +133,10 @@ proc gen_testfunc_call {swproj mhsinst} {
}
if {$iftmrintr == 1} {
set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells $ipname] -filter "TYPE==INTERRUPT"]
set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells -hier $ipname] -filter "TYPE==INTERRUPT"]
set intcname [::hsi::utils::get_connected_intr_cntrl $ipname $intr_pin_name]
set intcvar intc
set proc [common::get_property IP_NAME [hsi::get_cells [hsi::get_sw_processor]]]
set proc [common::get_property IP_NAME [hsi::get_cells -hier [hsi::get_sw_processor]]]
}
set testfunc_call ""

4
XilinxProcessorIPLib/drivers/uartlite/data/uartlite_tapp.tcl
View file

@ -180,10 +180,10 @@ proc gen_testfunc_call {swproj mhsinst} {
set hasStdout 1
}
if {$ifuartliteintr == 1} {
set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells $ipname] -filter "TYPE==INTERRUPT"]
set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells -hier $ipname] -filter "TYPE==INTERRUPT"]
set intcname [::hsi::utils::get_connected_intr_cntrl $ipname $intr_pin_name]
set intcvar intc
set proc [common::get_property IP_NAME [hsi::get_cells [hsi::get_sw_processor]]]
set proc [common::get_property IP_NAME [hsi::get_cells -hier [hsi::get_sw_processor]]]
set mdm_name [common::get_property IP_NAME $mhsinst]
}

4
XilinxProcessorIPLib/drivers/uartns550/data/uartns550_tapp.tcl
View file

@ -184,10 +184,10 @@ proc gen_testfunc_call {swproj mhsinst} {
set hasStdout 1
}
if {$ifuartns550intr == 1} {
set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells $ipname] -filter "TYPE==INTERRUPT"]
set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells -hier $ipname] -filter "TYPE==INTERRUPT"]
set intcname [::hsi::utils::get_connected_intr_cntrl $ipname $intr_pin_name]
set intcvar intc
set proc [common::get_property IP_NAME [hsi::get_cells [hsi::get_sw_processor]]]
set proc [common::get_property IP_NAME [hsi::get_cells -hier [hsi::get_sw_processor]]]
}
if {${hasStdout} == 0} {

4
XilinxProcessorIPLib/drivers/vprocss/data/vprocss.tcl
View file

@ -80,7 +80,7 @@ proc hier_ip_define_config_file {drv_handle file_name drv_string args} {
::hsi::current_hw_instance $periph_g;
set child_cells_g [::hsi::get_cells]
set child_cells_g [::hsi::get_cells -hier]
foreach child_cell_g $child_cells_g {
set child_cell_vlnv [::common::get_property VLNV $child_cell_g]
@ -217,7 +217,7 @@ proc hier_ip_define_config_file {drv_handle file_name drv_string args} {
}
::hsi::current_hw_instance $periph
set child_cells [::hsi::get_cells]
set child_cells [::hsi::get_cells -hier]
puts $config_file ",\n"
foreach sub_core [lsort [array names sub_core_inst]] {

4
XilinxProcessorIPLib/drivers/wdttb/data/wdttb_tapp.tcl
View file

@ -140,10 +140,10 @@ proc gen_testfunc_call {swproj mhsinst} {
}
if {$iftmrintr == 1} {
set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells $ipname] WDT_INTERRUPT]
set intr_pin_name [hsi::get_pins -of_objects [hsi::get_cells -hier $ipname] WDT_INTERRUPT]
set intcname [::hsi::utils::get_connected_intr_cntrl $ipname $intr_pin_name]
set intcvar intc
set proc [common::get_property IP_NAME [hsi::get_cells [hsi::get_sw_processor]]]
set proc [common::get_property IP_NAME [hsi::get_cells -hier [hsi::get_sw_processor]]]
}
set testfunc_call ""

20
lib/bsp/standalone/data/standalone.tcl
View file

@ -56,7 +56,7 @@ proc generate {os_handle} {
set need_config_file "false"
# Copy over the right set of files as src based on processor type
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle] ]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle] ]
set proctype [common::get_property IP_NAME $hw_proc_handle]
set procname [common::get_property NAME $hw_proc_handle]
@ -276,7 +276,7 @@ proc xhandle_mb_interrupts {} {
# Handle the interrupt pin
set sw_proc_handle [hsi::get_sw_processor]
set periph [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle] ]
set periph [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle] ]
set source_ports [::hsi::utils::get_interrupt_sources $periph]
if {[llength $source_ports] > 1} {
error "ERROR: Too many interrupting ports on the MicroBlaze. Should only find 1" "" "hsi_error"
@ -351,7 +351,7 @@ proc xcreate_mb_exc_config_file {os_handle} {
set hconfig_file [open $hfilename w]
::hsi::utils::write_c_header $hconfig_file "Exception Handling Header for MicroBlaze Processor"
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle] ]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle] ]
set procvlnv [common::get_property VLNV $hw_proc_handle]
set procvlnv [split $procvlnv :]
set procver [lindex $procvlnv 3]
@ -426,7 +426,7 @@ proc xcreate_mb_exc_config_file {os_handle} {
proc post_generate {os_handle} {
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle] ]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle] ]
set procname [common::get_property NAME $hw_proc_handle]
set proctype [common::get_property IP_NAME $hw_proc_handle]
@ -590,14 +590,14 @@ proc handle_profile { os_handle proctype } {
if {$proctype == "ps7_cortexa9"} {
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle]]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle]]
set cpu_freq [common::get_property CONFIG.C_CPU_CLK_FREQ_HZ $hw_proc_handle]
if { [string compare -nocase $cpu_freq ""] == 0 } {
puts "WARNING<profile> :: CPU Clk Frequency not specified, Assuming 666Mhz"
set cpu_freq 666000000
}
} else {
set cpu_freq [common::get_property CONFIG.C_FREQ [hsi::get_cells $proc]]
set cpu_freq [common::get_property CONFIG.C_FREQ [hsi::get_cells -hier $proc]]
if { [string compare -nocase $cpu_freq ""] == 0 } {
puts "WARNING<profile> :: CPU Clk Frequency not specified, Assuming 100Mhz"
set cpu_freq 100000000
@ -690,21 +690,21 @@ proc execpipe {COMMAND} {
# - The xps/opb_timer can be connected directly to Microblaze External Intr Pin.
# - (OR) xps/opb_timer can be connected to xps/opb_intc
proc handle_profile_opbtimer { config_file timer_inst } {
set timer_handle [hsi::get_cells $timer_inst]
set timer_handle [hsi::get_cells -hier $timer_inst]
set timer_baseaddr [common::get_property CONFIG.C_BASEADDR $timer_handle]
puts $config_file "#define PROFILE_TIMER_BASEADDR [::hsi::utils::format_addr_string $timer_baseaddr "C_BASEADDR"]"
# Figure out how Timer is connected.
set timer_intr [hsi::get_pins -of_objects [hsi::get_cells $timer_handle] Interrupt]
set timer_intr [hsi::get_pins -of_objects [hsi::get_cells -hier $timer_handle] Interrupt]
if { [string compare -nocase $timer_intr ""] == 0 } {
error "ERROR <profile> :: Timer Interrupt PORT is not specified" "" "mdt_error"
}
#set mhs_handle [xget_handle $timer_handle "parent"]
# CR 302300 - There can be multiple "sink" for the interrupt. So need to iterate through the list
set intr_port_list [::hsi::utils::get_sink_pins [hsi::get_pins -of_objects [hsi::get_cells $timer_intr] INTERRUPT]]
set intr_port_list [::hsi::utils::get_sink_pins [hsi::get_pins -of_objects [hsi::get_cells -hier $timer_intr] INTERRUPT]]
set timer_connection 0
foreach intr_port $intr_port_list {
set intc_handle [hsi::get_cells -of_object $intr_port]
set intc_handle [hsi::get_cells -hier -of_object $intr_port]
# Check if the Sink is a Global Port. If so, Skip the Port Connection
if { [::hsi::utils::is_external_pin $intr_port] } {

50
lib/bsp/xilkernel/data/xilkernel.tcl
View file

@ -37,7 +37,7 @@
proc kernel_drc {os_handle} {
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle]]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle]]
set proctype [common::get_property IP_NAME $hw_proc_handle]
set compiler [common::get_property CONFIG.compiler $sw_proc_handle]
@ -58,7 +58,7 @@ proc kernel_drc {os_handle} {
if { $systmr_dev == "none" } {
error "ERROR: Xilkernel for Microblaze requires a system timer device to be specified. Please choose a valid peripheral instance in the systmr_dev parameter." "" "mdt_error"
}
set systmr_handle [hsi::get_cells $systmr_dev]
set systmr_handle [hsi::get_cells -hier $systmr_dev]
set systmr_type [common::get_property IP_NAME $systmr_handle]
if { $systmr_type != "fit_timer" && $systmr_type != "opb_timer" && $systmr_type != "xps_timer" && $systmr_type != "axi_timer" } {
error "ERROR: Xilkernel for Microblaze can work only with an axi_timer, xps_timer, opb_timer or fit_timer. Please choose a valid device as the system timer with the parameter systmr_dev." "" "mdt_error"
@ -123,7 +123,7 @@ proc kernel_drc {os_handle} {
proc generate {os_handle} {
variable standalone_version
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle]]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle]]
set proctype [common::get_property IP_NAME $hw_proc_handle]
set procver [common::get_property CONFIG.HW_VER $hw_proc_handle]
@ -376,7 +376,7 @@ proc generate {os_handle} {
set systmr_spec [common::get_property CONFIG.systmr_spec $os_handle]
if { $proctype == "microblaze" } {
set systmr_dev [common::get_property CONFIG.systmr_dev $os_handle]
set systmr_handle [hsi::get_cells $systmr_dev]
set systmr_handle [hsi::get_cells -hier $systmr_dev]
set systmr_type [common::get_property IP_NAME $systmr_handle]
}
@ -408,7 +408,7 @@ proc generate {os_handle} {
set sysintc_spec [common::get_property CONFIG.sysintc_spec $os_handle]
if { $sysintc_spec != "none" } {
xput_define $config_file "CONFIG_INTC" "true"
set sysintc_dev_handle [hsi::get_cells $sysintc_spec]
set sysintc_dev_handle [hsi::get_cells -hier $sysintc_spec]
set sysintc_baseaddr [::hsi::utils::get_ip_param_name $sysintc_dev_handle "C_BASEADDR"]
set sysintc_device_id [::hsi::utils::get_ip_param_name $sysintc_dev_handle "DEVICE_ID"]
xput_define $config_file "sysintc_baseaddr" $sysintc_baseaddr
@ -417,13 +417,13 @@ proc generate {os_handle} {
# Additionally for microblaze, figure out which interrupt
# input is the system timer interrupt and define its ID
if { $proctype == "microblaze" } {
set systmr_intr [hsi::get_pins -of_objects [hsi::get_cells $systmr_handle] Interrupt]
set systmr_intr [hsi::get_pins -of_objects [hsi::get_cells -hier $systmr_handle] Interrupt]
#set systmr_intr [xget_value $systmr_handle "PORT" "Interrupt"]
if { [string compare -nocase $systmr_intr ""] == 0 } {
error "ERROR: System Timer Interrupt PORT is not specified" "" "mdt_error"
}
#set mhs_handle [hsi::get_cells -of_object $systmr_handle]
set intr_ports [::hsi::utils::get_sink_pins [hsi::get_pins -of_objects [hsi::get_cells $systmr_intr] INTERRUPT]]
#set mhs_handle [hsi::get_cells -hier -of_object $systmr_handle]
set intr_ports [::hsi::utils::get_sink_pins [hsi::get_pins -of_objects [hsi::get_cells -hier $systmr_intr] INTERRUPT]]
#set intr_ports [xget_connected_ports_handle $mhs_handle $systmr_intr "sink"]
foreach intr_port $intr_ports {
set intr_port_type [common::get_property TYPE $intr_port]
@ -431,13 +431,13 @@ proc generate {os_handle} {
continue
}
set intc_handle [hsi::get_cells -of_object $intr_port]
set intc_handle [hsi::get_cells -hier -of_object $intr_port]
set intc_name [common::get_property NAME $intc_handle]
set proc_intc_handle [hsi::get_cells $intc_name]
set proc_intc_handle [hsi::get_cells -hier $intc_name]
if { [string compare -nocase $sysintc_dev_handle $intc_handle] == 0 } {
continue
}
set systmr_intrpin [hsi::get_pins -of_objects [hsi::get_cells $systmr_handle] -filter "TYPE == INTERRUPT"]
set systmr_intrpin [hsi::get_pins -of_objects [hsi::get_cells -hier $systmr_handle] -filter "TYPE == INTERRUPT"]
set intr_id [::hsi::utils::get_port_intr_id $systmr_handle $systmr_intrpin]
puts $config_file "#define SYSTMR_INTR_ID $intr_id\n"
}
@ -527,7 +527,7 @@ proc generate {os_handle} {
# Handle I/O ranges for MicroBlaze MPU here
if { $proctype == "microblaze" } {
#set mhs_handle [hsi::get_cells -of_object $hw_proc_handle]
#set mhs_handle [hsi::get_cells -hier -of_object $hw_proc_handle]
set mmu [common::get_property CONFIG.C_USE_MMU $hw_proc_handle]
if { $mmu >= 2 } {
@ -542,18 +542,18 @@ proc generate {os_handle} {
}
set dbus_name [::hsi::utils::get_intfnet_name $hw_proc_handle $dbus_if_name]
set dbus_handle [hsi::get_cells $dbus_name]
set dbus_handle [hsi::get_cells -hier $dbus_name]
if { $interconnect == 2 } {
set dcachelink_handle [hsi::get_cells "DXCL"]
set dcachelink_handle [hsi::get_cells -hier "DXCL"]
} else {
set dcachelink_handle [hsi::get_cells "M_AXI_DC"]
set dcachelink_handle [hsi::get_cells -hier "M_AXI_DC"]
}
#set addrlist [xget_hw_bus_slave_addrpairs $dbus_handle]
set addrlists [hsi::get_mem_ranges -of_objects [hsi::get_cells $sw_proc_handle]]
set addrlists [hsi::get_mem_ranges -of_objects [hsi::get_cells -hier $sw_proc_handle]]
set addrlist [list]
foreach addrist $addrlists {
set ip_name [common::get_property IP_NAME [hsi::get_cells $addrist]]
set ip_name [common::get_property IP_NAME [hsi::get_cells -hier $addrist]]
if { $ip_name == "axi_emc" || $ip_name == "mig_7series" } {
set mem [lindex [hsi::get_mem_ranges $addrist] 0]
set mc_base [common::get_property BASE_VALUE $mem]
@ -569,7 +569,7 @@ proc generate {os_handle} {
if { $dcachelink_handle != "" } {
#set xcl_addrlist [xget_hw_bus_slave_addrpairs $dcachelink_handle]
set xcl_addrlist [hsi::get_mem_ranges -of_objects [hsi::get_cells $sw_proc_handle]]
set xcl_addrlist [hsi::get_mem_ranges -of_objects [hsi::get_cells -hier $sw_proc_handle]]
set addrlist [concat addrlist xcl_addrlist]
}
@ -577,8 +577,8 @@ proc generate {os_handle} {
# Get the list of memory controllers in the mhs. We want to filter
# "memories" from the above addrlist
set memcon_handles [xget_memory_controller_handles [hsi::get_cells $sw_proc_handle]]
#set memcon_handles [hsi::get_mem_ranges -of_objects [hsi::get_cells $sw_proc_handle]]
set memcon_handles [xget_memory_controller_handles [hsi::get_cells -hier $sw_proc_handle]]
#set memcon_handles [hsi::get_mem_ranges -of_objects [hsi::get_cells -hier $sw_proc_handle]]
set n_ioranges 0
foreach {base high} $addrlist {
set skip 0
@ -770,7 +770,7 @@ proc xhandle_mb_interrupts {} {
# Handle the interrupt pin
set sw_proc_handle [hsi::get_sw_processor]
set periph [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle]]
set periph [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle]]
set source_ports [::hsi::utils::get_interrupt_sources $periph]
if {[llength $source_ports] > 1} {
error "ERROR: Too many interrupting ports on the MicroBlaze. Should only find 1" "" "hsi_error"
@ -781,7 +781,7 @@ proc xhandle_mb_interrupts {} {
set source_port [lindex $source_ports 0]
if {[llength $source_port] != 0} {
set source_port_name [common::get_property NAME $source_port]
set source_periph [hsi::get_cells -of_object $source_port]
set source_periph [hsi::get_cells -hier -of_object $source_port]
set source_name [common::get_property NAME $source_periph]
set source_driver [hsi::get_drivers $source_name]
@ -864,7 +864,7 @@ proc xcreate_mb_exc_config_file { } {
puts $hconfig_file "\n"
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle]]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle]]
set procver [common::get_property CONFIG.HW_VER $hw_proc_handle]
if { ![mb_has_exceptions $hw_proc_handle]} { ;# NO exceptions are enabled
@ -889,7 +889,7 @@ proc xcreate_mb_exc_config_file { } {
# --------------------------------------
proc post_generate {os_handle} {
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle]]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle]]
set proctype [common::get_property IP_NAME $hw_proc_handle]
set procname [common::get_property NAME $hw_proc_handle]
@ -1017,7 +1017,7 @@ proc xget_memory_controller_handles { mhs } {
set ret_list ""
# Gets all MhsInsts in the system
set mhsinsts [hsi::get_cells *]
set mhsinsts [hsi::get_cells -hier *]
# Loop thru each MhsInst and determine if have "ADDR_TYPE = MEMORY" in
# the parameters.

2
lib/sw_apps/freertos_hello_world/data/freertos_hello_world.tcl
View file

@ -64,7 +64,7 @@ proc swapp_is_supported_hw {} {
set proc_instance [::hsi::get_sw_processor];
set hw_processor [common::get_property HW_INSTANCE $proc_instance]
set proc_type [common::get_property IP_NAME [hsi::get_cells $hw_processor]];
set proc_type [common::get_property IP_NAME [hsi::get_cells -hier $hw_processor]];
if { $proc_type != "psu_cortexr5" } {
error "This application is supported only for CortexR5 processors.";

60
lib/sw_apps/lwip_echo_server/data/lwip_echo_server.tcl
View file

@ -9,9 +9,9 @@ proc swapp_get_description {} {
}
proc check_stdout_hw {} {
set slaves [common::get_property SLAVES [hsi::get_cells [hsi::get_sw_processor]]]
set slaves [common::get_property SLAVES [hsi::get_cells -hier [hsi::get_sw_processor]]]
foreach slave $slaves {
set slave_type [common::get_property IP_NAME [hsi::get_cells $slave]];
set slave_type [common::get_property IP_NAME [hsi::get_cells -hier $slave]];
# Check for MDM-Uart peripheral. The MDM would be listed as a peripheral
# only if it has a UART interface. So no further check is required
if { $slave_type == "ps7_uart" || $slave_type == "psu_uart" || $slave_type == "axi_uartlite" ||
@ -32,34 +32,34 @@ proc get_stdout {} {
}
proc check_emac_hw {} {
set emaclites [hsi::get_cells -filter { ip_name == "xps_ethernetlite" }];
set emaclites [hsi::get_cells -hier -filter { ip_name == "xps_ethernetlite" }];
if { [llength $emaclites] != 0 } {
return;
}
set emaclites [hsi::get_cells -filter { ip_name == "axi_ethernetlite"}];
set emaclites [hsi::get_cells -hier -filter { ip_name == "axi_ethernetlite"}];
if { [llength $emaclites] != 0 } {
return;
}
set temacs [hsi::get_cells -filter { ip_name == "xps_ll_temac" }];
set temacs [hsi::get_cells -hier -filter { ip_name == "xps_ll_temac" }];
if { [llength $temacs] != 0 } {
return;
}
set temacs [hsi::get_cells -filter { ip_name == "axi_ethernet" }];
set temacs [hsi::get_cells -hier -filter { ip_name == "axi_ethernet" }];
if { [llength $temacs] != 0 } {
return;
}
set temacs [hsi::get_cells -filter { ip_name == "axi_ethernet_buffer" }];
set temacs [hsi::get_cells -hier -filter { ip_name == "axi_ethernet_buffer" }];
if { [llength $temacs] != 0 } {
return;
}
set temacs [hsi::get_cells -filter { ip_name == "ps7_ethernet" }];
set temacs [hsi::get_cells -hier -filter { ip_name == "ps7_ethernet" }];
if { [llength $temacs] != 0 } {
return;
}
set temacs [hsi::get_cells -filter { ip_name == "psu_ethernet" }];
set temacs [hsi::get_cells -hier -filter { ip_name == "psu_ethernet" }];
if { [llength $temacs] != 0 } {
return;
}
@ -73,9 +73,9 @@ proc get_mem_size { memlist } {
proc require_memory {memsize} {
set proc_instance [hsi::get_sw_processor]
set imemlist [hsi::get_mem_ranges -of_objects [hsi::get_cells $proc_instance] -filter "IS_INSTRUCTION==1"];
set idmemlist [hsi::get_mem_ranges -of_objects [hsi::get_cells $proc_instance] -filter "IS_INSTRUCTION==1 && IS_DATA==1"];
set dmemlist [hsi::get_mem_ranges -of_objects [hsi::get_cells $proc_instance] -filter "IS_DATA==1"];
set imemlist [hsi::get_mem_ranges -of_objects [hsi::get_cells -hier $proc_instance] -filter "IS_INSTRUCTION==1"];
set idmemlist [hsi::get_mem_ranges -of_objects [hsi::get_cells -hier $proc_instance] -filter "IS_INSTRUCTION==1 && IS_DATA==1"];
set dmemlist [hsi::get_mem_ranges -of_objects [hsi::get_cells -hier $proc_instance] -filter "IS_DATA==1"];
set memlist [concat $imemlist $idmemlist $dmemlist];
@ -120,12 +120,12 @@ proc swapp_is_supported_hw {} {
# do processor specific checks
set proc [hsi::get_sw_processor];
set proc_type [common::get_property IP_NAME [hsi::get_cells $proc]]
set proc_type [common::get_property IP_NAME [hsi::get_cells -hier $proc]]
if { $proc_type == "microblaze"} {
# make sure there is a timer (if this is a MB)
set timerlist [hsi::get_cells -filter { ip_name == "xps_timer" }];
set timerlist [hsi::get_cells -hier -filter { ip_name == "xps_timer" }];
if { [llength $timerlist] <= 0 } {
set timerlist [hsi::get_cells -filter { ip_name == "axi_timer" }];
set timerlist [hsi::get_cells -hier -filter { ip_name == "axi_timer" }];
if { [llength $timerlist] <= 0 } {
error "There seems to be no timer peripheral in the hardware. lwIP requires an xps_timer for TCP operations.";
}
@ -159,7 +159,7 @@ proc swapp_is_supported_sw {} {
proc generate_stdout_config { fid } {
set stdout [get_stdout];
set stdout [hsi::get_cells $stdout]
set stdout [hsi::get_cells -hier $stdout]
# if stdout is uartlite, we don't have to generate anything
set stdout_type [common::get_property IP_TYPE $stdout];
@ -189,11 +189,11 @@ proc generate_emac_config {fp} {
# how lwIP determines the EMAC's that can be used.
set proc [hsi::get_sw_processor];
set proc_type [common::get_property IP_NAME [hsi::get_cells $proc]]
set proc_type [common::get_property IP_NAME [hsi::get_cells -hier $proc]]
set emaclites [hsi::get_cells -filter { ip_name == "xps_ethernetlite" }];
set emaclites [hsi::get_cells -hier -filter { ip_name == "xps_ethernetlite" }];
if { [llength $emaclites] == 0 } {
set emaclites [hsi::get_cells -filter { ip_name == "axi_ethernetlite" }];
set emaclites [hsi::get_cells -hier -filter { ip_name == "axi_ethernetlite" }];
}
if { [llength $emaclites] > 0 } {
# we have an emaclite
@ -212,7 +212,7 @@ proc generate_emac_config {fp} {
}
}
set temacs [hsi::get_cells -filter { ip_name == "xps_ll_temac" }];
set temacs [hsi::get_cells -hier -filter { ip_name == "xps_ll_temac" }];
if { [llength $temacs] > 0 } {
# we have an emaclite
set temac [lindex $temacs 0]
@ -223,7 +223,7 @@ proc generate_emac_config {fp} {
puts $fp "#define PLATFORM_EMAC_BASEADDR $emac_baseaddr";
return;
}
set temacs [hsi::get_cells -filter { ip_name == "axi_ethernet" }];
set temacs [hsi::get_cells -hier -filter { ip_name == "axi_ethernet" }];
if { [llength $temacs] > 0 } {
if {$proc_type == "ps7_cortexa9" && $use_softeth_on_zynq == 0} {
} else {
@ -240,7 +240,7 @@ proc generate_emac_config {fp} {
}
}
set temacs [hsi::get_cells -filter { ip_name == "axi_ethernet_buffer" }];
set temacs [hsi::get_cells -hier -filter { ip_name == "axi_ethernet_buffer" }];
if { [llength $temacs] > 0 } {
if {$proc_type == "ps7_cortexa9" && $use_softeth_on_zynq == 0} {
} else {
@ -257,13 +257,13 @@ proc generate_emac_config {fp} {
}
}
set temacs [hsi::get_cells -filter { ip_name == "ps7_ethernet" }];
set temacs [hsi::get_cells -hier -filter { ip_name == "ps7_ethernet" }];
if { [llength $temacs] > 0 } {
puts $fp "#define PLATFORM_EMAC_BASEADDR XPAR_XEMACPS_0_BASEADDR";
return;
}
set temacs [hsi::get_cells -filter { ip_name == "psu_ethernet" }];
set temacs [hsi::get_cells -hier -filter { ip_name == "psu_ethernet" }];
if { [llength $temacs] > 0 } {
puts $fp "#define PLATFORM_EMAC_BASEADDR XPAR_XEMACPS_0_BASEADDR";
return;
@ -276,15 +276,15 @@ proc generate_timer_config { fp } {
set postfix_intr "_INTERRUPT_INTR";
set postfix_base "_BASEADDR";
set intcs [hsi::get_cells -filter {ip_name == "xps_intc"}];
set intcs [hsi::get_cells -hier -filter {ip_name == "xps_intc"}];
if { [llength $intcs] == 0 } {
set intcs [hsi::get_cells -filter { ip_name == "axi_intc" }];
set intcs [hsi::get_cells -hier -filter { ip_name == "axi_intc" }];
}
set intc [lindex $intcs 0];
set timers [hsi::get_cells -filter { ip_name == "xps_timer" }];
set timers [hsi::get_cells -hier -filter { ip_name == "xps_timer" }];
if { [llength $timers] == 0 } {
set timers [hsi::get_cells -filter { ip_name == "axi_timer" }];
set timers [hsi::get_cells -hier -filter { ip_name == "axi_timer" }];
}
set timer [lindex $timers 0];
@ -325,7 +325,7 @@ proc swapp_generate {} {
# if MB, figure out the timer to be used
set proc [hsi::get_sw_processor];
set proc_type [common::get_property IP_NAME [hsi::get_cells $proc]]
set proc_type [common::get_property IP_NAME [hsi::get_cells -hier $proc]]
if { $proc_type == "microblaze"} {
generate_timer_config $fid;
@ -333,7 +333,7 @@ proc swapp_generate {} {
}
set hw_processor [common::get_property HW_INSTANCE $proc]
set proc_arm [common::get_property IP_NAME [hsi::get_cells $hw_processor]];
set proc_arm [common::get_property IP_NAME [hsi::get_cells -hier $hw_processor]];
if { $proc_arm == "ps7_cortexa9"} {
puts $fid "#define PLATFORM_ZYNQ \n";
} elseif { $proc_arm == "psu_cortexr5"} {

2
lib/sw_apps/openamp_echo_test/data/openamp_echo_test.tcl
View file

@ -71,7 +71,7 @@ proc swapp_is_supported_hw {} {
set proc_instance [hsi::get_sw_processor];
set hw_processor [common::get_property HW_INSTANCE $proc_instance]
set proc_type [common::get_property IP_NAME [hsi::get_cells $hw_processor]];
set proc_type [common::get_property IP_NAME [hsi::get_cells -hier $hw_processor]];
if { $proc_type != "psu_cortexr5" } {
error "This application is supported only for CortexR5 processors.";

2
lib/sw_apps/openamp_matrix_multiply/data/openamp_matrix_multiply.tcl
View file

@ -71,7 +71,7 @@ proc swapp_is_supported_hw {} {
set proc_instance [hsi::get_sw_processor];
set hw_processor [common::get_property HW_INSTANCE $proc_instance]
set proc_type [common::get_property IP_NAME [hsi::get_cells $hw_processor]];
set proc_type [common::get_property IP_NAME [hsi::get_cells -hier $hw_processor]];
if { $proc_type != "psu_cortexr5" } {
error "This application is supported only for CortexR5 processors.";

2
lib/sw_apps/openamp_rpc_demo/data/openamp_rpc_demo.tcl
View file

@ -71,7 +71,7 @@ proc swapp_is_supported_hw {} {
set proc_instance [hsi::get_sw_processor];
set hw_processor [common::get_property HW_INSTANCE $proc_instance]
set proc_type [common::get_property IP_NAME [hsi::get_cells $hw_processor]];
set proc_type [common::get_property IP_NAME [hsi::get_cells -hier $hw_processor]];
if { $proc_type != "psu_cortexr5" } {
error "This application is supported only for CortexR5 processors.";

6
lib/sw_apps/rsa_auth_app/data/rsa_auth_app.tcl
View file

@ -16,9 +16,9 @@ proc get_stdout {} {
}
proc check_stdout_hw {} {
set slaves [common::get_property SLAVES [hsi::get_cells [hsi::get_sw_processor]]]
set slaves [common::get_property SLAVES [hsi::get_cells -hier [hsi::get_sw_processor]]]
foreach slave $slaves {
set slave_type [common::get_property IP_NAME [hsi::get_cells $slave]];
set slave_type [common::get_property IP_NAME [hsi::get_cells -hier $slave]];
# Check for MDM-Uart peripheral. The MDM would be listed as a peripheral
# only if it has a UART interface. So no further check is required
if { $slave_type == "ps7_uart" || $slave_type == "axi_uartlite" ||
@ -44,7 +44,7 @@ proc swapp_is_supported_hw {} {
set proc_instance [hsi::get_sw_processor];
set hw_processor [common::get_property HW_INSTANCE $proc_instance]
set proc_type [common::get_property IP_NAME [hsi::get_cells $hw_processor]];
set proc_type [common::get_property IP_NAME [hsi::get_cells -hier $hw_processor]];
if { $proc_type != "ps7_cortexa9" } {
error "This application is supported only for CortexA9 processors.";

16
lib/sw_apps/xilkernel_thread_demo/data/xilkernel_thread_demo.tcl
View file

@ -13,9 +13,9 @@ proc get_stdout {} {
}
proc check_stdout_hw {} {
set slaves [common::get_property SLAVES [hsi::get_cells [hsi::get_sw_processor]]]
set slaves [common::get_property SLAVES [hsi::get_cells -hier [hsi::get_sw_processor]]]
foreach slave $slaves {
set slave_type [common::get_property IP_NAME [hsi::get_cells $slave]];
set slave_type [common::get_property IP_NAME [hsi::get_cells -hier $slave]];
# Check for MDM-Uart peripheral. The MDM would be listed as a peripheral
# only if it has a UART interface. So no further check is required
if { $slave_type == "ps7_uart" || $slave_type == "axi_uartlite" ||
@ -27,14 +27,14 @@ proc check_stdout_hw {} {
error "This application requires a Uart IP in the hardware."
# set uartlites [hsi::get_cells -filter { ip_name == "axi_uartlite" }];
# set uartlites [hsi::get_cells -hier -filter { ip_name == "axi_uartlite" }];
# if { [llength $uartlites] == 0 } {
# # we do not have an uartlite
# set uart16550s [hsi::get_cells -filter {ip_name == "axi_uart16550"}];
# set uart16550s [hsi::get_cells -hier -filter {ip_name == "axi_uart16550"}];
# if { [llength $uart16550s] == 0 } {
# # Check for MDM-Uart peripheral. The MDM would be listed as a peripheral
# # only if it has a UART interface. So no further check is required
# set mdmlist [hsi::get_cells -filter {ip_name == "mdm"}]
# set mdmlist [hsi::get_cells -hier -filter {ip_name == "mdm"}]
# if { [llength $mdmlist] == 0 } {
# error "This application requires a Uart IP in the hardware."
# }
@ -77,9 +77,9 @@ proc swapp_is_supported_hw {} {
if { $proc_type == 1} {
# make sure there is a timer (if this is a MB)
set timerlist [hsi::get_cells -filter {ip_name == "xps_timer"}];
set timerlist [hsi::get_cells -hier -filter {ip_name == "xps_timer"}];
if { [llength $timerlist] <= 0 } {
set timerlist [hsi::get_cells -filter {ip_name == "axi_timer"}];
set timerlist [hsi::get_cells -hier -filter {ip_name == "axi_timer"}];
if { [llength $timerlist] <= 0 } {
error "There seems to be no timer peripheral in the hardware. Xilkernel requires a timer for operation.";
}
@ -109,7 +109,7 @@ proc generate_stdout_config { fid } {
set stdout [get_stdout];
# if stdout is uartlite, we don't have to generate anything
set stdout_type [common::get_property IP_NAME [hsi::get_cells $stdout]];
set stdout_type [common::get_property IP_NAME [hsi::get_cells -hier $stdout]];
if { [regexp -nocase "uartlite" $stdout_type] || [string match -nocase "mdm" $stdout_type] } {
puts $fid "#define STDOUT_IS_UARTLITE";

4
lib/sw_apps/zynq_fsbl/data/zynq_fsbl.tcl
View file

@ -47,7 +47,7 @@ proc swapp_is_supported_hw {} {
set proc_instance [hsi::get_sw_processor];
set hw_processor [common::get_property HW_INSTANCE $proc_instance]
set proc_type [common::get_property IP_NAME [hsi::get_cells $hw_processor]];
set proc_type [common::get_property IP_NAME [hsi::get_cells -hier $hw_processor]];
if { $proc_type != "ps7_cortexa9" } {
error "This application is supported only for CortexA9 processors.";
@ -64,7 +64,7 @@ proc get_stdout {} {
}
proc check_stdout_hw {} {
set p7_uarts [hsi::get_cells -filter "IP_NAME=ps7_uart"];
set p7_uarts [hsi::get_cells -hier -filter "IP_NAME=ps7_uart"];
}
proc swapp_generate {} {

6
lib/sw_apps/zynqmp_fsbl/data/zynqmp_fsbl.tcl
View file

@ -77,7 +77,7 @@ proc swapp_is_supported_hw {} {
set proc_instance [hsi::get_sw_processor];
set hw_processor [common::get_property HW_INSTANCE $proc_instance]
set proc_type [common::get_property IP_NAME [hsi::get_cells $hw_processor]];
set proc_type [common::get_property IP_NAME [hsi::get_cells -hier $hw_processor]];
if { $proc_type != "psu_cortexr5" && $proc_type != "psu_cortexa53" } {
error "This application is supported only for CortexA53/CortexR5 processors.";
@ -94,7 +94,7 @@ proc get_stdout {} {
}
proc check_stdout_hw {} {
set pu_uarts [hsi::get_cells -filter "IP_NAME=psu_uart"];
set pu_uarts [hsi::get_cells -hier -filter "IP_NAME=psu_uart"];
}
proc swapp_generate {} {
@ -117,7 +117,7 @@ proc swapp_generate {} {
set proc_instance [hsi::get_sw_processor];
set hw_processor [common::get_property HW_INSTANCE $proc_instance]
set proc_type [common::get_property IP_NAME [hsi::get_cells $hw_processor]];
set proc_type [common::get_property IP_NAME [hsi::get_cells -hier $hw_processor]];
# based on the CPU (A53 or R5),
# remove unnecesary linker script and retain just one: lscript.ld

2
lib/sw_apps/zynqmp_pmufw/data/zynqmp_pmufw.tcl
View file

@ -59,7 +59,7 @@ proc swapp_is_supported_hw {} {
# check processor type
set proc_instance [hsi::get_sw_processor];
set hw_processor [common::get_property HW_INSTANCE $proc_instance]
set proc_type [common::get_property IP_NAME [hsi::get_cells $hw_processor]];
set proc_type [common::get_property IP_NAME [hsi::get_cells -hier $hw_processor]];
if {($proc_type != "psu_microblaze")} {
error "This application is supported only for PMU Microblaze processor (psu_microblaze).";

2
lib/sw_services/xilffs/data/xilffs.tcl
View file

@ -48,7 +48,7 @@ proc ffs_drc {libhandle} {
# Check if any IP instances that use FATFS are present
set sw_processor [hsi::get_sw_processor]
set processor [hsi::get_cells [common::get_property HW_INSTANCE $sw_processor]]
set processor [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_processor]]
set ffs_periphs_list [get_ffs_periphs $processor]

2
lib/sw_services/xilisf/data/xilisf.tcl
View file

@ -55,7 +55,7 @@ proc isf_drc {libhandle} {
# find the list of xps or opb spi cores
set sw_processor [hsi::get_sw_processor]
set processor [hsi::get_cells [common::get_property HW_INSTANCE $sw_processor]]
set processor [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_processor]]
set spi_periphs_list [get_spi_periphs $processor]

2
lib/sw_services/xilpm/data/xilpm.tcl
View file

@ -33,7 +33,7 @@
proc generate {libhandle} {
# Copy over the right set of files as src based on processor type
set sw_proc_handle [hsi::get_sw_processor]
set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle] ]
set hw_proc_handle [hsi::get_cells -hier [common::get_property HW_INSTANCE $sw_proc_handle] ]
set proctype [common::get_property IP_NAME $hw_proc_handle]
set procname [common::get_property NAME $hw_proc_handle]

2
lib/sw_services/xilrsa/data/xilrsa.tcl
View file

@ -47,7 +47,7 @@ proc rsa_drc {libhandle} {
set proc_instance [hsi::get_sw_processor];
set hw_processor [common::get_property HW_INSTANCE $proc_instance]
set proc_type [common::get_property IP_NAME [hsi::get_cells $hw_processor]];
set proc_type [common::get_property IP_NAME [hsi::get_cells -hier $hw_processor]];
if { $proc_type != "ps7_cortexa9" } {
error "ERROR: This library is supported only for CortexA9 processors.";