BSP: cortexa9: change in boot code
Modified boot code to enable scu after MMU is enabled and removed incorrect initialization of TLB lockdown register in gcc/boot.S & cpu_init.S, armcc/boot.S and iccarm/boot.s Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This commit is contained in:
Kinjal Pravinbhai Patel
Nava kishore Manne
parent
6d8be37a23
commit
e6d6e901cb
5 changed files with 47 additions and 36 deletions
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@ -212,4 +212,8 @@
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* 5.0 kvn 12/9/14 Support for Zync Ultrascale Mp.
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* 5.0 pkp 12/15/14 Added APIs to get information about the platforms running the code by
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* adding src/common/xplatform_info.*s
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* 5.0 pkp 16/12/14 Modified boot code to enable scu after MMU is enabled and
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* removed incorrect initialization of TLB lockdown register to fix
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* CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S
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* and iccarm/boot.s
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*****************************************************************************************/
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@ -51,6 +51,9 @@
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; 4.2 pkp 06/19/14 Enabled asynchronous abort exception
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; 4.2 pkp 08/04/14 Removed PEEP board related code which contained
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; initialization of uart smc nor and sram
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; 5.0 pkp 16/12/14 Modified initialization code to enable scu after
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; MMU is enabled and removed incorrect initialization
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; of TLB lockdown register to fix CR#830580
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; </pre>
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;
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; @note
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@ -163,17 +166,6 @@ OKToRun
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ldr r0, =_vector_table
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mcr p15, 0, r0, c12, c0, 0
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;set scu enable bit in scu
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ldr r7, =0xf8f00000
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ldr r0, [r7]
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orr r0, r0, #0x1
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str r0, [r7]
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;invalidate scu
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ldr r7, =0xf8f0000c
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ldr r6, =0xffff
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str r6, [r7]
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; Write to ACTLR
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mrc p15, 0,r0, c1, c0, 1 ; Read ACTLR
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orr r0, r0, #(0x01 << 6) ; SMP bit
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@ -302,6 +294,17 @@ mmu_loop:
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dsb ; dsb allow the MMU to start up
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isb ; isb flush prefetch buffer
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;set scu enable bit in scu
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ldr r7, =0xf8f00000
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ldr r0, [r7]
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orr r0, r0, #0x1
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str r0, [r7]
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;invalidate scu
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ldr r7, =0xf8f0000c
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ldr r6, =0xffff
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str r6, [r7]
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; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux)
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#if USE_AMP!=1
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ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
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@ -355,7 +358,6 @@ mmu_loop:
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mcr p15, 0, r0, c9, c13, 2 ; PMXEVCNTR
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mcr p15, 0, r0, c13, c0, 2 ; TPIDRURW
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mcr p15, 0, r0, c13, c0, 3 ; TPIDRURO
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mcr p15, 5, r0, c15, c5, 2 ; Write Lockdown TLB VA
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; Reset and start Cycle Counter
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mov r2, #0x80000000 ; clear overflow
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@ -55,6 +55,8 @@
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* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
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* 'xil_errata.h' for errata description
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* 4.2 pkp 06/19/14 Enabled asynchronous abort exception
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* 5.0 pkp 16/15/14 Modified initialization code to enable scu after
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* MMU is enabled
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* </pre>
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*
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* @note
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@ -180,17 +182,6 @@ OKToRun:
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ldr r0, =vector_base
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mcr p15, 0, r0, c12, c0, 0
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/*set scu enable bit in scu*/
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ldr r7, =0xf8f00000
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ldr r0, [r7]
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orr r0, r0, #0x1
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str r0, [r7]
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/*invalidate scu*/
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ldr r7, =0xf8f0000c
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ldr r6, =0xffff
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str r6, [r7]
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/* Write to ACTLR */
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mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/
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orr r0, r0, #(0x01 << 6) /* set SMP bit */
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@ -334,6 +325,17 @@ mmu_loop:
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isb /* isb flush prefetch buffer */
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/*set scu enable bit in scu*/
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ldr r7, =0xf8f00000
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ldr r0, [r7]
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orr r0, r0, #0x1
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str r0, [r7]
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/*invalidate scu*/
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ldr r7, =0xf8f0000c
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ldr r6, =0xffff
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str r6, [r7]
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/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */
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#if USE_AMP!=1
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ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
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@ -42,6 +42,8 @@
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* ----- ------- -------- ---------------------------------------------------
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* 1.00a ecm/sdm 10/20/09 Initial version
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* 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
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* 5.0 pkp 12/16/14 removed incorrect initialization of TLB lockdown
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* register to fix CR#830580
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* </pre>
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*
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* @note
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@ -64,7 +66,6 @@ __cpu_init:
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mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */
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mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */
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mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */
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mcr p15, 5, r0, c15, c5, 2 /* Write Lockdown TLB VA */
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/* Reset and start Cycle Counter */
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mov r2, #0x80000000 /* clear overflow */
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@ -43,6 +43,9 @@
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; 1.00a Initial version
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; 4.2 pkp 08/04/14 Removed PEEP board related code which contained
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; initialization of uart smc nor and sram
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; 5.0 pkp 16/12/14 Modified initialization code to enable scu after
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; MMU is enabled and removed incorrect initialization
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; of TLB lockdown register to fix CR#830580
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; </pre>
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;
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; @note
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@ -167,17 +170,6 @@ OKToRun
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ldr r0, =vector_base
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mcr p15, 0, r0, c12, c0, 0
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;set scu enable bit in scu
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ldr r7, =0xf8f00000
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ldr r0, [r7]
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orr r0, r0, #0x1
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str r0, [r7]
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;invalidate scu
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ldr r7, =0xf8f0000c
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ldr r6, =0xffff
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str r6, [r7]
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; Write to ACTLR
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mrc p15, 0,r0, c1, c0, 1 ; Read ACTLR
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orr r0, r0, #(0x01 << 6) ; SMP bit
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@ -320,6 +312,17 @@ mmu_loop
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dsb ; dsb allow the MMU to start up
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isb ; isb flush prefetch buffer
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;set scu enable bit in scu
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ldr r7, =0xf8f00000
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ldr r0, [r7]
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orr r0, r0, #0x1
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str r0, [r7]
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;invalidate scu
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ldr r7, =0xf8f0000c
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ldr r6, =0xffff
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str r6, [r7]
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; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux)
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#if USE_AMP!=1
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ldr r0,=SLCRUnlockReg ; Load SLCR base address base + unlock register
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@ -370,7 +373,6 @@ mmu_loop
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mcr p15, 0, r0, c9, c13, 2 ; PMXEVCNTR
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mcr p15, 0, r0, c13, c0, 2 ; TPIDRURW
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mcr p15, 0, r0, c13, c0, 3 ; TPIDRURO
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mcr p15, 5, r0, c15, c5, 2 ; Write Lockdown TLB VA
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; Reset and start Cycle Counter
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mov r2, #0x80000000 ; clear overflow
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