BSP: cortexa9: change in boot code
Modified boot code to enable scu after MMU is enabled and removed incorrect initialization of TLB lockdown register in gcc/boot.S & cpu_init.S, armcc/boot.S and iccarm/boot.s Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This commit is contained in:
parent
6d8be37a23
commit
e6d6e901cb
5 changed files with 47 additions and 36 deletions
|
@ -212,4 +212,8 @@
|
|||
* 5.0 kvn 12/9/14 Support for Zync Ultrascale Mp.
|
||||
* 5.0 pkp 12/15/14 Added APIs to get information about the platforms running the code by
|
||||
* adding src/common/xplatform_info.*s
|
||||
* 5.0 pkp 16/12/14 Modified boot code to enable scu after MMU is enabled and
|
||||
* removed incorrect initialization of TLB lockdown register to fix
|
||||
* CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S
|
||||
* and iccarm/boot.s
|
||||
*****************************************************************************************/
|
||||
|
|
|
@ -51,6 +51,9 @@
|
|||
; 4.2 pkp 06/19/14 Enabled asynchronous abort exception
|
||||
; 4.2 pkp 08/04/14 Removed PEEP board related code which contained
|
||||
; initialization of uart smc nor and sram
|
||||
; 5.0 pkp 16/12/14 Modified initialization code to enable scu after
|
||||
; MMU is enabled and removed incorrect initialization
|
||||
; of TLB lockdown register to fix CR#830580
|
||||
; </pre>
|
||||
;
|
||||
; @note
|
||||
|
@ -163,17 +166,6 @@ OKToRun
|
|||
ldr r0, =_vector_table
|
||||
mcr p15, 0, r0, c12, c0, 0
|
||||
|
||||
;set scu enable bit in scu
|
||||
ldr r7, =0xf8f00000
|
||||
ldr r0, [r7]
|
||||
orr r0, r0, #0x1
|
||||
str r0, [r7]
|
||||
|
||||
;invalidate scu
|
||||
ldr r7, =0xf8f0000c
|
||||
ldr r6, =0xffff
|
||||
str r6, [r7]
|
||||
|
||||
; Write to ACTLR
|
||||
mrc p15, 0,r0, c1, c0, 1 ; Read ACTLR
|
||||
orr r0, r0, #(0x01 << 6) ; SMP bit
|
||||
|
@ -302,6 +294,17 @@ mmu_loop:
|
|||
dsb ; dsb allow the MMU to start up
|
||||
isb ; isb flush prefetch buffer
|
||||
|
||||
;set scu enable bit in scu
|
||||
ldr r7, =0xf8f00000
|
||||
ldr r0, [r7]
|
||||
orr r0, r0, #0x1
|
||||
str r0, [r7]
|
||||
|
||||
;invalidate scu
|
||||
ldr r7, =0xf8f0000c
|
||||
ldr r6, =0xffff
|
||||
str r6, [r7]
|
||||
|
||||
; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux)
|
||||
#if USE_AMP!=1
|
||||
ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
|
||||
|
@ -355,7 +358,6 @@ mmu_loop:
|
|||
mcr p15, 0, r0, c9, c13, 2 ; PMXEVCNTR
|
||||
mcr p15, 0, r0, c13, c0, 2 ; TPIDRURW
|
||||
mcr p15, 0, r0, c13, c0, 3 ; TPIDRURO
|
||||
mcr p15, 5, r0, c15, c5, 2 ; Write Lockdown TLB VA
|
||||
|
||||
; Reset and start Cycle Counter
|
||||
mov r2, #0x80000000 ; clear overflow
|
||||
|
|
|
@ -55,6 +55,8 @@
|
|||
* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
|
||||
* 'xil_errata.h' for errata description
|
||||
* 4.2 pkp 06/19/14 Enabled asynchronous abort exception
|
||||
* 5.0 pkp 16/15/14 Modified initialization code to enable scu after
|
||||
* MMU is enabled
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
|
@ -180,17 +182,6 @@ OKToRun:
|
|||
ldr r0, =vector_base
|
||||
mcr p15, 0, r0, c12, c0, 0
|
||||
|
||||
/*set scu enable bit in scu*/
|
||||
ldr r7, =0xf8f00000
|
||||
ldr r0, [r7]
|
||||
orr r0, r0, #0x1
|
||||
str r0, [r7]
|
||||
|
||||
/*invalidate scu*/
|
||||
ldr r7, =0xf8f0000c
|
||||
ldr r6, =0xffff
|
||||
str r6, [r7]
|
||||
|
||||
/* Write to ACTLR */
|
||||
mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/
|
||||
orr r0, r0, #(0x01 << 6) /* set SMP bit */
|
||||
|
@ -334,6 +325,17 @@ mmu_loop:
|
|||
|
||||
isb /* isb flush prefetch buffer */
|
||||
|
||||
/*set scu enable bit in scu*/
|
||||
ldr r7, =0xf8f00000
|
||||
ldr r0, [r7]
|
||||
orr r0, r0, #0x1
|
||||
str r0, [r7]
|
||||
|
||||
/*invalidate scu*/
|
||||
ldr r7, =0xf8f0000c
|
||||
ldr r6, =0xffff
|
||||
str r6, [r7]
|
||||
|
||||
/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */
|
||||
#if USE_AMP!=1
|
||||
ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
|
||||
|
|
|
@ -42,6 +42,8 @@
|
|||
* ----- ------- -------- ---------------------------------------------------
|
||||
* 1.00a ecm/sdm 10/20/09 Initial version
|
||||
* 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
|
||||
* 5.0 pkp 12/16/14 removed incorrect initialization of TLB lockdown
|
||||
* register to fix CR#830580
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
|
@ -64,7 +66,6 @@ __cpu_init:
|
|||
mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */
|
||||
mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */
|
||||
mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */
|
||||
mcr p15, 5, r0, c15, c5, 2 /* Write Lockdown TLB VA */
|
||||
|
||||
/* Reset and start Cycle Counter */
|
||||
mov r2, #0x80000000 /* clear overflow */
|
||||
|
|
|
@ -43,6 +43,9 @@
|
|||
; 1.00a Initial version
|
||||
; 4.2 pkp 08/04/14 Removed PEEP board related code which contained
|
||||
; initialization of uart smc nor and sram
|
||||
; 5.0 pkp 16/12/14 Modified initialization code to enable scu after
|
||||
; MMU is enabled and removed incorrect initialization
|
||||
; of TLB lockdown register to fix CR#830580
|
||||
; </pre>
|
||||
;
|
||||
; @note
|
||||
|
@ -167,17 +170,6 @@ OKToRun
|
|||
ldr r0, =vector_base
|
||||
mcr p15, 0, r0, c12, c0, 0
|
||||
|
||||
;set scu enable bit in scu
|
||||
ldr r7, =0xf8f00000
|
||||
ldr r0, [r7]
|
||||
orr r0, r0, #0x1
|
||||
str r0, [r7]
|
||||
|
||||
;invalidate scu
|
||||
ldr r7, =0xf8f0000c
|
||||
ldr r6, =0xffff
|
||||
str r6, [r7]
|
||||
|
||||
; Write to ACTLR
|
||||
mrc p15, 0,r0, c1, c0, 1 ; Read ACTLR
|
||||
orr r0, r0, #(0x01 << 6) ; SMP bit
|
||||
|
@ -320,6 +312,17 @@ mmu_loop
|
|||
dsb ; dsb allow the MMU to start up
|
||||
isb ; isb flush prefetch buffer
|
||||
|
||||
;set scu enable bit in scu
|
||||
ldr r7, =0xf8f00000
|
||||
ldr r0, [r7]
|
||||
orr r0, r0, #0x1
|
||||
str r0, [r7]
|
||||
|
||||
;invalidate scu
|
||||
ldr r7, =0xf8f0000c
|
||||
ldr r6, =0xffff
|
||||
str r6, [r7]
|
||||
|
||||
; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux)
|
||||
#if USE_AMP!=1
|
||||
ldr r0,=SLCRUnlockReg ; Load SLCR base address base + unlock register
|
||||
|
@ -370,7 +373,6 @@ mmu_loop
|
|||
mcr p15, 0, r0, c9, c13, 2 ; PMXEVCNTR
|
||||
mcr p15, 0, r0, c13, c0, 2 ; TPIDRURW
|
||||
mcr p15, 0, r0, c13, c0, 3 ; TPIDRURO
|
||||
mcr p15, 5, r0, c15, c5, 2 ; Write Lockdown TLB VA
|
||||
|
||||
; Reset and start Cycle Counter
|
||||
mov r2, #0x80000000 ; clear overflow
|
||||
|
|
Loading…
Add table
Reference in a new issue