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sw_apps:zynq_fsbl: Corrected the format specifier in print statements

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Changed the format specifiers from %x to %lx and %d to %lu
while printing unsigned long variables.
Without these changes many warnings are shown in FSBL when xil_printf
type in BSP is changed to be compatible with printf.

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
This commit is contained in:
Sarat Chand Savitala 2015-08-06 16:27:39 +05:30 • committed by Nava kishore Manne
parent da9e3d6e71
commit e8ac191579
5 changed files with 49 additions and 49 deletions
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36
lib/sw_apps/zynq_fsbl/src/image_mover.c
View file

@ -187,7 +187,7 @@ u32 LoadBootImage(void)
RebootStatusRegister = Xil_In32(REBOOT_STATUS_REG);
fsbl_printf(DEBUG_INFO,
"Reboot status register: 0x%08x\r\n",RebootStatusRegister);
"Reboot status register: 0x%08lx\r\n",RebootStatusRegister);
if (Silicon_Version == SILICON_VERSION_1) {
/*
@ -213,7 +213,7 @@ u32 LoadBootImage(void)
MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
XDCFG_MULTIBOOT_ADDR_OFFSET);
fsbl_printf(DEBUG_INFO,"Multiboot Register: 0x%08x\r\n",MultiBootReg);
fsbl_printf(DEBUG_INFO,"Multiboot Register: 0x%08lx\r\n",MultiBootReg);
/*
* Compute the image start address
@ -222,7 +222,7 @@ u32 LoadBootImage(void)
* GOLDEN_IMAGE_OFFSET;
}
fsbl_printf(DEBUG_INFO,"Image Start Address: 0x%08x\r\n",ImageStartAddress);
fsbl_printf(DEBUG_INFO,"Image Start Address: 0x%08lx\r\n",ImageStartAddress);
/*
* Get partitions header information
@ -299,7 +299,7 @@ u32 LoadBootImage(void)
while (PartitionNum < PartitionCount) {
fsbl_printf(DEBUG_INFO, "Partition Number: %d\r\n", PartitionNum);
fsbl_printf(DEBUG_INFO, "Partition Number: %lu\r\n", PartitionNum);
HeaderPtr = &PartitionHeader[PartitionNum];
@ -339,7 +339,7 @@ u32 LoadBootImage(void)
* if FSBL is not the owner of partition,
* skip this partition, continue with next partition
*/
fsbl_printf(DEBUG_INFO, "Skipping partition %0x\r\n",
fsbl_printf(DEBUG_INFO, "Skipping partition %0lx\r\n",
PartitionNum);
/*
* Increment partition number
@ -606,7 +606,7 @@ u32 GetPartitionHeaderInfo(u32 ImageBaseAddress)
*/
PartitionHeaderOffset += ImageBaseAddress;
fsbl_printf(DEBUG_INFO,"Partition Header Offset:0x%08x\r\n",
fsbl_printf(DEBUG_INFO,"Partition Header Offset:0x%08lx\r\n",
PartitionHeaderOffset);
/*
@ -624,7 +624,7 @@ u32 GetPartitionHeaderInfo(u32 ImageBaseAddress)
*/
PartitionCount = GetPartitionCount(&PartitionHeader[0]);
fsbl_printf(DEBUG_INFO, "Partition Count: %d\r\n", PartitionCount);
fsbl_printf(DEBUG_INFO, "Partition Count: %lu\r\n", PartitionCount);
/*
* Partition Count check
@ -814,25 +814,25 @@ u32 LoadPartitionsHeaderInfo(u32 PartHeaderOffset, PartHeader *Header)
void HeaderDump(PartHeader *Header)
{
fsbl_printf(DEBUG_INFO, "Header Dump\r\n");
fsbl_printf(DEBUG_INFO, "Image Word Len: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO, "Image Word Len: 0x%08lx\r\n",
Header->ImageWordLen);
fsbl_printf(DEBUG_INFO, "Data Word Len: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO, "Data Word Len: 0x%08lx\r\n",
Header->DataWordLen);
fsbl_printf(DEBUG_INFO, "Partition Word Len:0x%08x\r\n",
fsbl_printf(DEBUG_INFO, "Partition Word Len:0x%08lx\r\n",
Header->PartitionWordLen);
fsbl_printf(DEBUG_INFO, "Load Addr: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO, "Load Addr: 0x%08lx\r\n",
Header->LoadAddr);
fsbl_printf(DEBUG_INFO, "Exec Addr: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO, "Exec Addr: 0x%08lx\r\n",
Header->ExecAddr);
fsbl_printf(DEBUG_INFO, "Partition Start: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO, "Partition Start: 0x%08lx\r\n",
Header->PartitionStart);
fsbl_printf(DEBUG_INFO, "Partition Attr: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO, "Partition Attr: 0x%08lx\r\n",
Header->PartitionAttr);
fsbl_printf(DEBUG_INFO, "Partition Checksum Offset: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO, "Partition Checksum Offset: 0x%08lx\r\n",
Header->CheckSumOffset);
fsbl_printf(DEBUG_INFO, "Section Count: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO, "Section Count: 0x%08lx\r\n",
Header->SectionCount);
fsbl_printf(DEBUG_INFO, "Checksum: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO, "Checksum: 0x%08lx\r\n",
Header->CheckSum);
}
@ -1017,7 +1017,7 @@ u32 ValidatePartitionHeaderChecksum(struct HeaderArray *H)
* Validate the checksum
*/
if (H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT] != Checksum) {
fsbl_printf(DEBUG_GENERAL, "Error: Checksum 0x%8.8x != 0x%8.8x\r\n",
fsbl_printf(DEBUG_GENERAL, "Error: Checksum 0x%8.8lx != 0x%8.8lx\r\n",
Checksum, H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT]);
return XST_FAILURE;
}

14
lib/sw_apps/zynq_fsbl/src/main.c
View file

@ -509,7 +509,7 @@ int main(void)
FsblFallback();
}
fsbl_printf(DEBUG_INFO,"Flash Base Address: 0x%08x\r\n", FlashReadBaseAddress);
fsbl_printf(DEBUG_INFO,"Flash Base Address: 0x%08lx\r\n", FlashReadBaseAddress);
/*
* Check for valid flash address
@ -549,7 +549,7 @@ int main(void)
*/
HandoffAddress = LoadBootImage();
fsbl_printf(DEBUG_INFO,"Handoff Address: 0x%08x\r\n",HandoffAddress);
fsbl_printf(DEBUG_INFO,"Handoff Address: 0x%08lx\r\n",HandoffAddress);
/*
* For Performance measurement
@ -800,7 +800,7 @@ void OutputStatus(u32 State)
#ifdef STDOUT_BASEADDRESS
u32 UartReg = 0;
fsbl_printf(DEBUG_GENERAL,"FSBL Status = 0x%.4x\r\n", State);
fsbl_printf(DEBUG_GENERAL,"FSBL Status = 0x%.4lx\r\n", State);
/*
* The TX buffer needs to be flushed out
* If this is not done some of the prints will not appear on the
@ -1034,7 +1034,7 @@ static void Update_MultiBootRegister(void)
XDCFG_MULTIBOOT_ADDR_OFFSET,
MultiBootReg);
fsbl_printf(DEBUG_INFO,"Updated MultiBootReg = 0x%08x\r\n",
fsbl_printf(DEBUG_INFO,"Updated MultiBootReg = 0x%08lx\r\n",
MultiBootReg);
}
}
@ -1296,7 +1296,7 @@ void GetSiliconVersion(void)
if(Silicon_Version == SILICON_VERSION_3_1) {
fsbl_printf(DEBUG_GENERAL,"Silicon Version 3.1\r\n");
} else {
fsbl_printf(DEBUG_GENERAL,"Silicon Version %d.0\r\n",
fsbl_printf(DEBUG_GENERAL,"Silicon Version %lu.0\r\n",
Silicon_Version + 1);
}
}
@ -1343,7 +1343,7 @@ u32 HeaderChecksum(u32 FlashOffsetAddress){
* Validate the checksum
*/
if (TempValue != Checksum){
fsbl_printf(DEBUG_INFO, "Checksum = %8.8x\r\n", Checksum);
fsbl_printf(DEBUG_INFO, "Checksum = %8.8lx\r\n", Checksum);
return XST_FAILURE;
}
@ -1448,7 +1448,7 @@ u32 NextValidImageCheck(void)
if ((ImageCheckID(ImageBaseAddr) == XST_SUCCESS) &&
(HeaderChecksum(ImageBaseAddr) == XST_SUCCESS)) {
fsbl_printf(DEBUG_GENERAL, "\r\nImage found, offset: 0x%.8x\r\n",
fsbl_printf(DEBUG_GENERAL, "\r\nImage found, offset: 0x%.8lx\r\n",
ImageBaseAddr);
/*
* Update multiboot register

44
lib/sw_apps/zynq_fsbl/src/pcap.c
View file

@ -187,7 +187,7 @@ u32 PcapDataTransfer(u32 *SourceDataPtr, u32 *DestinationDataPtr,
(u8 *)DestinationDataPtr,
DestinationLength, PcapTransferType);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %d \r \n",Status);
fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %lu \r \n",Status);
return XST_FAILURE;
}
@ -308,7 +308,7 @@ u32 PcapLoadPartition(u32 *SourceDataPtr, u32 *DestinationDataPtr,
(u8 *)DestinationDataPtr,
DestinationLength, PcapTransferType);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %d \r \n",Status);
fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %lu \r \n",Status);
return XST_FAILURE;
}
@ -420,7 +420,7 @@ void FabricInit(void)
* Set Level Shifters DT618760 - PS to PL enabling
*/
Xil_Out32(PS_LVL_SHFTR_EN, LVL_PS_PL);
fsbl_printf(DEBUG_INFO,"Level Shifter Value = 0x%x \r\n",
fsbl_printf(DEBUG_INFO,"Level Shifter Value = 0x%lx \r\n",
Xil_In32(PS_LVL_SHFTR_EN));
/*
@ -484,7 +484,7 @@ void FabricInit(void)
* Get Device configuration status
*/
StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr);
fsbl_printf(DEBUG_INFO,"Devcfg Status register = 0x%x \r\n",StatusReg);
fsbl_printf(DEBUG_INFO,"Devcfg Status register = 0x%lx \r\n",StatusReg);
fsbl_printf(DEBUG_INFO,"PCAP:Fabric is Initialized done\r\n");
}
@ -519,7 +519,7 @@ u32 ClearPcapStatus(void)
*/
IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr);
if (IntStatusReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %x\r\n",
fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %lx\r\n",
IntStatusReg);
return XST_FAILURE;
}
@ -529,7 +529,7 @@ u32 ClearPcapStatus(void)
*/
StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr);
fsbl_printf(DEBUG_INFO,"PCAP:StatusReg = 0x%.8x\r\n", StatusReg);
fsbl_printf(DEBUG_INFO,"PCAP:StatusReg = 0x%.8lx\r\n", StatusReg);
/*
* If the queue is full, return w/ XST_DEVICE_BUSY
@ -593,49 +593,49 @@ void PcapDumpRegisters (void) {
fsbl_printf(DEBUG_INFO,"PCAP register dump:\r\n");
fsbl_printf(DEBUG_INFO,"PCAP CTRL 0x%x: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO,"PCAP CTRL 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP LOCK 0x%x: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO,"PCAP LOCK 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP CONFIG 0x%x: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO,"PCAP CONFIG 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP ISR 0x%x: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO,"PCAP ISR 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP IMR 0x%x: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO,"PCAP IMR 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP STATUS 0x%x: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO,"PCAP STATUS 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP DMA SRC ADDR 0x%x: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO,"PCAP DMA SRC ADDR 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP DMA DEST ADDR 0x%x: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO,"PCAP DMA DEST ADDR 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP DMA SRC LEN 0x%x: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO,"PCAP DMA SRC LEN 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP DMA DEST LEN 0x%x: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO,"PCAP DMA DEST LEN 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP ROM SHADOW CTRL 0x%x: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO,"PCAP ROM SHADOW CTRL 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP MBOOT 0x%x: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO,"PCAP MBOOT 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP SW ID 0x%x: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO,"PCAP SW ID 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP UNLOCK 0x%x: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO,"PCAP UNLOCK 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP MCTRL 0x%x: 0x%08x\r\n",
fsbl_printf(DEBUG_INFO,"PCAP MCTRL 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET));
}
@ -669,7 +669,7 @@ int XDcfgPollDone(u32 MaskValue, u32 MaxCount)
Count -=1;
if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %x\r\n",
fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %lx\r\n",
IntrStsReg);
PcapDumpRegisters();
return XST_FAILURE;

2
lib/sw_apps/zynq_fsbl/src/qspi.c
View file

@ -550,7 +550,7 @@ u32 QspiAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
if ((SourceAddress >= FLASH_SIZE_16MB) && (BankSwitchFlag == 1)) {
BankSel = SourceAddress/FLASH_SIZE_16MB;
fsbl_printf(DEBUG_INFO, "Bank Selection %d\n\r", BankSel);
fsbl_printf(DEBUG_INFO, "Bank Selection %lu\n\r", BankSel);
Status = SendBankSelect(BankSel);
if (Status != XST_SUCCESS) {

2
lib/sw_apps/zynq_fsbl/src/sd.c
View file

@ -152,7 +152,7 @@ u32 SDAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
rc = f_lseek(&fil, SourceAddress);
if (rc) {
fsbl_printf(DEBUG_INFO,"SD: Unable to seek to %x\n", SourceAddress);
fsbl_printf(DEBUG_INFO,"SD: Unable to seek to %lx\n", SourceAddress);
return XST_FAILURE;
}