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bsp: a9: initialization order change in boot code

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This patch changes the initialization order in boot.S to follow
the correct order as specified in CortexA9 TRM

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This commit is contained in:
Kinjal Pravinbhai Patel 2015-05-13 12:42:03 +05:30 • committed by Nava kishore Manne
parent f112f71d81
commit ed26a3d6f0
4 changed files with 198 additions and 192 deletions
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4
lib/bsp/standalone/src/changelog.txt
View file

@ -219,4 +219,8 @@
* and iccarm/boot.s
* 5.0 pkp 25/02/15 Modified floating point flag to vfpv3 from vfpv3_d16 in BSP MakeFile
* for iccarm and armcc compiler of cortexA9
* 5.1 pkp 05/13/15 Changed the initialization order in cortexa9/gcc/boot.S, iccarm/boot.s
* and armcc/boot.s so to first invalidate caches and TLB, enable MMU and
* caches, then enable SMP bit in ACTLR. L2Cache invalidation and enabling
* of L2Cache is done later.
*****************************************************************************************/

129
lib/bsp/standalone/src/cortexa9/armcc/boot.S
View file

@ -54,6 +54,10 @@
; 5.0 pkp 16/12/14 Modified initialization code to enable scu after
; MMU is enabled and removed incorrect initialization
; of TLB lockdown register to fix CR#830580
; 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
; caches and TLB, enable MMU and caches, then enable SMP
; bit in ACTLR. L2Cache invalidation and enabling of L2Cache
; is done later.
; </pre>
;
; @note
@ -166,58 +170,18 @@ OKToRun
ldr r0, =_vector_table
mcr p15, 0, r0, c12, c0, 0
; Write to ACTLR
mrc p15, 0,r0, c1, c0, 1 ; Read ACTLR
orr r0, r0, #(0x01 << 6) ; SMP bit
orr r0, r0, #(0x01 ) ; Cache/TLB maintenance broadcast
mcr p15, 0,r0, c1, c0, 1 ; Write ACTLR
;invalidate scu
ldr r7, =0xf8f0000c
ldr r6, =0xffff
str r6, [r7]
; Invalidate caches and TLBs
;Invalidate caches and TLBs
mov r0,#0 ; r0 = 0
mcr p15, 0, r0, c8, c7, 0 ; invalidate TLBs
mcr p15, 0, r0, c7, c5, 0 ; invalidate icache
mcr p15, 0, r0, c7, c5, 6 ; Invalidate branch predictor array
bl invalidate_dcache ; invalidate dcache
; Invalidate L2c Cache
; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux)
#if USE_AMP!=1
ldr r0,=L2CCCrtl ; Load L2CC base address base + control register
mov r1, #0 ; force the disable bit
str r1, [r0] ; disable the L2 Caches
ldr r0,=L2CCAuxCrtl ; Load L2CC base address base + Aux control register
ldr r1,[r0] ; read the register
ldr r2,=L2CCAuxControl ; set the default bits
orr r1,r1,r2
str r1, [r0] ; store the Aux Control Register
ldr r0,=L2CCTAGLatReg ; Load L2CC base address base + TAG Latency address
ldr r1,=L2CCTAGLatency ; set the latencies for the TAG
str r1, [r0] ; store the TAG Latency register Register
ldr r0,=L2CCDataLatReg ; Load L2CC base address base + Data Latency address
ldr r1,=L2CCDataLatency ; set the latencies for the Data
str r1, [r0] ; store the Data Latency register Register
ldr r0,=L2CCWay ; Load L2CC base address base + way register
ldr r2, =0xFFFF
str r2, [r0] ; force invalidate
ldr r0,=L2CCSync ; need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET
; Load L2CC base address base + sync register
; poll for completion
Sync
ldr r1, [r0]
cmp r1, #0
bne Sync
ldr r0,=L2CCIntRaw ; clear pending interrupts
ldr r1,[r0]
ldr r0,=L2CCIntClear
str r1,[r0]
#endif
; Disable MMU, if enabled
mrc p15, 0, r0, c1, c0, 0 ; read CP15 register 1
bic r0, r0, #0x1 ; clear bit 0
@ -278,6 +242,12 @@ mmu_loop:
msr apsr, r2 ; was cpsr, apsr is considered synonym
ldr r13,=|Image$$ARM_LIB_STACK$$ZI$$Limit| ; SYS stack pointer
;set scu enable bit in scu
ldr r7, =0xf8f00000
ldr r0, [r7]
orr r0, r0, #0x1
str r0, [r7]
; enable MMU and cache
ldr r0,=MMUTable ; Load MMU translation table base
@ -294,30 +264,61 @@ mmu_loop:
dsb ; dsb allow the MMU to start up
isb ; isb flush prefetch buffer
;set scu enable bit in scu
ldr r7, =0xf8f00000
ldr r0, [r7]
orr r0, r0, #0x1
str r0, [r7]
;invalidate scu
ldr r7, =0xf8f0000c
ldr r6, =0xffff
str r6, [r7]
; Write to ACTLR
mrc p15, 0,r0, c1, c0, 1 ; Read ACTLR
orr r0, r0, #(0x01 << 6) ; SMP bit
orr r0, r0, #(0x01 ) ; Cache/TLB maintenance broadcast
mcr p15, 0,r0, c1, c0, 1 ; Write ACTLR
; Invalidate L2 Cache and initialize L2 Cache
; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux)
#if USE_AMP!=1
ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
ldr r1,=SLCRUnlockKey /* set unlock key */
str r1, [r0] /* Unlock SLCR */
ldr r0,=L2CCCrtl ; Load L2CC base address base + control register
mov r1, #0 ; force the disable bit
str r1, [r0] ; disable the L2 Caches
ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */
ldr r1,=SLCRL2cRamConfig /* set the configuration value */
str r1, [r0] /* store the L2c Ram Control Register */
ldr r0,=L2CCAuxCrtl ; Load L2CC base address base + Aux control register
ldr r1,[r0] ; read the register
ldr r2,=L2CCAuxControl ; set the default bits
orr r1,r1,r2
str r1, [r0] ; store the Aux Control Register
ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
ldr r1,=SLCRlockKey /* set lock key */
str r1, [r0] /* lock SLCR */
ldr r0,=L2CCTAGLatReg ; Load L2CC base address base + TAG Latency address
ldr r1,=L2CCTAGLatency ; set the latencies for the TAG
str r1, [r0] ; store the TAG Latency register Register
ldr r0,=L2CCDataLatReg ; Load L2CC base address base + Data Latency address
ldr r1,=L2CCDataLatency ; set the latencies for the Data
str r1, [r0] ; store the Data Latency register Register
ldr r0,=L2CCWay ; Load L2CC base address base + way register
ldr r2, =0xFFFF
str r2, [r0] ; force invalidate
ldr r0,=L2CCSync ; need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET
; Load L2CC base address base + sync register
; poll for completion
Sync
ldr r1, [r0]
cmp r1, #0
bne Sync
ldr r0,=L2CCIntRaw ; clear pending interrupts
ldr r1,[r0]
ldr r0,=L2CCIntClear
str r1,[r0]
ldr r0,=SLCRUnlockReg ;Load SLCR base address base + unlock register
ldr r1,=SLCRUnlockKey ;set unlock key
str r1, [r0] ;Unlock SLCR
ldr r0,=SLCRL2cRamReg ;Load SLCR base address base + l2c Ram Control register
ldr r1,=SLCRL2cRamConfig ;set the configuration value
str r1, [r0] ;store the L2c Ram Control Register
ldr r0,=SLCRlockReg ;Load SLCR base address base + lock register
ldr r1,=SLCRlockKey ;set lock key
str r1, [r0] ;lock SLCR
ldr r0,=L2CCCrtl ; Load L2CC base address base + control register
ldr r1,[r0] ; read the register

144
lib/bsp/standalone/src/cortexa9/gcc/boot.S
View file

@ -57,6 +57,10 @@
* 4.2 pkp 06/19/14 Enabled asynchronous abort exception
* 5.0 pkp 16/15/14 Modified initialization code to enable scu after
* MMU is enabled
* 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
* caches and TLB, enable MMU and caches, then enable SMP
* bit in ACTLR. L2Cache invalidation and enabling of L2Cache
* is done later.
* </pre>
*
* @note
@ -182,57 +186,18 @@ OKToRun:
ldr r0, =vector_base
mcr p15, 0, r0, c12, c0, 0
/* Write to ACTLR */
mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/
orr r0, r0, #(0x01 << 6) /* set SMP bit */
orr r0, r0, #(0x01 ) /* */
mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
/*invalidate scu*/
ldr r7, =0xf8f0000c
ldr r6, =0xffff
str r6, [r7]
/* Invalidate caches and TLBs */
/* Invalidate caches and TLBs */
mov r0,#0 /* r0 = 0 */
mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */
bl invalidate_dcache /* invalidate dcache */
/* Invalidate L2c Cache */
/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */
#if USE_AMP!=1
ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
mov r1, #0 /* force the disable bit */
str r1, [r0] /* disable the L2 Caches */
ldr r0,=L2CCAuxCrtl /* Load L2CC base address base + Aux control register */
ldr r1,[r0] /* read the register */
ldr r2,=L2CCAuxControl /* set the default bits */
orr r1,r1,r2
str r1, [r0] /* store the Aux Control Register */
ldr r0,=L2CCTAGLatReg /* Load L2CC base address base + TAG Latency address */
ldr r1,=L2CCTAGLatency /* set the latencies for the TAG*/
str r1, [r0] /* store the TAG Latency register Register */
ldr r0,=L2CCDataLatReg /* Load L2CC base address base + Data Latency address */
ldr r1,=L2CCDataLatency /* set the latencies for the Data*/
str r1, [r0] /* store the Data Latency register Register */
ldr r0,=L2CCWay /* Load L2CC base address base + way register*/
ldr r2, =0xFFFF
str r2, [r0] /* force invalidate */
ldr r0,=L2CCSync /* need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET */
/* Load L2CC base address base + sync register*/
/* poll for completion */
Sync: ldr r1, [r0]
cmp r1, #0
bne Sync
ldr r0,=L2CCIntRaw /* clear pending interrupts */
ldr r1,[r0]
ldr r0,=L2CCIntClear
str r1,[r0]
#endif
/* Disable MMU, if enabled */
mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */
bic r0, r0, #0x1 /* clear bit 0 */
@ -307,48 +272,81 @@ mmu_loop:
msr cpsr, r2
ldr r13,=SYS_stack /* SYS stack pointer */
/* enable MMU and cache */
ldr r0,=TblBase /* Load MMU translation table base */
orr r0, r0, #0x5B /* Outer-cacheable, WB */
mcr 15, 0, r0, c2, c0, 0 /* TTB0 */
mvn r0,#0 /* Load MMU domains -- all ones=manager */
mcr p15,0,r0,c3,c0,0
/* Enable mmu, icahce and dcache */
ldr r0,=CRValMmuCac
mcr p15,0,r0,c1,c0,0 /* Enable cache and MMU */
dsb /* dsb allow the MMU to start up */
isb /* isb flush prefetch buffer */
/*set scu enable bit in scu*/
ldr r7, =0xf8f00000
ldr r0, [r7]
orr r0, r0, #0x1
str r0, [r7]
/*invalidate scu*/
ldr r7, =0xf8f0000c
ldr r6, =0xffff
str r6, [r7]
/* enable MMU and cache */
ldr r0,=TblBase /* Load MMU translation table base */
orr r0, r0, #0x5B /* Outer-cacheable, WB */
mcr 15, 0, r0, c2, c0, 0 /* TTB0 */
mvn r0,#0 /* Load MMU domains -- all ones=manager */
mcr p15,0,r0,c3,c0,0
/* Enable mmu, icahce and dcache */
ldr r0,=CRValMmuCac
mcr p15,0,r0,c1,c0,0 /* Enable cache and MMU */
dsb /* dsb allow the MMU to start up */
isb /* isb flush prefetch buffer */
/* Write to ACTLR */
mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/
orr r0, r0, #(0x01 << 6) /* set SMP bit */
orr r0, r0, #(0x01 ) /* */
mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
/* Invalidate L2 Cache and enable L2 Cache*/
/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */
#if USE_AMP!=1
ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
mov r1, #0 /* force the disable bit */
str r1, [r0] /* disable the L2 Caches */
ldr r0,=L2CCAuxCrtl /* Load L2CC base address base + Aux control register */
ldr r1,[r0] /* read the register */
ldr r2,=L2CCAuxControl /* set the default bits */
orr r1,r1,r2
str r1, [r0] /* store the Aux Control Register */
ldr r0,=L2CCTAGLatReg /* Load L2CC base address base + TAG Latency address */
ldr r1,=L2CCTAGLatency /* set the latencies for the TAG*/
str r1, [r0] /* store the TAG Latency register Register */
ldr r0,=L2CCDataLatReg /* Load L2CC base address base + Data Latency address */
ldr r1,=L2CCDataLatency /* set the latencies for the Data*/
str r1, [r0] /* store the Data Latency register Register */
ldr r0,=L2CCWay /* Load L2CC base address base + way register*/
ldr r2, =0xFFFF
str r2, [r0] /* force invalidate */
ldr r0,=L2CCSync /* need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET */
/* Load L2CC base address base + sync register*/
/* poll for completion */
Sync: ldr r1, [r0]
cmp r1, #0
bne Sync
ldr r0,=L2CCIntRaw /* clear pending interrupts */
ldr r1,[r0]
ldr r0,=L2CCIntClear
str r1,[r0]
ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
ldr r1,=SLCRUnlockKey /* set unlock key */
str r1, [r0] /* Unlock SLCR */
ldr r1,=SLCRUnlockKey /* set unlock key */
str r1, [r0] /* Unlock SLCR */
ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */
ldr r1,=SLCRL2cRamConfig /* set the configuration value */
str r1, [r0] /* store the L2c Ram Control Register */
ldr r1,=SLCRL2cRamConfig /* set the configuration value */
str r1, [r0] /* store the L2c Ram Control Register */
ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
ldr r1,=SLCRlockKey /* set lock key */
str r1, [r0] /* lock SLCR */
ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
ldr r1,=SLCRlockKey /* set lock key */
str r1, [r0] /* lock SLCR */
ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
ldr r1,[r0] /* read the register */

113
lib/bsp/standalone/src/cortexa9/iccarm/boot.s
View file

@ -46,6 +46,10 @@
; 5.0 pkp 16/12/14 Modified initialization code to enable scu after
; MMU is enabled and removed incorrect initialization
; of TLB lockdown register to fix CR#830580
; 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
; caches and TLB, enable MMU and caches, then enable SMP
; bit in ACTLR. L2Cache invalidation and enabling of L2Cache
; is done later.
; </pre>
;
; @note
@ -170,57 +174,18 @@ OKToRun
ldr r0, =vector_base
mcr p15, 0, r0, c12, c0, 0
; Write to ACTLR
mrc p15, 0,r0, c1, c0, 1 ; Read ACTLR
orr r0, r0, #(0x01 << 6) ; SMP bit
orr r0, r0, #(0x01 ) ; Cache/TLB maintenance broadcast
mcr p15, 0,r0, c1, c0, 1 ; Write ACTLR
;invalidate scu
ldr r7, =0xf8f0000c
ldr r6, =0xffff
str r6, [r7]
; Invalidate caches and TLBs
;Invalidate caches and TLBs
mov r0,#0 ; r0 = 0
mcr p15, 0, r0, c8, c7, 0 ; invalidate TLBs
mcr p15, 0, r0, c7, c5, 0 ; invalidate icache
mcr p15, 0, r0, c7, c5, 6 ; Invalidate branch predictor array
bl invalidate_dcache ; invalidate dcache
; Invalidate L2c Cache
; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux)
#if USE_AMP!=1
ldr r0,=L2CCCrtl ; Load L2CC base address base + control register
mov r1, #0 ; force the disable bit
str r1, [r0] ; disable the L2 Caches
ldr r0,=L2CCAuxCrtl ; Load L2CC base address base + Aux control register
ldr r1,[r0] ; read the register
ldr r2,=L2CCAuxControl ; set the default bits
orr r1,r1,r2
str r1, [r0] ; store the Aux Control Register
ldr r0,=L2CCTAGLatReg ; Load L2CC base address base + TAG Latency address
ldr r1,=L2CCTAGLatency ; set the latencies for the TAG
str r1, [r0] ; store the TAG Latency register Register
ldr r0,=L2CCDataLatReg ; Load L2CC base address base + Data Latency address
ldr r1,=L2CCDataLatency ; set the latencies for the Data
str r1, [r0] ; store the Data Latency register Register
ldr r0,=L2CCWay ; Load L2CC base address base + way register
ldr r2, =0xFFFF
str r2, [r0] ; force invalidate
ldr r0,=L2CCSync ; need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET
; Load L2CC base address base + sync register
; poll for completion
Sync
ldr r1, [r0]
cmp r1, #0
bne Sync
ldr r0,=L2CCIntRaw ; clear pending interrupts
ldr r1,[r0]
ldr r0,=L2CCIntClear
str r1,[r0]
#endif
; Disable MMU, if enabled
mrc p15, 0, r0, c1, c0, 0 ; read CP15 register 1
@ -296,6 +261,12 @@ mmu_loop
msr cpsr, r2 ; was cpsr, apsr is considered synonym
ldr r13,=SFE(CSTACK) ; SYS stack pointer
;set scu enable bit in scu
ldr r7, =0xf8f00000
ldr r0, [r7]
orr r0, r0, #0x1
str r0, [r7]
; enable MMU and cache
ldr r0,=TblBase ; Load MMU translation table base
@ -312,24 +283,56 @@ mmu_loop
dsb ; dsb allow the MMU to start up
isb ; isb flush prefetch buffer
;set scu enable bit in scu
ldr r7, =0xf8f00000
ldr r0, [r7]
orr r0, r0, #0x1
str r0, [r7]
;invalidate scu
ldr r7, =0xf8f0000c
ldr r6, =0xffff
str r6, [r7]
; Write to ACTLR
mrc p15, 0,r0, c1, c0, 1 ; Read ACTLR
orr r0, r0, #(0x01 << 6) ; SMP bit
orr r0, r0, #(0x01 ) ; Cache/TLB maintenance broadcast
mcr p15, 0,r0, c1, c0, 1 ; Write ACTLR
; Invalidate L2 Cache and initialize L2 Cache
; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux)
#if USE_AMP!=1
ldr r0,=L2CCCrtl ; Load L2CC base address base + control register
mov r1, #0 ; force the disable bit
str r1, [r0] ; disable the L2 Caches
ldr r0,=L2CCAuxCrtl ; Load L2CC base address base + Aux control register
ldr r1,[r0] ; read the register
ldr r2,=L2CCAuxControl ; set the default bits
orr r1,r1,r2
str r1, [r0] ; store the Aux Control Register
ldr r0,=L2CCTAGLatReg ; Load L2CC base address base + TAG Latency address
ldr r1,=L2CCTAGLatency ; set the latencies for the TAG
str r1, [r0] ; store the TAG Latency register Register
ldr r0,=L2CCDataLatReg ; Load L2CC base address base + Data Latency address
ldr r1,=L2CCDataLatency ; set the latencies for the Data
str r1, [r0] ; store the Data Latency register Register
ldr r0,=L2CCWay ; Load L2CC base address base + way register
ldr r2, =0xFFFF
str r2, [r0] ; force invalidate
ldr r0,=L2CCSync ; need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET
; Load L2CC base address base + sync register
; poll for completion
Sync
ldr r1, [r0]
cmp r1, #0
bne Sync
ldr r0,=L2CCIntRaw ; clear pending interrupts
ldr r1,[r0]
ldr r0,=L2CCIntClear
str r1,[r0]
ldr r0,=SLCRUnlockReg ; Load SLCR base address base + unlock register
ldr r1,=SLCRUnlockKey ; set unlock key
str r1, [r0] ; Unlock SLCR
ldr r0,=SLCRL2cRamReg ; Load SLCR base address base + l2c Ram Control register ldr r1,=SLCRL2cRamConfig ; set the configuration value */
ldr r0,=SLCRL2cRamReg ; Load SLCR base address base + l2c Ram Control register
ldr r1,=SLCRL2cRamConfig ; set the configuration value
str r1, [r0] ; store the L2c Ram Control Register
ldr r0,=SLCRlockReg ; Load SLCR base address base + lock register