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OSD: Modified source files of osd_v4_0.

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Modified condition of error interrupt, asserts and backward compatability.

Signed-off-by: Durga challa <vnsldurg@xilinx.com>
This commit is contained in:
Durga challa 2014-09-02 11:29:15 +05:30 • committed by Suneel Garapati
parent 16649d5149
commit f026500324
4 changed files with 186 additions and 187 deletions
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295
XilinxProcessorIPLib/drivers/osd/src/xosd.c
View file

@ -139,15 +139,16 @@ static void StubErrCallBack(void *CallBackRef, u32 ErrorMask);
*
******************************************************************************/
int XOsd_CfgInitialize(XOsd *InstancePtr, XOsd_Config *CfgPtr,
u32 EffectiveAddr)
{
/* Verify arguments. */
Xil_AssertNonvoid(CfgPtr != NULL);
Xil_AssertNonvoid(CfgPtr->LayerNum <= (XOSD_MAX_NUM_OF_LAYERS));
Xil_AssertNonvoid(EffectiveAddr != (u32)0x0U);
/* Setup the instance */
(void)memset((void *)InstancePtr, 0, sizeof(XOsd));
u32 EffectiveAddr)
{
/* Verify arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(CfgPtr != NULL);
Xil_AssertNonvoid(CfgPtr->LayerNum <= (XOSD_MAX_NUM_OF_LAYERS));
Xil_AssertNonvoid(EffectiveAddr != (u32)0x00);
/* Setup the instance */
(void)memset((void *)InstancePtr, 0, sizeof(XOsd));
(void)memcpy((void *)&(InstancePtr->Config), (const void *)CfgPtr,
sizeof(XOsd_Config));
InstancePtr->Config.BaseAddress = EffectiveAddr;
@ -197,14 +198,14 @@ void XOsd_SetActiveSize(XOsd *InstancePtr, u32 Width, u32 Height)
{
u32 RegValue;
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
Xil_AssertVoid(Width > (u32)0x0U);
Xil_AssertVoid(Height > (u32)0x0U);
Xil_AssertVoid(Width <= (u32)(XOSD_ACTSIZE_NUM_PIXEL_MASK));
Xil_AssertVoid(Height <= ((XOSD_ACTSIZE_NUM_LINE_MASK) >>
(XOSD_ACTSIZE_NUM_LINE_SHIFT)));
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
Xil_AssertVoid(Width > (u32)0x0);
Xil_AssertVoid(Height > (u32)0x0);
Xil_AssertVoid(Width <= (u32)(XOSD_ACTSIZE_NUM_PIXEL_MASK));
Xil_AssertVoid(Height <= ((XOSD_ACTSIZE_NUM_LINE_MASK) >>
(XOSD_ACTSIZE_NUM_LINE_SHIFT)));
/* Save the dimension info in the driver instance for error handling */
InstancePtr->ScreenWidth = Width;
@ -357,14 +358,14 @@ void XOsd_SetLayerDimension(XOsd *InstancePtr, u8 LayerIndex, u16 XStart,
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
Xil_AssertVoid((u16)LayerIndex < InstancePtr->Config.LayerNum);
Xil_AssertVoid(InstancePtr->Layers[LayerIndex].LayerType !=
(XOSD_LAYER_TYPE_DISABLE));
Xil_AssertVoid(XSize > (u16)0x0U);
Xil_AssertVoid(YSize > (u16)0x0U);
Xil_AssertVoid(((u32)XStart + (u32)XSize) <= InstancePtr->ScreenWidth);
Xil_AssertVoid(((u32)YStart + (u32)YSize) <=
InstancePtr->ScreenHeight);
Xil_AssertVoid((u16)LayerIndex < InstancePtr->Config.LayerNum);
Xil_AssertVoid(InstancePtr->Layers[LayerIndex].LayerType !=
(XOSD_LAYER_TYPE_DISABLE));
Xil_AssertVoid(XSize > (u16)0x0);
Xil_AssertVoid(YSize > (u16)0x0);
Xil_AssertVoid(((u32)XStart + (u32)XSize) <= InstancePtr->ScreenWidth);
Xil_AssertVoid(((u32)YStart + (u32)YSize) <=
InstancePtr->ScreenHeight);
/* Calculate the base register address of the layer to work on */
LayerBaseRegAddr = (u32)(XOSD_L0C_OFFSET) + (((u32)LayerIndex) *
@ -430,14 +431,14 @@ void XOsd_GetLayerDimension(XOsd *InstancePtr, u8 LayerIndex, u16 *XStartPtr,
((u32)XOSD_LAYER_SIZE));
/* Get the origin of the layer */
RegValue = XOsd_ReadReg(InstancePtr->Config.BaseAddress,
((LayerBaseRegAddr) + (XOSD_LXP)));
*XStartPtr = (u16)((RegValue) & (XOSD_LXP_XSTART_MASK));
*YStartPtr = (u16)((RegValue) & (XOSD_LXP_YSTART_MASK)) >>
(XOSD_LXP_YSTART_SHIFT);
/* Get the size of the layer */
RegValue = XOsd_ReadReg(InstancePtr->Config.BaseAddress,
RegValue = XOsd_ReadReg(InstancePtr->Config.BaseAddress,
((LayerBaseRegAddr) + (XOSD_LXP)));
*XStartPtr = (u16)((RegValue) & (XOSD_LXP_XSTART_MASK));
*YStartPtr = (u16)(((RegValue) & (XOSD_LXP_YSTART_MASK)) >>
(XOSD_LXP_YSTART_SHIFT));
/* Get the size of the layer */
RegValue = XOsd_ReadReg(InstancePtr->Config.BaseAddress,
LayerBaseRegAddr + (XOSD_LXS));
*XSizePtr = (u16)((RegValue) & (XOSD_LXS_XSIZE_MASK));
*YSizePtr = (u16)(((RegValue) & (XOSD_LXS_YSIZE_MASK)) >>
@ -485,13 +486,13 @@ void XOsd_SetLayerAlpha(XOsd *InstancePtr, u8 LayerIndex,
/* Read the current Layer Control register value */
RegValue = XOsd_ReadReg(InstancePtr->Config.BaseAddress,
((LayerBaseRegAddr) + (XOSD_LXC)));
/* Update the global alpha enable and the global alpha value fields */
if (GlobalAlphaEnable != (u16)0x0U) {
RegValue |= ((u32)(XOSD_LXC_GALPHAEN_MASK));
}
else {
((LayerBaseRegAddr) + (XOSD_LXC)));
/* Update the global alpha enable and the global alpha value fields */
if (GlobalAlphaEnable != (u16)0x0) {
RegValue |= ((u32)(XOSD_LXC_GALPHAEN_MASK));
}
else {
RegValue &= (u32)(~(XOSD_LXC_GALPHAEN_MASK));
}
RegValue &= (u32)(~(XOSD_LXC_ALPHA_MASK));
@ -548,13 +549,13 @@ void XOsd_GetLayerAlpha(XOsd *InstancePtr, u8 LayerIndex,
/* Get the info of the global alpha enable and the global alpha value
* fields
*/
*GlobalAlphaEnablePtr = (u16)((((RegValue) &
((u32)(XOSD_LXC_GALPHAEN_MASK))) ==
(XOSD_LXC_GALPHAEN_MASK)) ? 1U : 0U);
*GlobalAlphaValuePtr = (u16)(((RegValue) & (XOSD_LXC_ALPHA_MASK)) >>
(XOSD_LXC_ALPHA_SHIFT));
}
*/
*GlobalAlphaEnablePtr = (u16)((((RegValue) &
((u32)(XOSD_LXC_GALPHAEN_MASK))) ==
(XOSD_LXC_GALPHAEN_MASK)) ? 1 : 0);
*GlobalAlphaValuePtr = (u16)(((RegValue) & (XOSD_LXC_ALPHA_MASK)) >>
(XOSD_LXC_ALPHA_SHIFT));
}
/*****************************************************************************/
/**
@ -717,13 +718,13 @@ void XOsd_DisableLayer(XOsd *InstancePtr, u8 LayerIndex)
Xil_AssertVoid((u16)LayerIndex < InstancePtr->Config.LayerNum);
Xil_AssertVoid(InstancePtr->Layers[LayerIndex].LayerType !=
(XOSD_LAYER_TYPE_DISABLE));
/* Calculate the base register address of the layer to work on */
LayerBaseRegAddr = ((u32)(XOSD_L0C_OFFSET)) +
((((u32)LayerIndex) * ((u32)(XOSD_LAYER_SIZE))));
/* Read the current layer control register value */
RegValue = XOsd_ReadReg(InstancePtr->Config.BaseAddress,
/* Calculate the base register address of the layer to work on */
LayerBaseRegAddr = ((u32)(XOSD_L0C_OFFSET)) +
((((u32)LayerIndex) * ((u32)(XOSD_LAYER_SIZE))));
/* Read the current layer control register value */
RegValue = XOsd_ReadReg(InstancePtr->Config.BaseAddress,
((LayerBaseRegAddr) + (XOSD_LXC)));
/* Clear the layer enable field */
@ -774,36 +775,35 @@ void XOsd_LoadColorLUTBank(XOsd *InstancePtr, u8 GcIndex, u8 BankIndex,
& (XOSD_GCWBA_GCNUM_MASK);
XOsd_WriteReg(InstancePtr->Config.BaseAddress, (XOSD_GCWBA_OFFSET),
RegValue);
/* Load color data */
if(InstancePtr->Config.SlaveAxisVideoDataWidth == (u16)(XOSD_DATA_8)) {
for(Index = 0x0U;
Index < ((InstancePtr->Layers[GcIndex].ColorLutSize *
(XOSD_COLOR_ENTRY_SIZE)) / sizeof(u32));
Index++) {
/* Load color data */
if(InstancePtr->Config.SlaveAxisVideoDataWidth == (u16)(XOSD_DATA_8)) {
for(Index = 0x0;
Index < ((InstancePtr->Layers[GcIndex].ColorLutSize *
(XOSD_COLOR_ENTRY_SIZE)) / sizeof(u32));
Index++) {
XOsd_WriteReg(InstancePtr->Config.BaseAddress,
(XOSD_GCD_OFFSET), ColorData[Index]);
}
}
/* For video channel size of 10 or 12, the color size is 64 bits */
else {
for (Index = 0U;
Index < (((InstancePtr->Layers[GcIndex].ColorLutSize) *
((XOSD_DATA_2) * (XOSD_COLOR_ENTRY_SIZE))) /
(sizeof(u32)));
}
/* For video channel size of 10 or 12, the color size is 64 bits */
else {
for (Index = 0;
Index < (((InstancePtr->Layers[GcIndex].ColorLutSize) *
((XOSD_DATA_2) * (XOSD_COLOR_ENTRY_SIZE))) /
(sizeof(u32)));
Index++) {
XOsd_WriteReg(InstancePtr->Config.BaseAddress,
(XOSD_GCD_OFFSET), ColorData[Index]);
}
}
/* Set the active color LUT bank */
RegValue = XOsd_ReadReg(InstancePtr->Config.BaseAddress,
(XOSD_GCABA_OFFSET));
RegValue &= ((u32)(~1U) << (((u32)(XOSD_GCABA_COL_SHIFT)) +
((u32)GcIndex)));
RegValue |= ((u32)BankIndex) << ((XOSD_GCABA_COL_SHIFT) +
((u32)GcIndex));
/* Set the active color LUT bank */
RegValue = XOsd_ReadReg(InstancePtr->Config.BaseAddress,
(XOSD_GCABA_OFFSET));
RegValue &= ~((u32)1 << ((XOSD_GCABA_COL_SHIFT) + GcIndex));
RegValue |= ((u32)BankIndex) << ((XOSD_GCABA_COL_SHIFT) +
((u32)GcIndex));
XOsd_WriteReg(InstancePtr->Config.BaseAddress, (XOSD_GCABA_OFFSET),
RegValue);
}
@ -858,22 +858,21 @@ void XOsd_LoadCharacterSetBank(XOsd *InstancePtr, u8 GcIndex, u8 BankIndex,
(u32)(InstancePtr->Layers[GcIndex].FontBitsPerPixel));
FontWriteNum /= (u32)(XOSD_FONT_BIT_TO_BYTE);
FontWriteNum *= (u32)(InstancePtr->Layers[GcIndex].FontNumChars);
FontWriteNum /= (u32)sizeof(u32);
FontWriteNum /= (u32)sizeof(u32);
/* Load the font data */
for (Index = 0x0; Index < FontWriteNum; Index++) {
XOsd_WriteReg(InstancePtr->Config.BaseAddress, (XOSD_GCD_OFFSET),
CharSetData[Index]);
}
/* Load the font data */
for (Index = 0x0U; Index < FontWriteNum; Index++) {
XOsd_WriteReg(InstancePtr->Config.BaseAddress, (XOSD_GCD_OFFSET),
CharSetData[Index]);
}
/* Set the bank to be active so the font is used by the core */
RegValue = XOsd_ReadReg(InstancePtr->Config.BaseAddress,
(XOSD_GCABA_OFFSET));
RegValue &= (u32)((~((u32)1U << (XOSD_GCABA_CHR_SHIFT)) +
((u32)GcIndex)));
RegValue |= ((u32)BankIndex) << ((XOSD_GCABA_CHR_SHIFT) +
((u32)GcIndex));
XOsd_WriteReg(InstancePtr->Config.BaseAddress, (XOSD_GCABA_OFFSET),
/* Set the bank to be active so the font is used by the core */
RegValue = XOsd_ReadReg(InstancePtr->Config.BaseAddress,
(XOSD_GCABA_OFFSET));
RegValue &= ~((u32)1 << ((XOSD_GCABA_CHR_SHIFT) + GcIndex));
RegValue |= ((u32)BankIndex) << ((XOSD_GCABA_CHR_SHIFT) +
((u32)GcIndex));
XOsd_WriteReg(InstancePtr->Config.BaseAddress, (XOSD_GCABA_OFFSET),
RegValue);
}
@ -918,26 +917,26 @@ void XOsd_LoadTextBank(XOsd *InstancePtr, u8 GcIndex, u8 BankIndex,
RegValue |= (((u32)GcIndex) << (XOSD_GCWBA_GCNUM_SHIFT)) &
(XOSD_GCWBA_GCNUM_MASK);
XOsd_WriteReg(InstancePtr->Config.BaseAddress, (XOSD_GCWBA_OFFSET),
RegValue);
/* Load text data */
for (Index = 0x0U;
Index < (u32)((((u32)(InstancePtr->
Layers[GcIndex].TextNumStrings) *
(u32)(InstancePtr->Layers[GcIndex].TextMaxStringLength)) /
RegValue);
/* Load text data */
for (Index = 0x0;
Index < (u32)((((u32)(InstancePtr->
Layers[GcIndex].TextNumStrings) *
(u32)(InstancePtr->Layers[GcIndex].TextMaxStringLength)) /
sizeof(u32)));
Index++) {
XOsd_WriteReg(InstancePtr->Config.BaseAddress,
(XOSD_GCD_OFFSET), TextData[Index]);
}
/* Set the active text bank */
RegValue = XOsd_ReadReg(InstancePtr->Config.BaseAddress,
(XOSD_GCABA_OFFSET));
RegValue &= ~(1U << ((XOSD_GCABA_TXT_SHIFT) + GcIndex));
RegValue |= ((u32)BankIndex) << ((XOSD_GCABA_TXT_SHIFT) +
((u32)GcIndex));
/* Set the active text bank */
RegValue = XOsd_ReadReg(InstancePtr->Config.BaseAddress,
(XOSD_GCABA_OFFSET));
RegValue &= ~(1 << ((XOSD_GCABA_TXT_SHIFT) + GcIndex));
RegValue |= ((u32)BankIndex) << ((XOSD_GCABA_TXT_SHIFT) +
((u32)GcIndex));
XOsd_WriteReg(InstancePtr->Config.BaseAddress, (XOSD_GCABA_OFFSET),
RegValue);
}
@ -982,18 +981,18 @@ void XOsd_SetActiveBank(XOsd *InstancePtr, u8 GcIndex, u8 ColorBankIndex,
Xil_AssertVoid(TextBankIndex < (XOSD_GC_BANK_NUM));
Xil_AssertVoid(InstructionBankIndex < (XOSD_GC_BANK_NUM));
/* Clear the current active bank setting first */
RegValue = XOsd_ReadReg(InstancePtr->Config.BaseAddress,
(XOSD_GCABA_OFFSET));
RegValue &= ~(1U << GcIndex) & (XOSD_GCABA_INS_MASK);
RegValue &= ~(1U << ((XOSD_GCABA_COL_SHIFT) + (GcIndex))) &
(XOSD_GCABA_COL_MASK);
RegValue &= ~(1U << ((XOSD_GCABA_TXT_SHIFT) + (GcIndex))) &
(XOSD_GCABA_TXT_MASK);
RegValue &= ~(1U << ((XOSD_GCABA_CHR_SHIFT) + (GcIndex))) &
(XOSD_GCABA_CHR_MASK);
/* Choose the active banks */
/* Clear the current active bank setting first */
RegValue = XOsd_ReadReg(InstancePtr->Config.BaseAddress,
(XOSD_GCABA_OFFSET));
RegValue &= ~(1 << GcIndex) & (XOSD_GCABA_INS_MASK);
RegValue &= ~(1 << ((XOSD_GCABA_COL_SHIFT) + (GcIndex))) &
(XOSD_GCABA_COL_MASK);
RegValue &= ~(1 << ((XOSD_GCABA_TXT_SHIFT) + (GcIndex))) &
(XOSD_GCABA_TXT_MASK);
RegValue &= ~(1 << ((XOSD_GCABA_CHR_SHIFT) + (GcIndex))) &
(XOSD_GCABA_CHR_MASK);
/* Choose the active banks */
RegValue |= (((u32)InstructionBankIndex) << ((u32)GcIndex)) &
(XOSD_GCABA_INS_MASK);
RegValue |= (((u32)ColorBankIndex) << ((XOSD_GCABA_COL_SHIFT) +
@ -1138,31 +1137,31 @@ void XOsd_LoadInstructionList(XOsd *InstancePtr, u8 GcIndex, u8 BankIndex,
RegValue = (((u32)BankIndex) + (XOSD_GCWBA_INS0)) &
(XOSD_GCWBA_BANK_MASK);
RegValue |= (((u32)GcIndex) << (XOSD_GCWBA_GCNUM_SHIFT)) &
(XOSD_GCWBA_GCNUM_MASK);
XOsd_WriteReg(InstancePtr->Config.BaseAddress, (XOSD_GCWBA_OFFSET),
RegValue);
for (Index = 0U; Index < (InstNum * (XOSD_INS_SIZE)); Index++) {
XOsd_WriteReg(InstancePtr->Config.BaseAddress,
(XOSD_GCD_OFFSET), InstSetPtr[Index]);
}
(XOSD_GCWBA_GCNUM_MASK);
XOsd_WriteReg(InstancePtr->Config.BaseAddress, (XOSD_GCWBA_OFFSET),
RegValue);
for (Index = 0; Index < (InstNum * (XOSD_INS_SIZE)); Index++) {
XOsd_WriteReg(InstancePtr->Config.BaseAddress,
(XOSD_GCD_OFFSET), InstSetPtr[Index]);
}
/* Notify OSD this is the end of the instruction list by adding an END
* instruction
*/
if (InstNum < InstancePtr->Layers[GcIndex].InstructionNum) {
for (Index = 0x0U; Index < (XOSD_INS_SIZE); Index++) {
XOsd_WriteReg(InstancePtr->Config.BaseAddress,
(XOSD_GCD_OFFSET), 0x0U);
}
}
/* Set the active instruction bank */
RegValue = XOsd_ReadReg(InstancePtr->Config.BaseAddress,
(XOSD_GCABA_OFFSET));
RegValue &= ~(1U << GcIndex);
RegValue |= ((u32)BankIndex << (u32)GcIndex);
XOsd_WriteReg(InstancePtr->Config.BaseAddress,
(XOSD_GCABA_OFFSET), RegValue);
* instruction
*/
if (InstNum < InstancePtr->Layers[GcIndex].InstructionNum) {
for (Index = 0x0; Index < (XOSD_INS_SIZE); Index++) {
XOsd_WriteReg(InstancePtr->Config.BaseAddress,
(XOSD_GCD_OFFSET), 0x0);
}
}
/* Set the active instruction bank */
RegValue = XOsd_ReadReg(InstancePtr->Config.BaseAddress,
(XOSD_GCABA_OFFSET));
RegValue &= ~(1 << GcIndex);
RegValue |= ((u32)BankIndex << (u32)GcIndex);
XOsd_WriteReg(InstancePtr->Config.BaseAddress,
(XOSD_GCABA_OFFSET), RegValue);
}
/*****************************************************************************/
@ -1191,15 +1190,13 @@ static void PopulateLayerProperty(XOsd *InstancePtr, XOsd_Config *CfgPtr)
Xil_AssertVoid(CfgPtr != NULL);
/* Use short variable names to keep the lines in this function
* shorter
*/
IpTemp = InstancePtr;
Xil_AssertVoid(IpTemp != NULL);
Cfg = CfgPtr;
Xil_AssertVoid(Cfg != NULL);
/* Layer #0 */
IpTemp->Layers[0].LayerType = Cfg->Layer0Type;
* shorter
*/
IpTemp = InstancePtr;
Cfg = CfgPtr;
/* Layer #0 */
IpTemp->Layers[0].LayerType = Cfg->Layer0Type;
IpTemp->Layers[0].InstructionNum = Cfg->Layer0InstructionMemSize;
IpTemp->Layers[0].InstructionBoxEnable = Cfg->Layer0InstructionBoxEnable;
IpTemp->Layers[0].InstructionLineEnable = Cfg->Layer0InstructionLineEnable;

13
XilinxProcessorIPLib/drivers/osd/src/xosd.h
View file

@ -265,12 +265,13 @@ enum {
#define XOSD_DisableLayer XOsd_DisableLayer
#define XOSD_LoadColorLUTBank XOsd_LoadColorLUTBank
#define XOSD_LoadCharacterSetBank XOsd_LoadCharacterSetBank
#define XOSD_LoadTextBank XOsd_LoadTextBank
#define XOSD_SetActiveBank XOsd_SetActiveBank
#define XOSD_CreateInstruction XOsd_CreateInstruction
#define XOSD_LoadInstructionList XOsd_LoadInstructionList
#define XOSD_LookupConfig XOsd_LookupConfig
#define XOSD_IntrHandler XOsd_IntrHandler
#define XOSD_LoadTextBank XOsd_LoadTextBank
#define XOSD_SetActiveBank XOsd_SetActiveBank
#define XOSD_CreateInstruction XOsd_CreateInstruction
#define XOSD_GetVersion XOsd_GetVersion
#define XOSD_LoadInstructionList XOsd_LoadInstructionList
#define XOSD_LookupConfig XOsd_LookupConfig
#define XOSD_IntrHandler XOsd_IntrHandler
#define XOSD_SetCallBack XOsd_SetCallBack
/*@}*/

50
XilinxProcessorIPLib/drivers/osd/src/xosd_hw.h
View file

@ -134,14 +134,14 @@ extern "C" {
#define XOSD_RST_OFFSET XOSD_CTL_OFFSET /**< Software Reset Offset */
/**
* Interrupt status register generates a interrupt if the corresponding bits
* of interrupt enable register bits are set.
*/
#define XOSD_ISR_OFFSET XOSD_STATUS /**< Interrupt Status
* Register Offset */
#define XOSD_IER_OFFSET 0x00C /**< Interrupt Enable
* Register Offset */
* Interrupt status register generates a interrupt if the corresponding bits
* of interrupt enable register bits are set.
*/
#define XOSD_ISR_OFFSET XOSD_STATUS_OFFSET/**< Interrupt Status
* Register Offset */
#define XOSD_IER_OFFSET 0x00C /**< Interrupt Enable
* Register Offset */
#define XOSD_STATUS_OFFSET 0x004 /**< Status Offset */
#define XOSD_ERROR_OFFSET 0x008 /**< Error Offset */
@ -598,16 +598,14 @@ extern "C" {
/*@}*/
/** @name Compatibility Macros
* @{
*/
#define XOSD_CTL XOSD_CTL_OFFSET
#define XOSD_STATUS XOSD_STATUS_OFFSET
#define XOSD_ERROR XOSD_ERROR_OFFSET
#define XOSD_VER XOSD_VER_OFFSET
#define XOSD_SS XOSD_ACTIVE_SIZE_OFFSET
#define XOSD_OPENC XOSD_OPENC_OFFSET
#define XOSD_BC0 XOSD_BC0_OFFSET
#define XOSD_BC1 XOSD_BC1_OFFSET
* @{
*/
#define XOSD_CTL XOSD_CTL_OFFSET
#define XOSD_SS XOSD_ACTIVE_SIZE_OFFSET
#define XOSD_VER XOSD_VER_OFFSET
#define XOSD_OPENC XOSD_OPENC_OFFSET
#define XOSD_BC0 XOSD_BC0_OFFSET
#define XOSD_BC1 XOSD_BC1_OFFSET
#define XOSD_BC2 XOSD_BC2_OFFSET
#define XOSD_L0C XOSD_L0C_OFFSET
@ -648,12 +646,16 @@ extern "C" {
#define XOSD_RST XOSD_RST_OFFSET
#define XOSD_ISR XOSD_ISR_OFFSET
#define XOSD_IER XOSD_IER_OFFSET
#define XOSD_In32 XOsd_In32
#define XOSD_Out32 XOsd_Out32
#define XOSD_ISR XOSD_ISR_OFFSET
#define XOSD_IER XOSD_IER_OFFSET
#define XOSD_SS_YSIZE_MASK XOSD_ACTSIZE_NUM_LINE_MASK
#define XOSD_SS_XSIZE_MASK XOSD_ACTSIZE_NUM_PIXEL_MASK
#define XOSD_SS_YSIZE_SHIFT XOSD_ACTSIZE_NUM_LINE_SHIFT
#define XOSD_In32 XOsd_In32
#define XOSD_Out32 XOsd_Out32
#define XOSD_ReadReg XOsd_ReadReg
#define XOSD_WriteReg XOsd_WriteReg
/*@}*/

15
XilinxProcessorIPLib/drivers/osd/src/xosd_intr.c
View file

@ -110,14 +110,13 @@ void XOsd_IntrHandler(void *InstancePtr)
Xil_AssertVoid(XOsdPtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
/* Get pending interrupts. */
PendingIntr = (u32)(XOsd_IntrGetPending(XOsdPtr));
/* Error interrupt is occurring or spurious interrupt. */
if (((PendingIntr) & (XOSD_IXR_ALLERR_MASK)) ==
((XOSD_IXR_ALLERR_MASK))) {
ErrorStatus = (PendingIntr) & (XOSD_IXR_ALLERR_MASK);
XOsdPtr->ErrCallBack(XOsdPtr->ErrRef, ErrorStatus);
}
PendingIntr = (u32)(XOsd_IntrGetPending(XOsdPtr));
/* Error interrupt is occurring or spurious interrupt. */
if (((PendingIntr) & (XOSD_IXR_ALLERR_MASK)) != (u32)0x00) {
ErrorStatus = (PendingIntr) & (XOSD_IXR_ALLERR_MASK);
XOsdPtr->ErrCallBack(XOsdPtr->ErrRef, ErrorStatus);
}
/* A Processing start interrupt has occurred. */
if (((PendingIntr) & (XOSD_IXR_PROC_STARTED_MASK)) ==