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axicdma: Mark only BD Memory region as uncacheable

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This patch updates the Xil_SetTlbAttributes
to mark the BD memory region only uncaheable and
updated the cache flush/invalidate api's for a53 case.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by:  Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
This commit is contained in:
Kedareswara rao Appana 2015-08-21 17:01:14 +05:30 • committed by Nava kishore Manne
parent b38a8677a2
commit f2fc9f0ca9
2 changed files with 26 additions and 2 deletions
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20
XilinxProcessorIPLib/drivers/axicdma/examples/xaxicdma_example_sg_intr.c
View file

@ -79,9 +79,16 @@
#ifndef __MICROBLAZE__
#include "xpseudo_asm_gcc.h"
#endif
#ifdef __arm__
#include "xreg_cortexa9.h"
#endif
#ifdef __aarch64__
#include "xreg_cortexa53.h"
#endif
#ifdef XPAR_UARTNS550_0_BASEADDR
#include "xuartns550_l.h" /* to use uartns550 */
#endif
@ -129,6 +136,7 @@ extern void xil_printf(const char *format, ...);
#define MAX_PKT_LEN 1024
#define MARK_UNCACHEABLE 0x701
/* Number of BDs in the transfer example
* We show how to submit multiple BDs for one transmit.
@ -609,6 +617,10 @@ static int SetupTransfer(XAxiCdma * InstancePtr)
*/
Xil_DCacheFlushRange((u32)TransmitBufferPtr,
MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER);
#ifdef __aarch64__
Xil_DCacheFlushRange((UINTPTR)ReceiveBufferPtr,
MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER);
#endif
Status = XAxiCdma_SetCoalesce(InstancePtr, COALESCING_COUNT,
DELAY_COUNT);
@ -734,7 +746,9 @@ static int CheckData(u8 *SrcPtr, u8 *DestPtr, int Length)
/* Invalidate the DestBuffer before receiving the data, in case the
* Data Cache is enabled
*/
Xil_DCacheInvalidateRange((u32)DestPtr, Length);
#ifndef __aarch64__
Xil_DCacheInvalidateRange((UINTPTR)DestPtr, Length);
#endif
for (Index = 0; Index < Length; Index++) {
if ( DestPtr[Index] != SrcPtr[Index]) {
@ -784,6 +798,10 @@ int XAxiCdma_SgIntrExample(XScuGic *IntcInstancePtr, XAxiCdma *InstancePtr,
SrcPtr = (u8 *)TransmitBufferPtr;
DstPtr = (u8 *)ReceiveBufferPtr;
#ifdef __aarch64__
Xil_SetTlbAttributes(BD_SPACE_BASE, MARK_UNCACHEABLE);
#endif
/* Initialize the XAxiCdma device.
*/
CfgPtr = XAxiCdma_LookupConfig(DeviceId);

8
XilinxProcessorIPLib/drivers/axicdma/examples/xaxicdma_example_sg_poll.c
View file

@ -361,6 +361,10 @@ static int SetupTransfer(XAxiCdma * InstancePtr)
*/
Xil_DCacheFlushRange((UINTPTR)TransmitBufferPtr,
MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER);
#ifdef __aarch64__
Xil_DCacheFlushRange((UINTPTR)ReceiveBufferPtr,
MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER);
#endif
return XST_SUCCESS;
}
@ -471,7 +475,9 @@ static int CheckData(u8 *SrcPtr, u8 *DestPtr, int Length)
/* Invalidate the DestBuffer before receiving the data, in case the
* Data Cache is enabled
*/
#ifndef __aarch64__
Xil_DCacheInvalidateRange((UINTPTR)DestPtr, Length);
#endif
for (Index = 0; Index < Length; Index++) {
if ( DestPtr[Index] != SrcPtr[Index]) {
@ -510,7 +516,7 @@ int XAxiCdma_SgPollExample(u16 DeviceId)
DstPtr = (u8 *)ReceiveBufferPtr;
#ifdef __aarch64__
Xil_SetTlbAttributes(MEMORY_BASE, MARK_UNCACHEABLE);
Xil_SetTlbAttributes(BD_SPACE_BASE, MARK_UNCACHEABLE);
#endif
/* Initialize the XAxiCdma device.