dp: XDptx_Config->XDp_Config

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>

XilinxProcessorIPLib/drivers/dp/src/xdp.h

@@ -206,13 +206,54 @@
 /******************************* Include Files ********************************/
 
 #include "xdptx.h"
+#include "xil_types.h"
 
 /****************************** Type Definitions ******************************/
 
+/**
+ * This typedef contains configuration information for the DisplayPort TX core.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Device instance ID. */
+	u32 BaseAddr;		/**< The base address of the core instance. */
+	u32 SAxiClkHz;		/**< The clock frequency of the core instance's
+					S_AXI_ACLK port. */
+	u8 MaxLaneCount;	/**< The maximum lane count supported by this
+					core instance. */
+	u8 MaxLinkRate;		/**< The maximum link rate supported by this
+					core instance. */
+	u8 MaxBitsPerColor;	/**< The maximum bits/color supported by this
+					core instance*/
+	u8 QuadPixelEn;		/**< Quad pixel support by this core
+					instance. */
+	u8 DualPixelEn;		/**< Dual pixel support by this core
+					instance. */
+	u8 YCrCbEn;		/**< YCrCb format support by this core
+					instance. */
+	u8 YOnlyEn;		/**< YOnly format support by this core
+					instance. */
+	u8 PayloadDataWidth;	/**< The payload data width used by this core
+					instance. */
+	u8 SecondaryChEn;	/**< This core instance supports audio packets
+					being sent by the secondary channel. */
+	u8 NumAudioChs;		/**< The number of audio channels supported by
+					this core instance. */
+	u8 MstSupport;		/**< Multi-stream transport (MST) mode is
+					enabled by this core instance. */
+	u8 NumMstStreams;	/**< The total number of MST streams supported
+					by this core instance. */
+	u8 DpProtocol;		/**< The DisplayPort protocol version that this
+					core instance is configured for.
+					0 = v1.1a, 1 = v1.2. */
+} XDp_Config;
+
+/* Backwards compatible with dptx. */
+#define XDptx_Config XDp_Config
+
 /**************************** Function Prototypes *****************************/
 
 /* xdp_sinit.c: Configuration extraction function.*/
-XDptx_Config *XDp_LookupConfig(u16 DeviceId);
+XDp_Config *XDp_LookupConfig(u16 DeviceId);
 
 /* Backwards compatible with dptx. */
 #define XDptx_LookupConfig XDp_LookupConfig

XilinxProcessorIPLib/drivers/dp/src/xdp_sinit.c

@@ -59,7 +59,7 @@
  * A table of configuration structures containing the configuration information
  * for each DisplayPort TX core in the system.
  */
-extern XDptx_Config XDptx_ConfigTable[XPAR_XDPTX_NUM_INSTANCES];
+extern XDp_Config XDptx_ConfigTable[XPAR_XDPTX_NUM_INSTANCES];
 
 /**************************** Function Definitions ****************************/
 
@@ -77,9 +77,9 @@ extern XDptx_Config XDptx_ConfigTable[XPAR_XDPTX_NUM_INSTANCES];
  * @note	None.
  *
 *******************************************************************************/
-XDptx_Config *XDp_LookupConfig(u16 DeviceId)
+XDp_Config *XDp_LookupConfig(u16 DeviceId)
 {
-	XDptx_Config *CfgPtr;
+	XDp_Config *CfgPtr;
 	u32 Index;
 
 	for (Index = 0; Index < XPAR_XDPTX_NUM_INSTANCES; Index++) {

XilinxProcessorIPLib/drivers/dp/src/xdptx.c

@@ -163,7 +163,7 @@ u32 XDptx_InitializeTx(XDptx *InstancePtr)
 {
 	u32 Status;
 	u32 RegVal;
-	XDptx_Config *Config = &InstancePtr->Config;
+	XDp_Config *Config = &InstancePtr->Config;
 
 	/* Verify arguments. */
 	Xil_AssertNonvoid(InstancePtr != NULL);
@@ -245,7 +245,7 @@ u32 XDptx_InitializeTx(XDptx *InstancePtr)
  *		after this function is invoked.
  *
 *******************************************************************************/
-void XDptx_CfgInitialize(XDptx *InstancePtr, XDptx_Config *ConfigPtr,
+void XDptx_CfgInitialize(XDptx *InstancePtr, XDp_Config *ConfigPtr,
 							u32 EffectiveAddr)
 {
 	/* Verify arguments. */
@@ -313,7 +313,7 @@ u32 XDptx_GetRxCapabilities(XDptx *InstancePtr)
 	u32 Status;
 	u8 *Dpcd = InstancePtr->RxConfig.DpcdRxCapsField;
 	XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
-	XDptx_Config *Config = &InstancePtr->Config;
+	XDp_Config *Config = &InstancePtr->Config;
 	u8 RxMaxLinkRate;
 	u8 RxMaxLaneCount;
 

XilinxProcessorIPLib/drivers/dp/src/xdptx.h

@@ -234,43 +234,6 @@
 
 /****************************** Type Definitions ******************************/
 
-/**
- * This typedef contains configuration information for the DisplayPort TX core.
- */
-typedef struct {
-	u16 DeviceId;		/**< Device instance ID. */
-	u32 BaseAddr;		/**< The base address of the core instance. */
-	u32 SAxiClkHz;		/**< The clock frequency of the core instance's
-					S_AXI_ACLK port. */
-	u8 MaxLaneCount;	/**< The maximum lane count supported by this
-					core instance. */
-	u8 MaxLinkRate;		/**< The maximum link rate supported by this
-					core instance. */
-	u8 MaxBitsPerColor;	/**< The maximum bits/color supported by this
-					core instance*/
-	u8 QuadPixelEn;		/**< Quad pixel support by this core
-					instance. */
-	u8 DualPixelEn;		/**< Dual pixel support by this core
-					instance. */
-	u8 YCrCbEn;		/**< YCrCb format support by this core
-					instance. */
-	u8 YOnlyEn;		/**< YOnly format support by this core
-					instance. */
-	u8 PayloadDataWidth;	/**< The payload data width used by this core
-					instance. */
-	u8 SecondaryChEn;	/**< This core instance supports audio packets
-					being sent by the secondary channel. */
-	u8 NumAudioChs;		/**< The number of audio channels supported by
-					this core instance. */
-	u8 MstSupport;		/**< Multi-stream transport (MST) mode is
-					enabled by this core instance. */
-	u8 NumMstStreams;	/**< The total number of MST streams supported
-					by this core instance. */
-	u8 DpProtocol;		/**< The DisplayPort protocol version that this
-					core instance is configured for.
-					0 = v1.1a, 1 = v1.2. */
-} XDptx_Config;
-
 /**
  * This typedef contains configuration information about the RX device.
  */
@@ -565,7 +528,7 @@ typedef struct {
 	u8 TrainAdaptive;			/**< Downshift lane count and
 							link rate if necessary
 							during training. */
-	XDptx_Config Config;			/**< Configuration structure for
+	XDp_Config Config;			/**< Configuration structure for
 							the DisplayPort TX
 							core. */
 	XDptx_SinkConfig RxConfig;		/**< Configuration structure for
@@ -622,7 +585,7 @@ typedef struct {
 
 /* xdptx.c: Setup and initialization functions. */
 u32 XDptx_InitializeTx(XDptx *InstancePtr);
-void XDptx_CfgInitialize(XDptx *InstancePtr, XDptx_Config *ConfigPtr,
+void XDptx_CfgInitialize(XDptx *InstancePtr, XDp_Config *ConfigPtr,
 							u32 EffectiveAddr);
 u32 XDptx_GetRxCapabilities(XDptx *InstancePtr);
 

XilinxProcessorIPLib/drivers/dp/src/xdptx_spm.c

@@ -622,7 +622,7 @@ void XDptx_SetVideoMode(XDptx *InstancePtr, u8 Stream)
 *******************************************************************************/
 void XDptx_ClearMsaValues(XDptx *InstancePtr, u8 Stream)
 {
-	XDptx_Config *Config;
+	XDp_Config *Config;
 	u32 StreamOffset[4] = {0, XDPTX_STREAM2_MSA_START_OFFSET,
 		XDPTX_STREAM3_MSA_START_OFFSET, XDPTX_STREAM4_MSA_START_OFFSET};
 
@@ -693,7 +693,7 @@ void XDptx_ClearMsaValues(XDptx *InstancePtr, u8 Stream)
 *******************************************************************************/
 void XDptx_SetMsaValues(XDptx *InstancePtr, u8 Stream)
 {
-	XDptx_Config *Config;
+	XDp_Config *Config;
 	XDptx_MainStreamAttributes *MsaConfig;
 	u32 StreamOffset[4] = {0, XDPTX_STREAM2_MSA_START_OFFSET,
 		XDPTX_STREAM3_MSA_START_OFFSET, XDPTX_STREAM4_MSA_START_OFFSET};