Integrated fsbl related changes
Wall Data: Originally submitted from RDI_devivar_sdk_nov15 Build Type: full Test Types: pre-commits, gui pre-commits [git-p4: depot-paths = "//Rodin/HEAD/data/embeddedsw/": change = 974578]
This commit is contained in:
Devi Vara Prasad Bandaru
Jagannadha Sutradharudu Teki
parent
3a1dd6502d
commit
f69fb10301
11 changed files with 19755 additions and 8796 deletions
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@ -1,41 +1,28 @@
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/******************************************************************************
|
||||
*
|
||||
* (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
|
||||
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of this
|
||||
* software and associated documentation files (the "Software"), to deal in the Software
|
||||
* without restriction, including without limitation the rights to use, copy, modify, merge,
|
||||
* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
|
||||
* persons to whom the Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
|
||||
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
|
||||
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
|
||||
* and (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage
|
||||
* of any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought by
|
||||
* a third party) even if such damage or loss was reasonably foreseeable or
|
||||
* Xilinx had been advised of the possibility of the same.
|
||||
* The above copyright notice and this permission notice shall be included in all copies or
|
||||
* substantial portions of the Software.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or
|
||||
* environmental damage (individually and collectively, "Critical
|
||||
* Applications"). Customer assumes the sole risk and liability of any use of
|
||||
* Xilinx products in Critical Applications, subject only to applicable laws
|
||||
* and regulations governing limitations on product liability.
|
||||
* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
|
||||
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or
|
||||
* otherwise to promote the sale, use or other dealings in this Software without prior written
|
||||
* authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
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/****************************************************************************/
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@ -3702,8 +3689,27 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
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// .. FINISH: LOCK IT BACK
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// .. START: SRAM/NOR SET OPMODE
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// .. FINISH: SRAM/NOR SET OPMODE
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// .. START: TRACE LOCK ACCESS REGISTER
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// .. a = 0XC5ACCE55
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// .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U
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// .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
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// ..
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EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
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// .. FINISH: TRACE LOCK ACCESS REGISTER
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// .. START: TRACE CURRENT PORT SIZE
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// .. a = 2
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// .. ==> 0XF8803004[31:0] = 0x00000002U
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// .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U
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// ..
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EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U),
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// .. FINISH: TRACE CURRENT PORT SIZE
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// .. START: TRACE LOCK ACCESS REGISTER
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// .. a = 0X0
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// .. ==> 0XF8803FB0[31:0] = 0x00000000U
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// .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
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// ..
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EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U),
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// .. FINISH: TRACE LOCK ACCESS REGISTER
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// .. START: UART REGISTERS
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// .. BDIV = 0x6
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// .. ==> 0XE0001034[7:0] = 0x00000006U
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@ -7987,8 +7993,27 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
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// .. FINISH: LOCK IT BACK
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// .. START: SRAM/NOR SET OPMODE
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// .. FINISH: SRAM/NOR SET OPMODE
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// .. START: TRACE LOCK ACCESS REGISTER
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// .. a = 0XC5ACCE55
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// .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U
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// .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
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// ..
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EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
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// .. FINISH: TRACE LOCK ACCESS REGISTER
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// .. START: TRACE CURRENT PORT SIZE
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// .. a = 2
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// .. ==> 0XF8803004[31:0] = 0x00000002U
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// .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U
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// ..
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EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U),
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// .. FINISH: TRACE CURRENT PORT SIZE
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// .. START: TRACE LOCK ACCESS REGISTER
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// .. a = 0X0
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// .. ==> 0XF8803FB0[31:0] = 0x00000000U
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// .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
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// ..
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EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U),
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// .. FINISH: TRACE LOCK ACCESS REGISTER
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// .. START: UART REGISTERS
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// .. BDIV = 0x6
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// .. ==> 0XE0001034[7:0] = 0x00000006U
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@ -12205,8 +12230,27 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
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// .. FINISH: LOCK IT BACK
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// .. START: SRAM/NOR SET OPMODE
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// .. FINISH: SRAM/NOR SET OPMODE
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// .. START: TRACE LOCK ACCESS REGISTER
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// .. a = 0XC5ACCE55
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// .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U
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// .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
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// ..
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EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
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// .. FINISH: TRACE LOCK ACCESS REGISTER
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// .. START: TRACE CURRENT PORT SIZE
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// .. a = 2
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// .. ==> 0XF8803004[31:0] = 0x00000002U
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// .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U
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// ..
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EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U),
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// .. FINISH: TRACE CURRENT PORT SIZE
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// .. START: TRACE LOCK ACCESS REGISTER
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// .. a = 0X0
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// .. ==> 0XF8803FB0[31:0] = 0x00000000U
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// .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
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// ..
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EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U),
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// .. FINISH: TRACE LOCK ACCESS REGISTER
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// .. START: UART REGISTERS
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// .. BDIV = 0x6
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// .. ==> 0XE0001034[7:0] = 0x00000006U
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@ -1,44 +1,31 @@
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/******************************************************************************
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||||
*
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||||
* (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
|
||||
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This file contains confidential and proprietary information of Xilinx, Inc.
|
||||
* and is protected under U.S. and international copyright and other
|
||||
* intellectual property laws.
|
||||
*
|
||||
* DISCLAIMER
|
||||
* This disclaimer is not a license and does not grant any rights to the
|
||||
* materials distributed herewith. Except as otherwise provided in a valid
|
||||
* license issued to you by Xilinx, and to the maximum extent permitted by
|
||||
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
|
||||
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
|
||||
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
||||
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
|
||||
* and (2) Xilinx shall not be liable (whether in contract or tort, including
|
||||
* negligence, or under any other theory of liability) for any loss or damage
|
||||
* of any kind or nature related to, arising under or in connection with these
|
||||
* materials, including for any direct, or any indirect, special, incidental,
|
||||
* or consequential loss or damage (including loss of data, profits, goodwill,
|
||||
* or any type of loss or damage suffered as a result of any action brought by
|
||||
* a third party) even if such damage or loss was reasonably foreseeable or
|
||||
* Xilinx had been advised of the possibility of the same.
|
||||
*
|
||||
* CRITICAL APPLICATIONS
|
||||
* Xilinx products are not designed or intended to be fail-safe, or for use in
|
||||
* any application requiring fail-safe performance, such as life-support or
|
||||
* safety devices or systems, Class III medical devices, nuclear facilities,
|
||||
* applications related to the deployment of airbags, or any other applications
|
||||
* that could lead to death, personal injury, or severe property or
|
||||
* environmental damage (individually and collectively, "Critical
|
||||
* Applications"). Customer assumes the sole risk and liability of any use of
|
||||
* Xilinx products in Critical Applications, subject only to applicable laws
|
||||
* and regulations governing limitations on product liability.
|
||||
*
|
||||
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
||||
* AT ALL TIMES.
|
||||
*
|
||||
******************************************************************************/
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of this
|
||||
* software and associated documentation files (the "Software"), to deal in the Software
|
||||
* without restriction, including without limitation the rights to use, copy, modify, merge,
|
||||
* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
|
||||
* persons to whom the Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all copies or
|
||||
* substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
|
||||
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or
|
||||
* otherwise to promote the sale, use or other dealings in this Software without prior written
|
||||
* authorization from Xilinx.
|
||||
*
|
||||
*******************************************************************************/
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/****************************************************************************/
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/**
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*
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|
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File diff suppressed because it is too large
Load diff
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@ -211,6 +211,9 @@ proc ps7_peripherals_init_data_3_0 {} {
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mask_write 0XF8000B50 0x00000180 0x00000180
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mask_write 0XF8000B54 0x00000180 0x00000180
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mask_write 0XF8000004 0x0000FFFF 0x0000767B
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mask_write 0XF8803FB0 0xFFFFFFFF 0xC5ACCE55
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mask_write 0XF8803004 0xFFFFFFFF 0x00000002
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mask_write 0XF8803FB0 0xFFFFFFFF 0x00000000
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mask_write 0XE0001034 0x000000FF 0x00000006
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mask_write 0XE0001018 0x0000FFFF 0x0000003E
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mask_write 0XE0001000 0x000001FF 0x00000017
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@ -461,6 +464,9 @@ proc ps7_peripherals_init_data_2_0 {} {
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mask_write 0XF8000B50 0x00000180 0x00000180
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mask_write 0XF8000B54 0x00000180 0x00000180
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mask_write 0XF8000004 0x0000FFFF 0x0000767B
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mask_write 0XF8803FB0 0xFFFFFFFF 0xC5ACCE55
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mask_write 0XF8803004 0xFFFFFFFF 0x00000002
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mask_write 0XF8803FB0 0xFFFFFFFF 0x00000000
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mask_write 0XE0001034 0x000000FF 0x00000006
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mask_write 0XE0001018 0x0000FFFF 0x0000003E
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mask_write 0XE0001000 0x000001FF 0x00000017
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@ -709,6 +715,9 @@ proc ps7_peripherals_init_data_1_0 {} {
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mask_write 0XF8000B50 0x00000180 0x00000180
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mask_write 0XF8000B54 0x00000180 0x00000180
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mask_write 0XF8000004 0x0000FFFF 0x0000767B
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mask_write 0XF8803FB0 0xFFFFFFFF 0xC5ACCE55
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mask_write 0XF8803004 0xFFFFFFFF 0x00000002
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mask_write 0XF8803FB0 0xFFFFFFFF 0x00000000
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mask_write 0XE0001034 0x000000FF 0x00000006
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mask_write 0XE0001018 0x0000FFFF 0x0000003E
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mask_write 0XE0001000 0x000001FF 0x00000017
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12991
lib/zpe_templates/ZPE_ZC_702_HwPlatform/ps7_init_gpl.c
Executable file
12991
lib/zpe_templates/ZPE_ZC_702_HwPlatform/ps7_init_gpl.c
Executable file
File diff suppressed because it is too large
Load diff
132
lib/zpe_templates/ZPE_ZC_702_HwPlatform/ps7_init_gpl.h
Executable file
132
lib/zpe_templates/ZPE_ZC_702_HwPlatform/ps7_init_gpl.h
Executable file
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@ -0,0 +1,132 @@
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/******************************************************************************
|
||||
*
|
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* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
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*
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* "#include "ps7_init_gpl.h"
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*
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*
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*******************************************************************************/
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/****************************************************************************/
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/**
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*
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* @file ps7_init.h
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*
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* This file can be included in FSBL code
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* to get prototype of ps7_init() function
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* and error codes
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*
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*****************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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//typedef unsigned int u32;
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/** do we need to make this name more unique ? **/
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//extern u32 ps7_init_data[];
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extern unsigned long * ps7_ddr_init_data;
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extern unsigned long * ps7_mio_init_data;
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extern unsigned long * ps7_pll_init_data;
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extern unsigned long * ps7_clock_init_data;
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extern unsigned long * ps7_peripherals_init_data;
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#define OPCODE_EXIT 0U
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#define OPCODE_CLEAR 1U
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#define OPCODE_WRITE 2U
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#define OPCODE_MASKWRITE 3U
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#define OPCODE_MASKPOLL 4U
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#define OPCODE_MASKDELAY 5U
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#define NEW_PS7_ERR_CODE 1
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/* Encode number of arguments in last nibble */
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#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
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#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
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#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
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#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
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#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
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#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
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/* Returns codes of PS7_Init */
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#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
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#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
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#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
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#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
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#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
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||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
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|
||||
/* Silicon Versions */
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||||
#define PCW_SILICON_VERSION_1 0
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||||
#define PCW_SILICON_VERSION_2 1
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||||
#define PCW_SILICON_VERSION_3 2
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/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
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#define PS7_POST_CONFIG
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/* Freq of all peripherals */
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#define APU_FREQ 666666687
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#define DDR_FREQ 533333374
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#define DCI_FREQ 10158731
|
||||
#define QSPI_FREQ 190476196
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#define SMC_FREQ 10000000
|
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#define ENET0_FREQ 25000000
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#define ENET1_FREQ 10000000
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||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 50000000
|
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#define UART_FREQ 50000000
|
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#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
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#define WDT_FREQ 111111115
|
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#define TTC_FREQ 50000000
|
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#define CAN_FREQ 23809523
|
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#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 10000000
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#define FPGA0_FREQ 100000000
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||||
#define FPGA1_FREQ 50000000
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||||
#define FPGA2_FREQ 50000000
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||||
#define FPGA3_FREQ 50000000
|
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|
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|
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/* For delay calculation using global registers*/
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||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
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#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
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||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -1,15 +1,17 @@
|
|||
<?xml version="1.0"?>
|
||||
<Project Version="1" Minor="0">
|
||||
<BUILD_NUMBER Name="921552"/>
|
||||
<FULL_BUILD Name="SW Build 921552 on Mon May 26 14:24:56 MDT 2014"/>
|
||||
<BUILD_NUMBER Name="973827"/>
|
||||
<FULL_BUILD Name="SW Build 973827 on Sun Aug 3 20:32:33 MDT 2014"/>
|
||||
<MODE Name="Post-Bitstream"/>
|
||||
<SYSTEMINFO BOARD="" ARCH="zynq" PACKAGE="clg484" DEVICE="7z020" SPEED="-1"/>
|
||||
<SYSTEMINFO BOARD="" ARCH="zynq" PACKAGE="clg484" DEVICE="7z020" SPEED="-1" LUT="53200" FF="106400" BRAM="140" DSP="220"/>
|
||||
<HIERARCHY Name="zpe_without_controller_i"/>
|
||||
<File Type="HW_HANDOFF" Name="zpe_without_controller.hwh" ModTime="1402420880"/>
|
||||
<File Type="PS_FSBL_INIT" Name="ps7_init.c" ModTime="1402420880"/>
|
||||
<File Type="PS_FSBL_INIT" Name="ps7_init.h" ModTime="1402420880"/>
|
||||
<File Type="PS_XMD_INIT" Name="ps7_init.tcl" ModTime="1402420880"/>
|
||||
<File Type="PS_INIT_HELP" Name="ps7_init.html" ModTime="1402420880"/>
|
||||
<File Type="BIT" Name="zpe_without_controller_wrapper.bit" ModTime="1402432675"/>
|
||||
<File Type="HW_HANDOFF" Name="zpe_without_controller.hwh" ModTime="1407149188"/>
|
||||
<File Type="PS_FSBL_INIT" Name="ps7_init.c" ModTime="1407149188"/>
|
||||
<File Type="PS_FSBL_INIT" Name="ps7_init.h" ModTime="1407149188"/>
|
||||
<File Type="PS_XMD_INIT" Name="ps7_init.tcl" ModTime="1407149188"/>
|
||||
<File Type="PS_INIT_HELP" Name="ps7_init.html" ModTime="1407149188"/>
|
||||
<File Type="BIT" Name="zpe_without_controller_wrapper.bit" ModTime="1407155537"/>
|
||||
<File Type="BD_TCL" Name="zpe_without_controller_bd.tcl" ModTime="1407149188"/>
|
||||
<USEDRESOURCES LUT="38170" FF="36527" BRAM="56" DSP="0"/>
|
||||
</Project>
|
||||
|
||||
|
|
|
|||
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305
lib/zpe_templates/ZPE_ZC_702_HwPlatform/zpe_without_controller_bd.tcl
Executable file
305
lib/zpe_templates/ZPE_ZC_702_HwPlatform/zpe_without_controller_bd.tcl
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Loading…
Add table
Reference in a new issue