Added source files, integration files, self test example,
mdd and tcl files to cfa driver.
Signed-off-by: Shravan Kumar A <skumara@xilinx.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
Added source files, integration files, self test example,
mdd and tcl files to enhance driver.
Signed-off-by: Shravan Kumar A <skumara@xilinx.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
When enabling slave monitor, clear FIFO, enable read mode and clear
the transfer size register.
NACK interrupt should not be enabled as this will lead to the sw
being interrupted everytime a retry fails.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
This patch fixes issue of IAR compilation error of standalone BSP for cortexa9
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
Change CR_RESET_STATE defintion to include required bits to be set and
reset. When writing to the configuration register, read the register and
OR the required value to leave the reserved bits untouched.
Changes done in XQspiPs_Reset function and HW reset function.
The default value written was expanded to include setting hold bit and
using manual chip select (This is recommended and already explicitly
followed in all the examples).
Removed check for register values in selftest because a reset is done
in just the previous step where default values are already written.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
