High speed/wide bus operations involve data transfers. Hence these
buffers should be aligned and flushed/invalidated where required.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Change xilffs library to support data cache.
Dont disable data cache in the example.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>