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1 commit
master ... patch-axid

Author SHA1 Message Date
Steffen Vogel
e26f3a079f axidma: use virtual address for access to BD in XAxiDma_UpdateBdRingCDesc() 2016-04-19 19:57:22 +02:00
1 changed files with 13 additions and 13 deletions
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26
XilinxProcessorIPLib/drivers/axidma/src/xaxidma_bdring.c
View file

@ -221,31 +221,31 @@ int XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing* RingPtr)
if (!RingIndex) {
XAxiDma_WriteReg(RegBase,
XAXIDMA_CDESC_OFFSET,
(u32)(BdPtr & XAXIDMA_DESC_LSB_MASK));
(XAXIDMA_VIRT_TO_PHYS(BdPtr) & XAXIDMA_DESC_LSB_MASK));
if (RingPtr->Addr_ext)
XAxiDma_WriteReg(RegBase,
XAXIDMA_CDESC_MSB_OFFSET,
UPPER_32_BITS(BdPtr));
UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(BdPtr)));
}
else {
XAxiDma_WriteReg(RegBase,
(XAXIDMA_RX_CDESC0_OFFSET +
(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET),
(u32)(BdPtr & XAXIDMA_DESC_LSB_MASK));
(XAXIDMA_VIRT_TO_PHYS(BdPtr) & XAXIDMA_DESC_LSB_MASK));
if (RingPtr->Addr_ext)
XAxiDma_WriteReg(RegBase,
(XAXIDMA_RX_CDESC0_MSB_OFFSET +
(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET),
UPPER_32_BITS(BdPtr));
UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(BdPtr)));
}
}
else {
XAxiDma_WriteReg(RegBase,
XAXIDMA_CDESC_OFFSET,
(u32)(BdPtr & XAXIDMA_DESC_LSB_MASK));
(XAXIDMA_VIRT_TO_PHYS(BdPtr) & XAXIDMA_DESC_LSB_MASK));
if (RingPtr->Addr_ext)
XAxiDma_WriteReg(RegBase, XAXIDMA_CDESC_MSB_OFFSET,
UPPER_32_BITS(BdPtr));
UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(BdPtr)));
}
}
else {
@ -265,29 +265,29 @@ int XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing* RingPtr)
if (RingPtr->IsRxChannel) {
if (!RingIndex) {
XAxiDma_WriteReg(RegBase,
XAXIDMA_CDESC_OFFSET,(u32) (BdPtr & XAXIDMA_DESC_LSB_MASK));
XAXIDMA_CDESC_OFFSET,(XAXIDMA_VIRT_TO_PHYS(BdPtr) & XAXIDMA_DESC_LSB_MASK));
if (RingPtr->Addr_ext)
XAxiDma_WriteReg(RegBase, XAXIDMA_CDESC_MSB_OFFSET,
UPPER_32_BITS(BdPtr));
UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(BdPtr)));
}
else {
XAxiDma_WriteReg(RegBase,
(XAXIDMA_RX_CDESC0_OFFSET +
(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET),
(u32)(BdPtr & XAXIDMA_DESC_LSB_MASK));
(XAXIDMA_VIRT_TO_PHYS(BdPtr) & XAXIDMA_DESC_LSB_MASK));
if (RingPtr->Addr_ext)
XAxiDma_WriteReg(RegBase,
(XAXIDMA_RX_CDESC0_MSB_OFFSET +
(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET),
UPPER_32_BITS(BdPtr));
UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(BdPtr)));
}
}
else {
XAxiDma_WriteReg(RegBase,
XAXIDMA_CDESC_OFFSET, (u32)(BdPtr & XAXIDMA_DESC_LSB_MASK));
XAXIDMA_CDESC_OFFSET, (XAXIDMA_VIRT_TO_PHYS(BdPtr) & XAXIDMA_DESC_LSB_MASK));
if (RingPtr->Addr_ext)
XAxiDma_WriteReg(RegBase, XAXIDMA_CDESC_MSB_OFFSET,
UPPER_32_BITS(BdPtr));
UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(BdPtr)));
}
break;
}
@ -471,7 +471,7 @@ u32 XAxiDma_BdRingCreate(XAxiDma_BdRing *RingPtr, UINTPTR PhysAddr,
RingPtr->HwHead = (XAxiDma_Bd *) VirtAddr;
RingPtr->HwTail = (XAxiDma_Bd *) VirtAddr;
RingPtr->PostHead = (XAxiDma_Bd *) VirtAddr;
RingPtr->BdaRestart = (XAxiDma_Bd *) PhysAddr;
RingPtr->BdaRestart = (XAxiDma_Bd *) VirtAddr;
return XST_SUCCESS;
}