wdtps v2_0

The Xilinx watchdog timer driver supports the Xilinx watchdog timer hardware.

The Xilinx watchdog timer (WDT) driver supports the following features:

• Both Interrupt driven and Polled mode
• enabling and disabling the watchdog timer
• restarting the watchdog.
• initializing the most significant digit of the counter restart value.
• multiple individually enabling/disabling outputs

It is the responsibility of the application to provide an interrupt handler for the watchdog timer and connect it to the interrupt system if interrupt driven mode is desired.

If interrupt is enabled, the watchdog timer device generates an interrupt when the counter reaches zero.

If the hardware interrupt signal is not connected/enabled, polled mode is the only option (using IsWdtExpired) for the watchdog.

The outputs from the WDT are individually enabled/disabled using _EnableOutput()/_DisableOutput(). The clock divisor ratio and initial restart value of the count is configurable using _SetControlValues().

The reset condition of the hardware has the maximum initial count in the Counter Reset Value (CRV) and the WDT is disabled with the reset enable enabled and the reset length set to 32 clocks. i.e.

     register ZMR = 0x1C2
     register CCR = 0x3FC
 

This driver is intended to be RTOS and processor independent. It works with physical addresses only. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver.

 MODIFICATION HISTORY:

 Ver   Who    Date     Changes
 ----- ------ -------- -----------------------------------------------
 1.00a ecm/jz 01/15/10 First release
 1.01a asa    02/15/12 Added tcl file to generate xparameters
 1.02a  sg    07/15/12 Removed code/APIs related to  External Signal
			Length functionality for CR 658287
			Removed APIs XWdtPs_SetExternalSignalLength,
			XWdtPs_GetExternalSignalLength
			Modified the Self Test to use the Reset Length mask
			for CR 658287