Xilinx Processor IP Library

Software Drivers

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• XIICPS_ADDR_MASK : xiicps_hw.h
• XIICPS_ADDR_OFFSET : xiicps_hw.h
• XIICPS_CR_ACKEN_MASK : xiicps_hw.h
• XIICPS_CR_CLR_FIFO_MASK : xiicps_hw.h
• XIICPS_CR_DIV_A_MASK : xiicps_hw.h
• XIICPS_CR_DIV_A_SHIFT : xiicps_hw.h
• XIICPS_CR_DIV_B_MASK : xiicps_hw.h
• XIICPS_CR_DIV_B_SHIFT : xiicps_hw.h
• XIICPS_CR_HOLD_MASK : xiicps_hw.h
• XIICPS_CR_MS_MASK : xiicps_hw.h
• XIICPS_CR_NEA_MASK : xiicps_hw.h
• XIICPS_CR_OFFSET : xiicps_hw.h
• XIICPS_CR_RD_WR_MASK : xiicps_hw.h
• XIICPS_CR_RESET_VALUE : xiicps_hw.h
• XIICPS_CR_SLVMON_MASK : xiicps_hw.h
• XIICPS_DATA_INTR_DEPTH : xiicps_hw.h
• XIICPS_DATA_MASK : xiicps_hw.h
• XIICPS_DATA_OFFSET : xiicps_hw.h
• XIicPs_DisableAllInterrupts : xiicps_hw.h
• XIicPs_DisableInterrupts : xiicps_hw.h
• XIICPS_DIV_A_MAX : xiicps_hw.h
• XIicPs_EnableInterrupts : xiicps_hw.h
• XIICPS_FIFO_DEPTH : xiicps_hw.h
• XIICPS_IDR_OFFSET : xiicps_hw.h
• XIICPS_IER_OFFSET : xiicps_hw.h
• XIICPS_IMR_OFFSET : xiicps_hw.h
• XIICPS_ISR_OFFSET : xiicps_hw.h
• XIICPS_IXR_ALL_INTR_MASK : xiicps_hw.h
• XIICPS_IXR_ARB_LOST_MASK : xiicps_hw.h
• XIICPS_IXR_COMP_MASK : xiicps_hw.h
• XIICPS_IXR_DATA_MASK : xiicps_hw.h
• XIICPS_IXR_DEFAULT_MASK : xiicps_hw.h
• XIICPS_IXR_NACK_MASK : xiicps_hw.h
• XIICPS_IXR_RX_OVR_MASK : xiicps_hw.h
• XIICPS_IXR_RX_UNF_MASK : xiicps_hw.h
• XIICPS_IXR_SLV_RDY_MASK : xiicps_hw.h
• XIICPS_IXR_TO_MASK : xiicps_hw.h
• XIICPS_IXR_TX_OVR_MASK : xiicps_hw.h
• XIicPs_ReadIER : xiicps_hw.h
• XIicPs_ReadReg : xiicps_hw.h
• XIICPS_SLV_PAUSE_MASK : xiicps_hw.h
• XIICPS_SLV_PAUSE_OFFSET : xiicps_hw.h
• XIICPS_SR_BA_MASK : xiicps_hw.h
• XIICPS_SR_OFFSET : xiicps_hw.h
• XIICPS_SR_RXDV_MASK : xiicps_hw.h
• XIICPS_SR_RXOVF_MASK : xiicps_hw.h
• XIICPS_SR_RXRW_MASK : xiicps_hw.h
• XIICPS_SR_TXDV_MASK : xiicps_hw.h
• XIICPS_TIME_OUT_MASK : xiicps_hw.h
• XIICPS_TIME_OUT_OFFSET : xiicps_hw.h
• XIICPS_TO_RESET_VALUE : xiicps_hw.h
• XIICPS_TRANS_SIZE_MASK : xiicps_hw.h
• XIICPS_TRANS_SIZE_OFFSET : xiicps_hw.h
• XIicPs_WriteReg : xiicps_hw.h

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