MODIFICATION HISTORY:
Ver Who Date Changes ----- ---- -------- ------------------------------------------------------- 1.00a asa 6/30/10 First release based on the ll temac driver 1.02a asa 2/16/11 Made changes in XAxiEthernet_Reset to insert delays. 3.02a srt 4/13/13 Removed Warnings (CR 704998).
#include "xaxiethernet.h"
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XAxiEthernet_CfgInitialize initializes an AXI Ethernet device along with the InstancePtr that references it. The PHY is setup independently from the Ethernet core. Use the MII or whatever other interface may be present for setup.
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XAxiEthernet_ClearBadFrmRcvOption is used to disable the bad frame receive option.
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XAxiEthernet_ClearOptions clears the options, Options for the Axi Ethernet, specified by InstancePtr. Axi Ethernet should be stopped with XAxiEthernet_Stop() before changing options.
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XAxiEthernet_DisableControlFrameLenCheck is used to disable the length check for control frames (pause frames). This means once the API is called, control frames larger than the minimum frame length are accepted.
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XAxiEthernet_EnableControlFrameLenCheck is used to enable the length check for control frames (pause frames). After calling the API, all control frames received will be checked for proper length (less than minimum frame length). By default, upon normal start up, control frame length check is enabled. Hence this API needs to be called only if previously the control frame length check has been disabled by calling the API XAxiEthernet_DisableControlFrameLenCheck.
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XAxiEthernet_GetMacAddress gets the MAC address for the Axi Ethernet, specified by InstancePtr into the memory buffer specified by AddressPtr.
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XAxiEthernet_GetOperatingSpeed gets the current operating link speed. This may be the value set by XAxiEthernet_SetOperatingSpeed() or a hardware default.
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XAxiEthernet_GetOptions returns the current option settings.
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XAxiEthernet_PhySetMdioDivisor sets the MDIO clock divisor in the Axi Ethernet,specified by InstancePtr to the value, Divisor. This function must be called once after each reset prior to accessing MII PHY registers. From the Virtex-6(TM) and Spartan-6 (TM) Embedded Tri-Mode Ethernet MAC User's Guide, the following equation governs the MDIO clock to the PHY:
f[HOSTCLK] f[MDC] = ----------------------- (1 + Divisor) * 2 where f[HOSTCLK] is the bus clock frequency in MHz, and f[MDC] is the MDIO clock frequency in MHz to the PHY. Typically, f[MDC] should not exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster access.
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XAxiEthernet_Reset does not perform a soft reset of the AxiEthernet core. AxiEthernet hardware is reset by the device connected to the AXI4-Stream interface. This function inserts some delay before proceeding to check for MgtRdy bit. The delay is necessary to be at a safe side. It takes a while for the reset process to complete and for any of the AxiEthernet registers to be accessed. It then checks for MgtRdy bit in IS register to know if AxiEthernet reset is completed or not. Subsequently it calls one more driver function to complete the AxiEthernet hardware initialization.
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XAxiEthernet_SetBadFrmRcvOption is used to enable the bad frame receive option. If enabled, this option ensures that bad receive frames are allowed and passed to the AXI4-Stream interface as if they are good frames.
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XAxiEthernet_SetMacAddress sets the MAC address for the Axi Ethernet device, specified by InstancePtr to the MAC address specified by AddressPtr. The Axi Ethernet device must be stopped before calling this function.
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XAxiEthernet_SetOperatingSpeed sets the current operating link speed. For any traffic to be passed, this speed must match the current MII/GMII/SGMII/RGMII link speed.
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XAxiEthernet_SetOptions enables the options, Options for the Axi Ethernet, specified by InstancePtr. Axi Ethernet should be stopped with XAxiEthernet_Stop() before changing options.
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XAxiEthernet_Start starts the Axi Ethernet device as follows:
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XAxiEthernet_Stop gracefully stops the Axi Ethernet device as follows:
XAxiEthernet_Stop does not modify any of the current device options. Since the transmitter is not disabled, frames currently in internal buffers or in process by a DMA engine are allowed to be transmitted.
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