Overview

See xvphy.h for a detailed description of the driver.

Note: None.

MODIFICATION HISTORY:

Ver   Who  Date     Changes
----- ---- -------- -----------------------------------------------
1.0   als, 10/19/15 Initial release.
      gm

See xvphy.h for a detailed description of the driver.

Note: None.

MODIFICATION HISTORY:

Ver   Who  Date     Changes
----- ---- -------- -----------------------------------------------
1.0   als  10/19/15 Initial release.

Functions
void	XVphy_Ch2Ids (XVphy InstancePtr, XVphy_ChannelId ChId, u8 Id0, u8 *Id1)

void	XVphy_CfgInitialize (XVphy InstancePtr, XVphy_Config ConfigPtr, u32 EffectiveAddr)

u32	XVphy_PllInitialize (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_PllRefClkSelType QpllRefClkSel, XVphy_PllRefClkSelType CpllRefClkSel, XVphy_PllType TxPllSelect, XVphy_PllType RxPllSelect)

void	XVphy_WaitUs (XVphy *InstancePtr, u32 MicroSeconds)

u32	XVphy_ClkInitialize (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir)

u32	XVphy_GetVersion (XVphy *InstancePtr)

void	XVphy_SetRxLpm (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir, u8 Enable)

void	XVphy_SetTxVoltageSwing (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, u8 Vs)

void	XVphy_SetTxPreEmphasis (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, u8 Pe)

u32	XVphy_WriteCfgRefClkSelReg (XVphy *InstancePtr, u8 QuadId)

u32	XVphy_CfgLineRate (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, u64 LineRateHz)

u32	XVphy_CfgQuadRefClkFreq (XVphy *InstancePtr, u8 QuadId, XVphy_PllRefClkSelType RefClkType, u32 FreqHz)

void	XVphy_CfgPllRefClkSel (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_PllRefClkSelType RefClkSel)

void	XVphy_CfgSysClkDataSel (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, XVphy_SysClkDataSelType SysClkDataSel)

void	XVphy_CfgSysClkOutSel (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, XVphy_SysClkOutSelType SysClkOutSel)

XVphy_PllType	XVphy_GetPllType (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, XVphy_ChannelId ChId)

u32	XVphy_GetQuadRefClkFreq (XVphy *InstancePtr, u8 QuadId, XVphy_PllRefClkSelType RefClkType)

XVphy_PllRefClkSelType	XVphy_GetPllRefClkSel (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)

XVphy_SysClkDataSelType	XVphy_GetSysClkDataSel (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, XVphy_ChannelId ChId)

XVphy_SysClkOutSelType	XVphy_GetSysClkOutSel (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, XVphy_ChannelId ChId)

u32	XVphy_WaitForPmaResetDone (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir)

u32	XVphy_WaitForResetDone (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir)

u32	XVphy_WaitForPllLock (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)

u32	XVphy_IsPllLocked (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)

u32	XVphy_ResetGtPll (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir, u8 Hold)

u32	XVphy_ResetGtTxRx (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir, u8 Hold)

u32	XVphy_GtUserRdyEnable (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir, u8 Hold)

u32	XVphy_ResetGt (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir)

u32	XVphy_DrpWrite (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, u16 Addr, u16 Val)

u16	XVphy_DrpRead (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, u16 Addr)

void	XVphy_MmcmReset (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, u8 Hold)

void	XVphy_MmcmPowerDown (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, u8 Hold)

void	XVphy_MmcmStart (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir)

void	XVphy_MmcmLockedMaskEnable (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, u8 Enable)

void	XVphy_BufgGtReset (XVphy *InstancePtr, XVphy_DirectionType Dir, u8 Reset)

void	XVphy_SetBufgGtDiv (XVphy *InstancePtr, XVphy_DirectionType Dir, u8 Div)

void	XVphy_IBufDsEnable (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, u8 Enable)

void	XVphy_Clkout1OBufTdsEnable (XVphy *InstancePtr, XVphy_DirectionType Dir, u8 Enable)

void	XVphy_Set8b10b (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir, u8 Enable)

u32	XVphy_PowerDownGtPll (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, u8 Hold)

u32	XVphy_IsBonded (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)

u32	XVphy_ClkCalcParams (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir, u32 PllClkInFreqHz)

u32	XVphy_OutDivReconfig (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir)

u32	XVphy_DirReconfig (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir)

u32	XVphy_ClkReconfig (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)

Function Documentation

void XVphy_BufgGtReset	(	XVphy *	InstancePtr,
		XVphy_DirectionType	Dir,
		u8	Reset
	)

This function resets the BUFG_GT peripheral.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
Dir	is an indicator for TX or RX
Reset	specifies TRUE/FALSE value to either assert or deassert reset on the BUFG_GT, respectively.

Returns: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

void XVphy_CfgInitialize	(	XVphy *	InstancePtr,
		XVphy_Config *	ConfigPtr,
		u32	EffectiveAddr
	)

This function retrieves the configuration for this Video PHY instance and fills in the InstancePtr->Config structure.

Parameters

InstancePtr	is a pointer to the XVphy instance.
ConfigPtr	is a pointer to the configuration structure that will be used to copy the settings from.
EffectiveAddr	is the device base address in the virtual memory space. If the address translation is not used, then the physical address is passed.

Returns: None.

Note: Unexpected errors may occur if the address mapping is changed after this function is invoked.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_Config::DruRefClkSel, XVphy::IsReady, XVphy_Config::RxRefClkSel, XVphy_Config::RxSysPllClkSel, XVphy_Config::TxRefClkSel, XVphy_Config::TxSysPllClkSel, and XVphy_Config::XcvrType.

Referenced by XVphy_DpInitialize(), and XVphy_HdmiInitialize().

u32 XVphy_CfgLineRate	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId,
		u64	LineRateHz
	)

Configure the channel's line rate.

This is a software only configuration and this value is used in the PLL calculator.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID to operate on.
LineRate	is the line rate to configure software.

Returns

XST_SUCCESS if the reference clock type is valid.
XST_FAILURE otherwise.

Note: None.

References XVphy_Channel::LineRateHz, XVphy::Quads, and XVphy_Ch2Ids().

Referenced by XVphy_HdmiCpllParam(), and XVphy_HdmiQpllParam().

void XVphy_CfgPllRefClkSel	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId,
		XVphy_PllRefClkSelType	RefClkSel
	)

Configure the PLL reference clock selection for the specified channel(s).

This is applied to both direction to the software configuration only.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID to operate on.
SysClkDataSel	is the reference clock selection to configure.

Returns: None.

Note: None.

References XVphy::Quads, and XVphy_Ch2Ids().

Referenced by XVphy_HdmiRxTimerTimeoutHandler(), and XVphy_PllInitialize().

u32 XVphy_CfgQuadRefClkFreq	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_PllRefClkSelType	RefClkType,
		u32	FreqHz
	)

Configure the quad's reference clock frequency.

This is a software only configuration and this value is used in the PLL calculator.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
RefClkType	is the reference clock type to operate on.
FreqHz	is the reference clock frequency to configure software.

Returns

XST_SUCCESS if the reference clock type is valid.
XST_FAILURE otherwise.

Note: None.

References XVphy::Quads.

Referenced by XVphy_DpInitialize().

void XVphy_CfgSysClkDataSel	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_DirectionType	Dir,
		XVphy_SysClkDataSelType	SysClkDataSel
	)

Configure the SYSCLKDATA reference clock selection for the direction.

Same configuration applies to all channels in the quad. This is applied to the software configuration only.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
Dir	is an indicator for TX or RX.
SysClkDataSel	is the reference clock selection to configure.

Returns: None.

Note: None.

References XVphy::Quads, and XVphy_Ch2Ids().

Referenced by XVphy_HdmiQpllParam(), and XVphy_PllInitialize().

void XVphy_CfgSysClkOutSel	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_DirectionType	Dir,
		XVphy_SysClkOutSelType	SysClkOutSel
	)

Configure the SYSCLKOUT reference clock selection for the direction.

Same configuration applies to all channels in the quad. This is applied to the software configuration only.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
Dir	is an indicator for TX or RX.
SysClkOutSel	is the reference clock selection to configure.

Returns: None.

Note: None.

References XVphy::Quads, and XVphy_Ch2Ids().

Referenced by XVphy_HdmiQpllParam(), and XVphy_PllInitialize().

void XVphy_Ch2Ids	(	XVphy *	InstancePtr,
		XVphy_ChannelId	ChId,
		u8 *	Id0,
		u8 *	Id1
	)

This function will set the channel IDs to correspond with the supplied channel ID based on the protocol.

HDMI uses 3 channels; DP uses 4. This ID translation is done to allow other functions to operate iteratively over multiple channels.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
ChId	is the channel ID used to determine the indices.
Id0	is a pointer to the start channel ID to set.
Id1	is a pointer to the end channel ID to set.

Returns: None.

Note: The contents of Id0 and Id1 will be set according to ChId.

References XVphy::Config, XVphy_Config::TxProtocol, and XVphy_Config::XcvrType.

u32 XVphy_ClkCalcParams	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId,
		XVphy_DirectionType	Dir,
		u32	PllClkInFreqHz
	)

This function will try to find the necessary PLL divisor values to produce the configured line rate given the specified PLL input frequency.

This will be done for all channels specified by ChId. This function is a wrapper for XVphy_PllCalculator.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to calculate the PLL values for.
ChId	is the channel ID to calculate the PLL values for.
Dir	is an indicator for TX or RX.
PllClkInFreqHz	is the PLL input frequency on which to base the calculations on. A value of 0 indicates to use the currently configured quad PLL reference clock. A non-zero value indicates to ignore what is currently configured in SW, and use a custom frequency instead.

Returns

XST_SUCCESS if valid PLL values were found to satisfy the constraints.
XST_FAILURE otherwise.

Note: If successful, the channel's PllParams structure will be modified with the valid PLL parameters.

References XVphy_Ch2Ids().

Referenced by XVphy_ClkInitialize(), XVphy_HdmiCpllParam(), and XVphy_HdmiQpllParam().

u32 XVphy_ClkInitialize	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId,
		XVphy_DirectionType	Dir
	)

This function will initialize the clocking for a given channel.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID to operate on.
Dir	is an indicator for TX or RX.

Returns

XST_SUCCESS if the configuration was successful.
XST_FAILURE otherwise.

Note: None.

References XVphy_ClkCalcParams(), XVphy_ClkReconfig(), XVphy_DirReconfig(), and XVphy_OutDivReconfig().

void XVphy_Clkout1OBufTdsEnable	(	XVphy *	InstancePtr,
		XVphy_DirectionType	Dir,
		u8	Enable
	)

This function enables the TX or RX CLKOUT1 OBUFTDS peripheral.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
Dir	is an indicator for TX or RX.
Enable	specifies TRUE/FALSE value to either enable or disable the OBUFTDS, respectively.

Returns: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

u32 XVphy_ClkReconfig	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId
	)

This function will set the current clocking settings for each channel to hardware based on the configuration stored in the driver's instance.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID for which to write the settings for.

Returns

XST_SUCCESS if the configuration was successful.
XST_FAILURE otherwise.

Note: None.

References XVphy_Ch2Ids().

Referenced by XVphy_ClkInitialize(), XVphy_HdmiRxTimerTimeoutHandler(), and XVphy_HdmiTxTimerTimeoutHandler().

u32 XVphy_DirReconfig	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId,
		XVphy_DirectionType	Dir
	)

This function will set the current RX/TX configuration over DRP.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID for which to write the settings for.
Dir	is an indicator for RX or TX.

Returns

XST_SUCCESS if the configuration was successful.
XST_FAILURE otherwise.

Note: None.

References XVphy::Config, XVphy_Config::XcvrType, XVphy_Ch2Ids(), XVPHY_LOG_EVT_GT_RECONFIG, and XVphy_LogWrite().

Referenced by XVphy_ClkInitialize(), XVphy_HdmiRxTimerTimeoutHandler(), and XVphy_HdmiTxTimerTimeoutHandler().

u16 XVphy_DrpRead	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId,
		u16	Addr
	)

This function will initiate a read DRP transaction.

It is a wrapper around XVphy_DrpAccess.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID on which to direct the DRP access.
Dir	is an indicator for write (TX) or read (RX).
Addr	is the DRP address to issue the DRP access to.

Returns

XST_SUCCESS if the DRP access was successful.
XST_FAILURE otherwise, if the busy bit did not go low, or if the ready bit did not go high.

Note: None.

Referenced by XVphy_Gthe2ClkChReconfig(), XVphy_Gthe2ClkCmnReconfig(), XVphy_Gthe2OutDivChReconfig(), XVphy_Gthe3ClkChReconfig(), XVphy_Gthe3ClkCmnReconfig(), XVphy_Gthe3OutDivChReconfig(), XVphy_Gthe3RxChReconfig(), XVphy_Gthe3TxPllRefClkDiv1Reconfig(), XVphy_Gtxe2ClkChReconfig(), XVphy_Gtxe2ClkCmnReconfig(), XVphy_Gtxe2OutDivChReconfig(), XVphy_Gtxe2RxChReconfig(), and XVphy_Gtxe2TxPllRefClkDiv1Reconfig().

u32 XVphy_DrpWrite	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId,
		u16	Addr,
		u16	Val
	)

This function will initiate a write DRP transaction.

It is a wrapper around XVphy_DrpAccess.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID on which to direct the DRP access.
Dir	is an indicator for write (TX) or read (RX).
Addr	is the DRP address to issue the DRP access to.
Val	is the value to write to the DRP address.

Returns

XST_SUCCESS if the DRP access was successful.
XST_FAILURE otherwise, if the busy bit did not go low, or if the ready bit did not go high.

Note: None.

Referenced by XVphy_Gthe2ClkChReconfig(), XVphy_Gthe2ClkCmnReconfig(), XVphy_Gthe2OutDivChReconfig(), XVphy_Gthe2RxChReconfig(), XVphy_Gthe3ClkChReconfig(), XVphy_Gthe3ClkCmnReconfig(), XVphy_Gthe3OutDivChReconfig(), XVphy_Gthe3RxChReconfig(), XVphy_Gthe3TxPllRefClkDiv1Reconfig(), XVphy_Gtxe2ClkChReconfig(), XVphy_Gtxe2ClkCmnReconfig(), XVphy_Gtxe2OutDivChReconfig(), XVphy_Gtxe2RxChReconfig(), and XVphy_Gtxe2TxPllRefClkDiv1Reconfig().

XVphy_PllRefClkSelType XVphy_GetPllRefClkSel	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId
	)

Obtain the current PLL reference clock selection.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID which to operate on.

Returns: The current PLL reference clock selection.

Note: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy::Quads, and XVphy_ReadReg.

XVphy_PllType XVphy_GetPllType	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_DirectionType	Dir,
		XVphy_ChannelId	ChId
	)

Obtain the channel's PLL reference clock selection.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
Dir	is an indicator for TX or RX.
ChId	is the channel ID which to operate on.

Returns: The PLL type being used by the channel.

Note: None.

References XVphy_GetSysClkDataSel(), and XVphy_GetSysClkOutSel().

Referenced by XVphy_HdmiCpllLockHandler(), XVphy_HdmiQpllLockHandler(), XVphy_HdmiRxClkDetFreqChangeHandler(), XVphy_HdmiRxTimerTimeoutHandler(), XVphy_HdmiTxClkDetFreqChangeHandler(), and XVphy_HdmiTxTimerTimeoutHandler().

u32 XVphy_GetQuadRefClkFreq	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_PllRefClkSelType	RefClkType
	)

Obtain the current reference clock frequency for the quad based on the reference clock type.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
RefClkType	is the type to obtain the clock selection for.

Returns: The current reference clock frequency for the quad for the specified type selection.

Note: None.

References XVphy::Quads.

Referenced by XVphy_Gthe2CfgSetCdr(), and XVphy_Gthe3CfgSetCdr().

XVphy_SysClkDataSelType XVphy_GetSysClkDataSel	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_DirectionType	Dir,
		XVphy_ChannelId	ChId
	)

Obtain the current [RT]XSYSCLKSEL[0] configuration.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
Dir	is an indicator for TX or RX.
ChId	is the channel ID which to operate on.

Returns: The current [RT]XSYSCLKSEL[0] selection.

Note: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy::Quads, XVphy_Config::XcvrType, and XVphy_ReadReg.

Referenced by XVphy_GetPllType(), XVphy_IsBonded(), and XVphy_ResetGt().

XVphy_SysClkOutSelType XVphy_GetSysClkOutSel	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_DirectionType	Dir,
		XVphy_ChannelId	ChId
	)

Obtain the current [RT]XSYSCLKSEL[1] configuration.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
Dir	is an indicator for TX or RX.
ChId	is the channel ID which to operate on.

Returns: The current [RT]XSYSCLKSEL[1] selection.

Note: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy::Quads, XVphy_Config::XcvrType, and XVphy_ReadReg.

Referenced by XVphy_GetPllType(), XVphy_IsBonded(), and XVphy_ResetGt().

u32 XVphy_GetVersion ( XVphy * InstancePtr )

This function will obtian the IP version.

Parameters

InstancePtr is a pointer to the XVphy core instance.

Returns: The IP version of the Video PHY core.

Note: None.

References XVphy_Config::BaseAddr, XVphy::Config, and XVphy_ReadReg.

u32 XVphy_GtUserRdyEnable	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId,
		XVphy_DirectionType	Dir,
		u8	Hold
	)

This function will reset and enable the Video PHY's user core logic.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID which to operate on.
Dir	is an indicator for TX or RX.
Hold	is an indicator whether to "hold" the reset if set to 1. If set to 0: reset, then enable.

Returns

XST_SUCCESS.

Note: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

Referenced by XVphy_HdmiTxClkDetFreqChangeHandler().

void XVphy_IBufDsEnable	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_DirectionType	Dir,
		u8	Enable
	)

This function enables the TX or RX IBUFDS peripheral.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
Dir	is an indicator for TX or RX.
Enable	specifies TRUE/FALSE value to either enable or disable the IBUFDS, respectively.

Returns: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_Config::RxRefClkSel, XVphy_Config::TxRefClkSel, XVphy_ReadReg, and XVphy_WriteReg.

Referenced by XVphy_HdmiInitialize().

u32 XVphy_IsBonded	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId
	)

This function returns true when the RX and TX are bonded and are running from the same (RX) reference clock.

Parameters

InstancePtr is a pointer to the XVphy core instance.

Returns: TRUE if the RX and TX are using the same PLL, FALSE otherwise.

Note: None.

References XVphy_GetSysClkDataSel(), and XVphy_GetSysClkOutSel().

Referenced by XVphy_HdmiCpllLockHandler(), XVphy_HdmiCpllParam(), XVphy_HdmiGtRxResetDoneLockHandler(), XVphy_HdmiQpllLockHandler(), XVphy_HdmiRxClkDetFreqChangeHandler(), XVphy_HdmiRxTimerTimeoutHandler(), XVphy_SetHdmiRxParam(), and XVphy_SetHdmiTxParam().

u32 XVphy_IsPllLocked	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId
	)

This function will check the status of a PLL lock on the specified channel.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID which to operate on.

Returns

XST_SUCCESS if the specified PLL is locked.
XST_FAILURE otherwise.

Note: None.

References XVphy_Config::BaseAddr, XVphy::Config, and XVphy_ReadReg.

Referenced by XVphy_HdmiCpllLockHandler(), XVphy_HdmiQpllLockHandler(), and XVphy_WaitForPllLock().

void XVphy_MmcmLockedMaskEnable	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_DirectionType	Dir,
		u8	Enable
	)

This function will reset the mixed-mode clock manager (MMCM) core.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
Dir	is an indicator for TX or RX.
Enable	is an indicator whether to "Enable" the locked mask if set to 1. If set to 0: reset, then disable.

Returns: None.

Note: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

Referenced by XVphy_HdmiInitialize(), and XVphy_MmcmStart().

void XVphy_MmcmPowerDown	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_DirectionType	Dir,
		u8	Hold
	)

This function will power down the mixed-mode clock manager (MMCM) core.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
Dir	is an indicator for TX or RX.
Hold	is an indicator whether to "hold" the power down if set to 1. If set to 0: power down, then power back up.

Returns

XST_SUCCESS.

Note: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

Referenced by XVphy_HdmiInitialize(), XVphy_HdmiRxClkDetFreqChangeHandler(), XVphy_HdmiTxClkDetFreqChangeHandler(), and XVphy_MmcmStart().

void XVphy_MmcmReset	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_DirectionType	Dir,
		u8	Hold
	)

This function will reset the mixed-mode clock manager (MMCM) core.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
Dir	is an indicator for TX or RX.
Hold	is an indicator whether to "hold" the reset if set to 1. If set to 0: reset, then enable.

Returns

XST_SUCCESS.

Note: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

Referenced by XVphy_HdmiInitialize(), and XVphy_MmcmStart().

void XVphy_MmcmStart	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_DirectionType	Dir
	)

This function will start the mixed-mode clock manager (MMCM) core.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
Dir	is an indicator for TX or RX.

Returns: None.

Note: None.

References XVphy::Config, XVphy_Config::RxProtocol, XVphy_Config::TxProtocol, XVphy_MmcmLockedMaskEnable(), XVphy_MmcmPowerDown(), XVphy_MmcmReset(), and XVphy_WaitUs().

Referenced by XVphy_HdmiTxTimerTimeoutHandler().

u32 XVphy_OutDivReconfig	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId,
		XVphy_DirectionType	Dir
	)

This function will set the current output divider configuration over DRP.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID for which to write the settings for.
Dir	is an indicator for RX or TX.

Returns

XST_SUCCESS if the configuration was successful.
XST_FAILURE otherwise.

Note: None.

References XVphy_Ch2Ids(), XVPHY_LOG_EVT_GT_RECONFIG, and XVphy_LogWrite().

Referenced by XVphy_ClkInitialize(), XVphy_HdmiRxTimerTimeoutHandler(), and XVphy_HdmiTxTimerTimeoutHandler().

u32 XVphy_PllInitialize	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId,
		XVphy_PllRefClkSelType	QpllRefClkSel,
		XVphy_PllRefClkSelType	CpllRefClkSel,
		XVphy_PllType	TxPllSelect,
		XVphy_PllType	RxPllSelect
	)

This function will initialize the PLL selection for a given channel.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID to operate on.
QpllRefClkSel	is the QPLL reference clock selection for the quad.
CpllRefClkSel	is the CPLL reference clock selection for the quad.
TxPllSelect	is the reference clock selection for the quad's TX PLL dividers.
RxPllSelect	is the reference clock selection for the quad's RX PLL dividers.

Returns

XST_SUCCESS.

Note: None.

References XVphy_CfgPllRefClkSel(), XVphy_CfgSysClkDataSel(), XVphy_CfgSysClkOutSel(), and XVphy_WriteCfgRefClkSelReg().

Referenced by XVphy_DpInitialize().

u32 XVphy_PowerDownGtPll	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId,
		u8	Hold
	)

This function will power down the specified GT PLL.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID to power down the PLL for.
Dir	is an indicator for TX or RX.
Hold	is an indicator whether to "hold" the power down if set to 1. If set to 0: power down, then power back up.

Returns

XST_SUCCESS.

Note: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_Ch2Ids(), XVphy_ReadReg, and XVphy_WriteReg.

Referenced by XVphy_HdmiInitialize(), XVphy_HdmiRxClkDetFreqChangeHandler(), XVphy_HdmiRxTimerTimeoutHandler(), XVphy_HdmiTxClkDetFreqChangeHandler(), and XVphy_HdmiTxTimerTimeoutHandler().

u32 XVphy_ResetGt	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_DirectionType	Dir
	)

This function will reset the specified GT quad.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
Dir	is an indicator for TX or RX.

Returns

XST_SUCCESS if a valid PLL was specified.
XST_FAILURE otherwise.

Note: None.

References XVphy_GetSysClkDataSel(), XVphy_GetSysClkOutSel(), and XVphy_ResetGtPll().

u32 XVphy_ResetGtPll	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId,
		XVphy_DirectionType	Dir,
		u8	Hold
	)

This function will reset the GT's PLL logic.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID which to operate on.
Dir	is an indicator for TX or RX.
Hold	is an indicator whether to "hold" the reset if set to 1. If set to 0: reset, then enable.

Returns

XST_SUCCESS.

Note: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

Referenced by XVphy_HdmiInitialize(), XVphy_HdmiRxClkDetFreqChangeHandler(), XVphy_HdmiRxTimerTimeoutHandler(), XVphy_HdmiTxClkDetFreqChangeHandler(), XVphy_HdmiTxTimerTimeoutHandler(), XVphy_HdmiUpdateClockSelection(), and XVphy_ResetGt().

u32 XVphy_ResetGtTxRx	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId,
		XVphy_DirectionType	Dir,
		u8	Hold
	)

This function will reset the GT's TX/RX logic.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID which to operate on.
Dir	is an indicator for TX or RX.
Hold	is an indicator whether to "hold" the reset if set to 1. If set to 0: reset, then enable.

Returns

XST_SUCCESS.

Note: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

Referenced by XVphy_HdmiCpllLockHandler(), XVphy_HdmiGtRxResetDoneLockHandler(), XVphy_HdmiInitialize(), XVphy_HdmiQpllLockHandler(), XVphy_HdmiRxClkDetFreqChangeHandler(), XVphy_HdmiRxTimerTimeoutHandler(), XVphy_HdmiTxClkDetFreqChangeHandler(), and XVphy_HdmiTxTimerTimeoutHandler().

void XVphy_Set8b10b	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId,
		XVphy_DirectionType	Dir,
		u8	Enable
	)

This function will set 8b10b encoding for the specified GT PLL.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID to operate on.
Dir	is an indicator for TX or RX.
Enable	is an indicator to enable/disable 8b10b encoding.

Returns

XST_SUCCESS.

Note: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

Referenced by XVphy_DpInitialize().

void XVphy_SetBufgGtDiv	(	XVphy *	InstancePtr,
		XVphy_DirectionType	Dir,
		u8	Div
	)

This function obtains the divider value of the BUFG_GT peripheral.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
Dir	is an indicator for TX or RX
Div	3-bit divider value

Returns: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

Referenced by XVphy_HdmiInitialize(), and XVphy_HdmiTxTimerTimeoutHandler().

void XVphy_SetRxLpm	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId,
		XVphy_DirectionType	Dir,
		u8	Enable
	)

This function will enable or disable the LPM logic in the Video PHY core.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID to operate on.
Dir	is an indicator for TX or RX.
Enable	will enable (if 1) or disable (if 0) the LPM logic.

Returns: None.

Note: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

Referenced by XVphy_DpInitialize(), and XVphy_HdmiInitialize().

void XVphy_SetTxPreEmphasis	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId,
		u8	Pe
	)

This function will set the TX pre-emphasis value for a given channel.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID to operate on.
Pe	is the pre-emphasis value to write.

Returns: None.

Note: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

Referenced by XVphy_DpInitialize(), and XVphy_HdmiInitialize().

void XVphy_SetTxVoltageSwing	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId,
		u8	Vs
	)

This function will set the TX voltage swing value for a given channel.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID to operate on.
Vs	is the voltage swing value to write.

Returns: None.

Note: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

Referenced by XVphy_DpInitialize(), and XVphy_HdmiInitialize().

u32 XVphy_WaitForPllLock	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId
	)

This function will wait for a PLL lock on the specified channel(s) or time out.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID which to operate on.

Returns

XST_SUCCESS if the PLL(s) have locked.
XST_FAILURE otherwise; waiting for the lock timed out.

Note: None.

References XVphy_IsPllLocked(), and XVphy_WaitUs().

u32 XVphy_WaitForPmaResetDone	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId,
		XVphy_DirectionType	Dir
	)

This function will wait for a PMA reset done on the specified channel(s) or time out.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID which to operate on.
Dir	is an indicator for TX or RX.

Returns

XST_SUCCESS if the PMA reset has finalized.
XST_FAILURE otherwise; waiting for the reset done timed out.

Note: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WaitUs().

u32 XVphy_WaitForResetDone	(	XVphy *	InstancePtr,
		u8	QuadId,
		XVphy_ChannelId	ChId,
		XVphy_DirectionType	Dir
	)

This function will wait for a reset done on the specified channel(s) or time out.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.
ChId	is the channel ID which to operate on.
Dir	is an indicator for TX or RX.

Returns

XST_SUCCESS if the reset has finalized.
XST_FAILURE otherwise; waiting for the reset done timed out.

Note: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WaitUs().

void XVphy_WaitUs	(	XVphy *	InstancePtr,
		u32	MicroSeconds
	)

This function is the delay/sleep function for the XVphy driver.

For the Zynq family, there exists native sleep functionality. For MicroBlaze however, there does not exist such functionality. In the MicroBlaze case, the default method for delaying is to use a predetermined amount of loop iterations. This method is prone to inaccuracy and dependent on system configuration; for greater accuracy, the user may supply their own delay/sleep handler, pointed to by InstancePtr->UserTimerWaitUs, which may have better accuracy if a hardware timer is used.

Parameters

InstancePtr	is a pointer to the XVphy instance.
MicroSeconds	is the number of microseconds to delay/sleep for.

Returns: None.

Note: None.

References XVphy::IsReady, and XVphy::UserTimerWaitUs.

Referenced by XVphy_MmcmStart(), XVphy_WaitForPllLock(), XVphy_WaitForPmaResetDone(), and XVphy_WaitForResetDone().

u32 XVphy_WriteCfgRefClkSelReg	(	XVphy *	InstancePtr,
		u8	QuadId
	)

This function writes the current software configuration for the reference clock selections to hardware for the specified quad on all channels.

Parameters

InstancePtr	is a pointer to the XVphy core instance.
QuadId	is the GT quad ID to operate on.

Returns

XST_SUCCESS.

Note: None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_Channel::CpllRefClkSel, XVphy::Quads, XVphy_Channel::RxDataRefClkSel, XVphy_Channel::RxOutRefClkSel, XVphy_Channel::TxDataRefClkSel, XVphy_Channel::TxOutRefClkSel, XVphy_Config::XcvrType, and XVphy_WriteReg.

Referenced by XVphy_HdmiRxTimerTimeoutHandler(), XVphy_HdmiTxTimerTimeoutHandler(), XVphy_PllInitialize(), XVphy_SetHdmiRxParam(), and XVphy_SetHdmiTxParam().

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