srio v1_0

This file contains the implementation of the SRIO Gen2 driver. User documentation for the driver functions is contained in this file in the form of comment blocks at the front of each function.

The SRIO Gen2 Core supports RapidIO Interconnect Specification rev. 2.2 The SRIO Gen2 Endpoint comprises of the phy ,logical and transport and buffer layers. Using the SRIO Gen2 Endpoint Core we can generate I/O transactions Read(NREAD), Write(NWRITE), Read with response (NREAD_R), Stream write(SWRITE) atomic operations(atomic set,clear,test and swap etc...). It also supports Messaging Transactions Message (MESSAGE), Doorbell(DOORBELL)and 8-bit/16-bit device ID's.

Initialization & Configuration

The XSrio_Config structure is used by the driver to configure itself. This configuration structure is typically created by the tool-chain based on HW build properties.

To support multiple runtime loading and initialization strategies employed by various operating systems, the driver instance can be initialized in the following way:

• XSrio_LookupConfig(DeviceId) - Use the device identifier to find the static configuration structure defined in xsrio_g.c. This is setup by the tools. For some operating systems the config structure will be initialized by the software and this call is not needed.

• XSrio_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a configuration structure provided by the caller. If running in a system with address translation, the provided virtual memory base address replaces the physical address present in the configuration structure.

Interrupts There are no interrupts available for the SRIO Gen2 Core.

Examples

There is an example provided to show the usage of the APIs

• SRIO Dma loopback example (xsrio_dma_loopback_example.c)

Asserts

Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.

RTOS Independence

This driver is intended to be RTOS and processor independent. It works with physical addresses only. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver.

 MODIFICATION HISTORY:

 Ver   Who  Date     Changes
 ----- ---- -------- -------------------------------------------------------
 1.0   adk  16/04/14 Initial release.