xadcps v2_1

The XAdcPs driver supports the Xilinx XADC/ADC device.

The XADC/ADC device has the following features:

• 10-bit, 200-KSPS (kilo samples per second) Analog-to-Digital Converter (ADC)
• Monitoring of on-chip supply voltages and temperature
• 1 dedicated differential analog-input pair and 16 auxiliary differential analog-input pairs
• Automatic alarms based on user defined limits for the on-chip supply voltages and temperature
• Automatic Channel Sequencer, programmable averaging, programmable acquisition time for the external inputs, unipolar or differential input selection for the external inputs
• Inbuilt Calibration
• Optional interrupt request generation

The user should refer to the hardware device specification for detailed information about the device.

This header file contains the prototypes of driver functions that can be used to access the XADC/ADC device.

XADC Channel Sequencer Modes

The XADC Channel Sequencer supports the following operating modes:

• Default : This is the default mode after power up. In this mode of operation the XADC operates in a sequence mode, monitoring the on chip sensors: Temperature, VCCINT, and VCCAUX.
• One pass through sequence : In this mode the XADC converts the channels enabled in the Sequencer Channel Enable registers for a single pass and then stops.
• Continuous cycling of sequence : In this mode the XADC converts the channels enabled in the Sequencer Channel Enable registers continuously.
• Single channel mode: In this mode the XADC Channel Sequencer is disabled and the XADC operates in a Single Channel Mode. The XADC can operate either in a Continuous or Event driven sampling mode in the single channel mode.
• Simultaneous Sampling Mode: In this mode the XADC Channel Sequencer will automatically sequence through eight fixed pairs of auxiliary analog input channels for simulataneous conversion.
• Independent ADC mode: In this mode the first ADC (A) is used to is used to implement a fixed monitoring mode similar to the default mode but the alarm fucntions ar eenabled. The second ADC (B) is available to be used with external analog input channels only.

Read the XADC spec for more information about the sequencer modes.

Initialization and Configuration

The device driver enables higher layer software (e.g., an application) to communicate to the XADC/ADC device.

XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC device. The user needs to first call the XAdcPs_LookupConfig() API which returns the Configuration structure pointer which is passed as a parameter to the XAdcPs_CfgInitialize() API.

Interrupts

The XADC/ADC device supports interrupt driven mode and the default operation mode is polling mode.

The interrupt mode is available only if hardware is configured to support interrupts.

This driver does not provide a Interrupt Service Routine (ISR) for the device. It is the responsibility of the application to provide one if needed. Refer to the interrupt example provided with this driver for details on using the device in interrupt mode.

Virtual Memory

This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.

Threads

This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.

Asserts

Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.

Building the driver

The XAdcPs driver is composed of several source files. This allows the user to build and link only those parts of the driver that are necessary.

Limitations of the driver

XADC/ADC device can be accessed through the JTAG port and the PLB interface. The driver implementation does not support the simultaneous access of the device by both these interfaces. The user has to care of this situation in the user application code.

 MODIFICATION HISTORY:

 Ver   Who    Date     Changes
 ----- -----  -------- -----------------------------------------------------
 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
 1.01a bss    02/18/13	Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
			XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
			in xadcps.c to fix CR #693371
 1.03a bss    11/01/13 Modified xadcps_hw.h to use correct Register offsets
			CR#749687
 2.1   bss    08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
			XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
			XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
			functions.
			Modified Assert for XAdcPs_SetSingleChParams in
			xadcps.c to fix CR #807563.