MODIFICATION HISTORY:
Ver Who Date Changes ----- ---- -------- ----------------------------------------------- 1.00a als 05/17/14 Initial release.
#include "xil_io.h"
#include "xil_types.h"
| #define XDPTX_AUX_ADDRESS 0x0108 |
Specifies the address of current AUX command.
| #define XDPTX_AUX_CLK_DIVIDER 0x010C |
Clock divider value for generating the internal 1MHz clock.
| #define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK 0x00000F00 |
AUX (noise) signal width filter.
| #define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT 8 |
Shift bits for AUX signal width filter.
| #define XDPTX_AUX_CLK_DIVIDER_VAL_MASK 0x0000000F |
Clock divider value.
| #define XDPTX_AUX_CMD 0x0100 |
Initiates AUX commands.
| #define XDPTX_AUX_CMD_ADDR_ONLY_TRANSFER_EN 0x00001000 |
Address only transfer enable (STOP will be sent after command).
| #define XDPTX_AUX_CMD_I2C_READ 0x1 |
I2C-over-AUX read command.
| #define XDPTX_AUX_CMD_I2C_READ_MOT 0x5 |
I2C-over-AUX read MOT (middle-of-transaction) command.
| #define XDPTX_AUX_CMD_I2C_WRITE 0x0 |
I2C-over-AUX write command.
| #define XDPTX_AUX_CMD_I2C_WRITE_MOT 0x4 |
I2C-over-AUX write MOT (middle-of-transaction) command.
| #define XDPTX_AUX_CMD_I2C_WRITE_STATUS 0x2 |
I2C-over-AUX write status command.
| #define XDPTX_AUX_CMD_I2C_WRITE_STATUS_MOT 0x6 |
I2C-over-AUX write status MOT (middle-of- transaction) command.
| #define XDPTX_AUX_CMD_MASK 0x00000F00 |
AUX command.
| #define XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK 0x0000000F |
Number of bytes to transfer with the current AUX command.
| #define XDPTX_AUX_CMD_READ 0x9 |
AUX read command.
| #define XDPTX_AUX_CMD_SHIFT 8 |
Shift bits for command.
| #define XDPTX_AUX_CMD_WRITE 0x8 |
AUX write command.
| #define XDPTX_AUX_REPLY_CODE 0x0138 |
Reply code received from the most recent AUX command.
| #define XDPTX_AUX_REPLY_CODE_ACK 0x0 |
AUX command ACKed.
| #define XDPTX_AUX_REPLY_CODE_DEFER 0x2 |
AUX command deferred.
| #define XDPTX_AUX_REPLY_CODE_I2C_ACK 0x0 |
I2C-over-AUX command not ACKed.
| #define XDPTX_AUX_REPLY_CODE_I2C_DEFER 0x8 |
I2C-over-AUX command deferred.
| #define XDPTX_AUX_REPLY_CODE_I2C_NACK 0x4 |
I2C-over-AUX command not ACKed.
| #define XDPTX_AUX_REPLY_CODE_NACK 0x1 |
AUX command not ACKed.
| #define XDPTX_AUX_REPLY_COUNT 0x013C |
Number of reply transactions receieved over AUX.
| #define XDPTX_AUX_REPLY_DATA 0x0134 |
Reply data received during the AUX reply.
| #define XDPTX_AUX_WRITE_FIFO 0x0104 |
Write data for the current AUX command.
| #define XDPTX_CORE_ID 0x00FC |
DisplayPort revision.
| #define XDPTX_CORE_ID_DP_MJR_VER_MASK 0x0000F000 |
DisplayPort protocol major version.
| #define XDPTX_CORE_ID_DP_MJR_VER_SHIFT 24 |
Shift bits for DisplayPort protocol major version.
| #define XDPTX_CORE_ID_DP_MNR_VER_MASK 0x00000F00 |
DisplayPort protocol minor version.
| #define XDPTX_CORE_ID_DP_MNR_VER_SHIFT 16 |
Shift bits for DisplayPort protocol major version.
| #define XDPTX_CORE_ID_DP_REV_MASK 0x000000F0 |
DisplayPort protocol revision.
| #define XDPTX_CORE_ID_DP_REV_SHIFT 8 |
Shift bits for DisplayPort protocol revision.
| #define XDPTX_CORE_ID_TYPE_MASK 0x0000000F |
Core type.
| #define XDPTX_CORE_ID_TYPE_RX 0x1 |
Core is a receiver.
| #define XDPTX_CORE_ID_TYPE_TX 0x0 |
Core is a transmitter.
| #define XDPTX_DOWNSPREAD_CTRL 0x0018 |
Enable a 0.5% spreading of the clock.
| #define XDPTX_ENABLE 0x0080 |
Enable the basic operations of the transmitter or output stuffing symbols if disabled.
| #define XDPTX_ENABLE_MAIN_STREAM 0x0084 |
Enable transmission of main link video info.
| #define XDPTX_ENABLE_SEC_STREAM 0x0088 |
Enable the transmission of secondary link info.
| #define XDPTX_ENHANCED_FRAME_EN 0x0008 |
Enable enhanced framing symbol sequence.
| #define XDPTX_FORCE_SCRAMBLER_RESET 0x00C0 |
Force a scrambler reset.
| #define XDPTX_FRAC_BYTES_PER_TU 0x01C8 |
The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register value.
| #define XDPTX_FRAC_BYTES_PER_TU_STREAM2 0x0548 |
The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register value.
| #define XDPTX_FRAC_BYTES_PER_TU_STREAM3 0x0598 |
The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register value.
| #define XDPTX_FRAC_BYTES_PER_TU_STREAM4 0x05E8 |
The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register value.
| #define XDPTX_GT_DRP_CHANNEL_STATUS 0x02A8 |
Provides access to GT DRP channel status.
| #define XDPTX_GT_DRP_COMMAND 0x02A0 |
Provides acces to the GT DRP ports.
| #define XDPTX_GT_DRP_COMMAND_DRP_ADDR_MASK 0x000F |
DRP address.
| #define XDPTX_GT_DRP_COMMAND_DRP_RW_CMD_MASK 0x0080 |
DRP read/write command (Read=0, Write=1).
| #define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_MASK 0xFF00 |
DRP write data.
| #define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT 16 |
Shift bits for DRP write data.
| #define XDPTX_GT_DRP_READ_DATA 0x02A4 |
Provides access to GT DRP read data.
| #define XDPTX_HPD_DURATION 0x0150 |
Duration of the HPD pulse in microseconds.
| #define XDPTX_INIT_WAIT 0x01CC |
Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO.
| #define XDPTX_INIT_WAIT_STREAM2 0x054C |
Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO.
| #define XDPTX_INIT_WAIT_STREAM3 0x059C |
Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO.
| #define XDPTX_INIT_WAIT_STREAM4 0x05EC |
Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO.
| #define XDPTX_INTERRUPT_MASK 0x0144 |
Masks the specified interrupt sources.
| #define XDPTX_INTERRUPT_MASK_EXT_PKT_TXD_MASK 0x00000020 |
Mask extended packet transmit interrupt.
| #define XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK 0x00000002 |
Mask HPD event interrupt.
| #define XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK 0x00000001 |
Mask HPD IRQ interrupt.
| #define XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK 0x00000010 |
Mask HPD pulse detected interrupt.
| #define XDPTX_INTERRUPT_MASK_REPLY_RECEIVED_MASK 0x00000004 |
Mask reply received interrupt.
| #define XDPTX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK 0x00000008 |
Mask reply received interrupt.
| #define XDPTX_INTERRUPT_SIG_STATE 0x0130 |
The raw signal values for interupt events.
| #define XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK 0x00000001 |
Raw state of the HPD pin on the DP connector.
| #define XDPTX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK 0x00000004 |
A reply is currently being received.
| #define XDPTX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK 0x00000008 |
A reply timeout has occurred.
| #define XDPTX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK 0x00000002 |
A request is currently being sent.
| #define XDPTX_INTERRUPT_STATUS 0x0140 |
Status for interrupt events.
| #define XDPTX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK 0x00000020 |
Extended packet has been transmitted and the core is ready to accept a new packet.
| #define XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK 0x00000002 |
Detected the presence of the HPD signal.
| #define XDPTX_INTERRUPT_STATUS_HPD_IRQ_MASK 0x00000001 |
Detected an IRQ framed with the proper timing on the HPD signal.
| #define XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK 0x00000010 |
A pulse on the HPD line was detected.
| #define XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK 0x00000004 |
An AUX reply transaction has been detected.
| #define XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK 0x00000008 |
A reply timeout has occurred.
| #define XDPTX_LANE_COUNT_SET 0x0004 |
Set lane count setting.
| #define XDPTX_LINK_BW_SET 0x0000 |
Set main link bandwidth setting.
| #define XDPTX_LINK_BW_SET_162GBPS 0x06 |
1.62 Gbps link rate.
| #define XDPTX_LINK_BW_SET_270GBPS 0x0A |
2.70 Gbps link rate.
| #define XDPTX_LINK_BW_SET_540GBPS 0x14 |
5.40 Gbps link rate.
| #define XDPTX_LINK_QUAL_PATTERN_SET 0x0010 |
Transmit the link quality pattern.
| #define XDPTX_LINK_QUAL_PATTERN_SET_D102_TEST 0x1 |
D10.2 unscrambled test pattern transmitted.
| #define XDPTX_LINK_QUAL_PATTERN_SET_OFF 0x0 |
Link quality test pattern not transmitted.
| #define XDPTX_LINK_QUAL_PATTERN_SET_PRBS7 0x3 |
Pseudo random bit sequence 7 transmitted.
| #define XDPTX_LINK_QUAL_PATTERN_SET_SER_MES 0x2 |
Symbol error rate measurement pattern transmitted.
| #define XDPTX_M_VID 0x01AC |
M value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode.
| #define XDPTX_M_VID_STREAM2 0x052C |
M value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode.
| #define XDPTX_M_VID_STREAM3 0x057C |
M value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode.
| #define XDPTX_M_VID_STREAM4 0x05CC |
M value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode.
| #define XDPTX_MAIN_STREAM2_HRES 0x0514 |
Number of active pixels per line (the horizontal resolution).
| #define XDPTX_MAIN_STREAM2_HSTART 0x051C |
Number of clocks between the leading edge of the horizontal sync and the start of active data.
| #define XDPTX_MAIN_STREAM2_HSWIDTH 0x050C |
Width of the horizontal sync pulse.
| #define XDPTX_MAIN_STREAM2_HTOTAL 0x0500 |
Total number of clocks in the horizontal framing period.
| #define XDPTX_MAIN_STREAM2_INTERLACED 0x0540 |
Video is interlaced.
| #define XDPTX_MAIN_STREAM2_MISC0 0x0524 |
Miscellaneous stream attributes.
| #define XDPTX_MAIN_STREAM2_MISC1 0x0528 |
Miscellaneous stream attributes.
| #define XDPTX_MAIN_STREAM2_POLARITY 0x0508 |
Polarity for the video sync signals.
| #define XDPTX_MAIN_STREAM2_VRES 0x0518 |
Number of active lines (the vertical resolution).
| #define XDPTX_MAIN_STREAM2_VSTART 0x0520 |
Number of lines between the leading edge of the vertical sync and the first line of active data.
| #define XDPTX_MAIN_STREAM2_VSWIDTH 0x0510 |
Width of the vertical sync pulse.
| #define XDPTX_MAIN_STREAM2_VTOTAL 0x0504 |
Total number of lines in the video frame.
| #define XDPTX_MAIN_STREAM3_HRES 0x0564 |
Number of active pixels per line (the horizontal resolution).
| #define XDPTX_MAIN_STREAM3_HSTART 0x056C |
Number of clocks between the leading edge of the horizontal sync and the start of active data.
| #define XDPTX_MAIN_STREAM3_HSWIDTH 0x055C |
Width of the horizontal sync pulse.
| #define XDPTX_MAIN_STREAM3_HTOTAL 0x0550 |
Total number of clocks in the horizontal framing period.
| #define XDPTX_MAIN_STREAM3_INTERLACED 0x0590 |
Video is interlaced.
| #define XDPTX_MAIN_STREAM3_MISC0 0x0574 |
Miscellaneous stream attributes.
| #define XDPTX_MAIN_STREAM3_MISC1 0x0578 |
Miscellaneous stream attributes.
| #define XDPTX_MAIN_STREAM3_POLARITY 0x0558 |
Polarity for the video sync signals.
| #define XDPTX_MAIN_STREAM3_VRES 0x0568 |
Number of active lines (the vertical resolution).
| #define XDPTX_MAIN_STREAM3_VSTART 0x0570 |
Number of lines between the leading edge of the vertical sync and the first line of active data.
| #define XDPTX_MAIN_STREAM3_VSWIDTH 0x0560 |
Width of the vertical sync pulse.
| #define XDPTX_MAIN_STREAM3_VTOTAL 0x0554 |
Total number of lines in the video frame.
| #define XDPTX_MAIN_STREAM4_HRES 0x05B4 |
Number of active pixels per line (the horizontal resolution).
| #define XDPTX_MAIN_STREAM4_HSTART 0x05BC |
Number of clocks between the leading edge of the horizontal sync and the start of active data.
| #define XDPTX_MAIN_STREAM4_HSWIDTH 0x05AC |
Width of the horizontal sync pulse.
| #define XDPTX_MAIN_STREAM4_HTOTAL 0x05A0 |
Total number of clocks in the horizontal framing period.
| #define XDPTX_MAIN_STREAM4_INTERLACED 0x05E0 |
Video is interlaced.
| #define XDPTX_MAIN_STREAM4_MISC0 0x05C4 |
Miscellaneous stream attributes.
| #define XDPTX_MAIN_STREAM4_MISC1 0x05C8 |
Miscellaneous stream attributes.
| #define XDPTX_MAIN_STREAM4_POLARITY 0x05A8 |
Polarity for the video sync signals.
| #define XDPTX_MAIN_STREAM4_VRES 0x05B8 |
Number of active lines (the vertical resolution).
| #define XDPTX_MAIN_STREAM4_VSTART 0x05C0 |
Number of lines between the leading edge of the vertical sync and the first line of active data.
| #define XDPTX_MAIN_STREAM4_VSWIDTH 0x05B0 |
Width of the vertical sync pulse.
| #define XDPTX_MAIN_STREAM4_VTOTAL 0x05A4 |
Total number of lines in the video frame.
| #define XDPTX_MAIN_STREAM_HRES 0x0194 |
Number of active pixels per line (the horizontal resolution).
| #define XDPTX_MAIN_STREAM_HSTART 0x019C |
Number of clocks between the leading edge of the horizontal sync and the start of active data.
| #define XDPTX_MAIN_STREAM_HSWIDTH 0x018C |
Width of the horizontal sync pulse.
| #define XDPTX_MAIN_STREAM_HTOTAL 0x0180 |
Total number of clocks in the horizontal framing period.
| #define XDPTX_MAIN_STREAM_INTERLACED 0x01C0 |
Video is interlaced.
| #define XDPTX_MAIN_STREAM_MISC0 0x01A4 |
Miscellaneous stream attributes.
| #define XDPTX_MAIN_STREAM_MISC1 0x01A8 |
Miscellaneous stream attributes.
| #define XDPTX_MAIN_STREAM_POLARITY 0x0188 |
Polarity for the video sync signals.
| #define XDPTX_MAIN_STREAM_VRES 0x0198 |
Number of active lines (the vertical resolution).
| #define XDPTX_MAIN_STREAM_VSTART 0x01A0 |
Number of lines between the leading edge of the vertical sync and the first line of active data.
| #define XDPTX_MAIN_STREAM_VSWIDTH 0x0190 |
Width of the vertical sync pulse.
| #define XDPTX_MAIN_STREAM_VTOTAL 0x0184 |
Total number of lines in the video frame.
| #define XDPTX_MAIN_STREAMX_MISC0_BDC_MASK 0x000000E0 |
Bit depth per color component (BDC).
| #define XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT 5 |
Shift bits for BDC.
| #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK 0x00000006 |
Component format.
| #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT 1 |
Shift bits for component format.
| #define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK 0x00000008 |
Dynamic range.
| #define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT 3 |
Shift bits for dynamic range.
| #define XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK 0x00000001 |
Synchronous clock.
| #define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK 0x00000010 |
YCbCr colorimetry.
| #define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT 4 |
Shift bits for YCbCr colorimetry.
| #define XDPTX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK 0x00000001 |
Interlaced vertical total even.
| #define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK 0x00000006 |
Stereo video attribute.
| #define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT 1 |
Shift bits for stereo video attribute.
| #define XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK 0x00000001 |
Polarity of the horizontal sync pulse.
| #define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK 0x00000002 |
Polarity of the vertical sync pulse.
| #define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT 1 |
Shift bits for polarity of the vertical sync pulse.
| #define XDPTX_MIN_BYTES_PER_TU 0x01C4 |
The minimum number of bytes per transfer unit.
| #define XDPTX_MIN_BYTES_PER_TU_STREAM2 0x0544 |
The minimum number of bytes per transfer unit.
| #define XDPTX_MIN_BYTES_PER_TU_STREAM3 0x0594 |
The minimum number of bytes per transfer unit.
| #define XDPTX_MIN_BYTES_PER_TU_STREAM4 0x05E4 |
The minimum number of bytes per transfer unit.
| #define XDPTX_N_VID 0x01B4 |
N value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode.
| #define XDPTX_N_VID_STREAM2 0x0534 |
N value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode.
| #define XDPTX_N_VID_STREAM3 0x0584 |
N value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode.
| #define XDPTX_N_VID_STREAM4 0x05D4 |
N value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode.
| #define XDPTX_PE_LEVEL_0 0x00 |
Pre-emphasis level 0.
| #define XDPTX_PE_LEVEL_1 0x0E |
Pre-emphasis level 1.
| #define XDPTX_PE_LEVEL_2 0x14 |
Pre-emphasis level 2.
| #define XDPTX_PE_LEVEL_3 0x1B |
Pre-emphasis level 3.
| #define XDPTX_PHY_CLOCK_SELECT 0x0234 |
Instructs the PHY PLL to generate the proper clock frequency for the required link rate.
| #define XDPTX_PHY_CLOCK_SELECT_162GBPS 0x1 |
1.62 Gbps link.
| #define XDPTX_PHY_CLOCK_SELECT_270GBPS 0x3 |
2.70 Gbps link.
| #define XDPTX_PHY_CLOCK_SELECT_540GBPS 0x5 |
5.40 Gbps link.
| #define XDPTX_PHY_CONFIG 0x0200 |
Transceiver PHY reset and configuration.
| #define XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK 0x0010003 |
Rest GT and PHY.
| #define XDPTX_PHY_CONFIG_GTTX_RESET_MASK 0x0010002 |
Hold GTTXRESET in reset.
| #define XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK 0x0010000 |
Release reset.
| #define XDPTX_PHY_CONFIG_PHY_RESET_MASK 0x0010001 |
Hold the PHY in reset.
| #define XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK 0x001E000 |
Set TX_PHY_LOOPBACK.
| #define XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK 0x0010200 |
HOLD TX_PHY_PCS reset.
| #define XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK 0x0010100 |
Hold TX_PHY_PMA reset.
| #define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK 0x0010400 |
Set TX_PHY_POLARITY.
| #define XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK 0x0011000 |
Set TX_PHY_PRBSFORCEERR.
| #define XDPTX_PHY_POSTCURSOR_LANE_0 0x024C |
Controls the post-cursor level.
| #define XDPTX_PHY_POSTCURSOR_LANE_1 0x0250 |
Controls the post-cursor level.
| #define XDPTX_PHY_POSTCURSOR_LANE_2 0x0254 |
Controls the post-cursor level.
| #define XDPTX_PHY_POSTCURSOR_LANE_3 0x0258 |
Controls the post-cursor level.
| #define XDPTX_PHY_PRECURSOR_LANE_0 0x023C |
Controls the pre-cursor level.
| #define XDPTX_PHY_PRECURSOR_LANE_1 0x0240 |
Controls the pre-cursor level.
| #define XDPTX_PHY_PRECURSOR_LANE_2 0x0244 |
Controls the pre-cursor level.
| #define XDPTX_PHY_PRECURSOR_LANE_3 0x0248 |
Controls the pre-cursor level.
| #define XDPTX_PHY_STATUS 0x0280 |
Current PHY status.
| #define XDPTX_PHY_STATUS_ALL_LANES_READY_MASK 0x0000003F |
All lanes are ready.
| #define XDPTX_PHY_STATUS_PLL_FABRIC_LOCK_MASK 0x00000020 |
FPGA fabric clock PLL locked.
| #define XDPTX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK 0x00000010 |
PLL locked for lanes 0 and 1.
| #define XDPTX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK 0x00000020 |
PLL locked for lanes 2 and 3.
| #define XDPTX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK 0x00000003 |
Reset done for lanes 0 and 1.
| #define XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK 0x0000000C |
Reset done for lanes 2 and 3.
| #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK 0x00030000 |
TX buffer status lane 0.
| #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT 16 |
Shift bits for TX buffer status lane 0.
| #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK 0x00300000 |
TX buffer status lane 1.
| #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT 20 |
Shift bits for TX buffer status lane 1.
| #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK 0x03000000 |
TX buffer status lane 2.
| #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT 24 |
Shift bits for TX buffer status lane 2.
| #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK 0x30000000 |
TX buffer status lane 3.
| #define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT 28 |
Shift bits for TX buffer status lane 3.
| #define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_MASK 0x000C0000 |
TX error on lane 0.
| #define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT 18 |
Shift bits for TX error on lane 0.
| #define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_MASK 0x00C00000 |
TX error on lane 1.
| #define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT 22 |
Shift bits for TX error on lane 1.
| #define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_MASK 0x0C000000 |
TX error on lane 2.
| #define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT 26 |
Shift bits for TX error on lane 2.
| #define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_MASK 0xC0000000 |
TX error on lane 3.
| #define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT 30 |
Shift bits for TX error on lane 3.
| #define XDPTX_PHY_TRANSMIT_PRBS7 0x0230 |
Enable pseudo random bit sequence 7 pattern transmission for link quality assessment.
| #define XDPTX_PHY_VOLTAGE_DIFF_LANE_0 0x0220 |
Controls the differential voltage swing.
| #define XDPTX_PHY_VOLTAGE_DIFF_LANE_1 0x0224 |
Controls the differential voltage swing.
| #define XDPTX_PHY_VOLTAGE_DIFF_LANE_2 0x0228 |
Controls the differential voltage swing.
| #define XDPTX_PHY_VOLTAGE_DIFF_LANE_3 0x022C |
Controls the differential voltage swing.
| #define XDptx_ReadReg | ( | BaseAddress, | |||
| RegOffset | ) | XDptx_In32((BaseAddress) + (RegOffset)) |
This is a low-level function that reads from the specified register.
| BaseAddress | is the base address of the device. | |
| RegOffset | is the register offset to be read from. |
| #define XDPTX_REPLY_DATA_COUNT 0x0148 |
Total number of data bytes actually received during a transaction.
| #define XDPTX_REPLY_STATUS 0x014C |
Reply status of most recent AUX transaction.
| #define XDPTX_REPLY_STATUS_REPLY_ERROR_MASK 0x00000008 |
Detected an error in the AUX reply of the most recent transaction.
| #define XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK 0x00000002 |
AUX reply is currently being received.
| #define XDPTX_REPLY_STATUS_REPLY_RECEIVED_MASK 0x00000001 |
AUX transaction is complete and a valid reply transaction received.
| #define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_MASK 0x00000FF0 |
Internal AUX reply state machine status bits.
| #define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT 4 |
Shift bits for the internal AUX reply state machine status.
| #define XDPTX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK 0x00000004 |
AUX request is currently being transmitted.
| #define XDPTX_SCRAMBLING_DISABLE 0x0014 |
Disable scrambler and transmit all symbols.
| #define XDPTX_SOFT_RESET 0x001C |
Software reset.
| #define XDPTX_SOFT_RESET_AUX_MASK 0x00000080 |
Reset AUX logic.
| #define XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK 0x00000001 |
Reset video logic.
| #define XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK 0x00000002 |
Reset video logic.
| #define XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK 0x00000004 |
Reset video logic.
| #define XDPTX_SOFT_RESET_VIDEO_STREAM4_MASK 0x00000008 |
Reset video logic.
| #define XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK 0x0000000F |
Reset video logic for all streams.
| #define XDPTX_STREAM0 0x01D0 |
Average stream symbol timeslots per MTP config.
| #define XDPTX_STREAM1 0x01D4 |
Average stream symbol timeslots per MTP config.
| #define XDPTX_STREAM2 0x01D8 |
Average stream symbol timeslots per MTP config.
| #define XDPTX_STREAM3 0x01DC |
Average stream symbol timeslots per MTP config.
| #define XDPTX_TRAINING_PATTERN_SET 0x000C |
Set the link training pattern.
| #define XDPTX_TRAINING_PATTERN_SET_OFF 0x0 |
Training off.
| #define XDPTX_TRAINING_PATTERN_SET_TP1 0x1 |
Training pattern 1 used for clock recovery.
| #define XDPTX_TRAINING_PATTERN_SET_TP2 0x2 |
Training pattern 2 used for channel equalization.
| #define XDPTX_TRAINING_PATTERN_SET_TP3 0x3 |
Training pattern 3 used for channel equalization for cores with DP v1.2.
| #define XDPTX_TU_SIZE 0x01B0 |
Size of a transfer unit in the framing logic.
| #define XDPTX_TU_SIZE_STREAM2 0x0530 |
Size of a transfer unit in the framing logic.
| #define XDPTX_TU_SIZE_STREAM3 0x0580 |
Size of a transfer unit in the framing logic.
| #define XDPTX_TU_SIZE_STREAM4 0x05D0 |
Size of a transfer unit in the framing logic.
| #define XDPTX_TX_AUDIO_CHANNELS 0x0304 |
Used to input active channel count.
| #define XDPTX_TX_AUDIO_CONTROL 0x0300 |
Enables audio stream packets in main link and buffer control.
| #define XDPTX_TX_AUDIO_EXT_DATA 0x0330 |
Word formatted as per extension packet.
| #define XDPTX_TX_AUDIO_INFO_DATA 0x0308 |
Word formatted as per CEA 861-C info frame.
| #define XDPTX_TX_AUDIO_MAUD 0x0328 |
M value of audio stream as computed by the transmitter when audio clock and link clock are synchronous.
| #define XDPTX_TX_AUDIO_NAUD 0x032C |
N value of audio stream as computed by the transmitter when audio clock and link clock are synchronous.
| #define XDPTX_TX_MST_CONFIG 0x00D0 |
Enable MST.
| #define XDPTX_TX_MST_CONFIG_MST_EN_MASK 0x00000001 |
Enable MST.
| #define XDPTX_TX_MST_CONFIG_VCP_UPDATED_MASK 0x00000002 |
The VC payload has been updated in the sink.
| #define XDPTX_TX_PHY_POWER_DOWN 0x0238 |
Controls PHY power down.
| #define XDPTX_TX_USER_FIFO_OVERFLOW 0x0110 |
Indicates an overflow in user FIFO.
| #define XDPTX_USER_DATA_COUNT_PER_LANE 0x01BC |
Used to translate the number of pixels per line to the native internal 16-bit datapath.
| #define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM2 0x053C |
Used to translate the number of pixels per line to the native internal 16-bit datapath.
| #define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM3 0x058C |
Used to translate the number of pixels per line to the native internal 16-bit datapath.
| #define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM4 0x05DC |
Used to translate the number of pixels per line to the native internal 16-bit datapath.
| #define XDPTX_USER_PIXEL_WIDTH 0x01B8 |
Selects the width of the user data input port.
| #define XDPTX_USER_PIXEL_WIDTH_STREAM2 0x0538 |
Selects the width of the user data input port.
| #define XDPTX_USER_PIXEL_WIDTH_STREAM3 0x0588 |
Selects the width of the user data input port.
| #define XDPTX_USER_PIXEL_WIDTH_STREAM4 0x05D8 |
Selects the width of the user data input port.
| #define XDPTX_VC_PAYLOAD_BUFFER_ADDR 0x0800 |
Virtual channel payload table (0xFF bytes).
| #define XDPTX_VERSION 0x00F8 |
Core version.
| #define XDPTX_VERSION_CORE_PATCH_MASK 0x00000030 |
Core patch details.
| #define XDPTX_VERSION_CORE_PATCH_SHIFT 8 |
Shift bits for core patch details.
| #define XDPTX_VERSION_CORE_VER_MJR_MASK 0x0000F000 |
Core major version.
| #define XDPTX_VERSION_CORE_VER_MJR_SHIFT 24 |
Shift bits for core major version.
| #define XDPTX_VERSION_CORE_VER_MNR_MASK 0x00000F00 |
Core minor version.
| #define XDPTX_VERSION_CORE_VER_MNR_SHIFT 16 |
Shift bits for core minor version.
| #define XDPTX_VERSION_CORE_VER_REV_MASK 0x000000C0 |
Core version revision.
| #define XDPTX_VERSION_CORE_VER_REV_SHIFT 12 |
Shift bits for core version revision.
| #define XDPTX_VERSION_INTER_REV_MASK 0x0000000F |
Internal revision.
| #define XDPTX_VS_LEVEL_0 0x2 |
Voltage swing level 0.
| #define XDPTX_VS_LEVEL_1 0x5 |
Voltage swing level 1.
| #define XDPTX_VS_LEVEL_2 0x8 |
Voltage swing level 2.
| #define XDPTX_VS_LEVEL_3 0xF |
Voltage swing level 3.
| #define XDPTX_VS_LEVEL_OFFSET 0x4 |
Voltage swing compensation offset used when there's no redriver in display path.
| #define XDptx_WriteReg | ( | BaseAddress, | |||
| RegOffset, | |||||
| Data | ) | XDptx_Out32((BaseAddress) + (RegOffset), (Data)) |
This is a low-level function that writes to the specified register.
| BaseAddress | is the base address of the device. | |
| RegOffset | is the register offset to write to. | |
| Data | is the 32-bit data to write to the specified register. |
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