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Xilinx Driver axipcie v3_0: axipcie v3_0
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<h3 class="PageHeader">Xilinx Processor IP Library</h3>
<hl>Software Drivers</hl>
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<h1>axipcie v3_0</h1><p>This file contains the software API definition of the Xilinx AXI PCIe IP (<a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a>). This driver provides "C" function interface to application/upper layer to access the hardware.</p>
<p><b>Features</b> The driver provides its user with entry points</p>
<ul>
<li>To initialize and configure itself and the hardware</li>
<li>To access PCIe configuration space locally</li>
<li>To enable/disable and to report errors (interrupts).</li>
</ul>
<p><b>IP Hardware Configuration</b> The AXI PCIE IP supports only the endpoint for Virtex�-6 and Spartan�-6 families.</p>
<p>The AXI PCIE IP supports both the endpoint and Root Port for the Kintex� 7 devices.</p>
<p><b>Driver Initialization & Configuration</b></p>
<p>The <a class="el" href="struct_x_axi_pcie___config.html">XAxiPcie_Config</a> structure is used by the driver to configure itself. This configuration structure is typically created by the tool-chain based on HW build properties.</p>
<p>To support multiple runtime loading and initialization strategies employed by various operating systems, the driver instance can be initialized in the following way:</p>
<ul>
<li>XAxiPcie_LookupConfig(DeviceId) - Use the device identifier to find the static configuration structure defined in <a class="el" href="xaxipcie__g_8c.html">xaxipcie_g.c</a>. This is setup by the tools. For some operating systems the config structure will be initialized by the software and this call is not needed.</li>
</ul>
<ul>
<li>XAxiPcie_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a configuration structure provided by the caller. If running in a system with address translation, the provided virtual memory base address replaces the physical address present in the configuration structure.</li>
</ul>
<p><b>Interrupt Management</b></p>
<p>The <a class="el" href="struct_x_axi_pcie.html">XAxiPcie</a> driver provides interrupt management functions. It allows the caller to enable/disable each individual interrupt as well as get/clear pending interrupts. Implementation of callback handlers is left to the user.</p>
<dl class="note"><dt><b>Note:</b></dt><dd></dd></dl>
<pre>
MODIFICATION HISTORY:</pre><pre> Ver Who Date Changes
----- ---- -------- ------------------------------------------------------
1.00a rkv 03/03/11 Original code.
2.00a nm 10/19/11 Added support of pcie root complex functionality.
Changed these functions
-renamed function XAxiPcie_GetRequestId to
XAxiPcie_GetRequesterId
-added two functions arguments RootPortPtr &
ECAMSizePtr to XAxiPcie_GetBridgeInfo API
Added these new API for root complex support</p>
<ul>
<li>XAxiPcie_GetRootPortStatusCtrl</li>
<li>XAxiPcie_SetRootPortStatusCtrl</li>
<li>XAxiPcie_SetRootPortMSIBase</li>
<li>XAxiPcie_GetRootPortErrFIFOMsg</li>
<li>XAxiPcie_ClearRootPortErrFIFOMsg</li>
<li>XAxiPcie_GetRootPortIntFIFOReg</li>
<li>XAxiPcie_ClearRootPortIntFIFOReg</li>
<li>XAxiPcie_WriteLocalConfigSpace</li>
<li>XAxiPcie_ComposeExternalConfigAddress</li>
<li>XAxiPcie_ReadRemoteConfigSpace</li>
<li>XAxiPcie_WriteRemoteConfigSpace</li>
</ul>
</pre><pre> 2.01a nm 04/01/12 Removed XAxiPcie_SetRequesterId and
XAxiPcie_SetBlPortNumber APIs as these are writing
to Read Only bits for CR638299.
2.02a nm 08/01/12 Updated for removing compilation errors with C++,
changed XCOMPONENT_IS_READY to XIL_COMPONENT_IS_READY
Removed the Endian Swap in
XAxiPcie_ReadRemoteConfigSpace and
XAxiPcie_WriteRemoteConfigSpace APIs as the HW
has been fixed and the swapping is not required
in the driver (CR 657412)
2.03a srt 04/13/13 Removed Warnings (CR 705004).
2.04a srt 09/06/13 Fixed CR 734175:
C_BASEADDR and C_HIGHADDR configuration parameters are
renamed to BASEADDR and HIGHADDR in Vivado builds.
Modified the tcl for this change.
3.0 adk 19/12/13 Updated as per the New Tcl API's</pre><pre> </pre> </div>
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