Classes |
struct | XEmacPs_Config |
struct | XEmacPs |
Defines |
#define | XEMACPS_H |
#define | XEMACPS_DEVICE_NAME "xemacps" |
#define | XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC" |
#define | XEMACPS_MDIO_DIV_DFT MDC_DIV_32 |
#define | XEMACPS_MAC_ADDR_SIZE 6 |
#define | XEMACPS_MTU 1500 |
#define | XEMACPS_HDR_SIZE 14 |
#define | XEMACPS_HDR_VLAN_SIZE 18 |
#define | XEMACPS_TRL_SIZE 4 |
#define | XEMACPS_MAX_FRAME_SIZE |
#define | XEMACPS_MAX_VLAN_FRAME_SIZE |
#define | XEMACPS_SINGLE_BURST 1 |
#define | XEMACPS_4BYTE_BURST 4 |
#define | XEMACPS_8BYTE_BURST 8 |
#define | XEMACPS_16BYTE_BURST 16 |
#define | XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing) |
#define | XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing) |
#define | XEmacPs_IntEnable(InstancePtr, Mask) |
#define | XEmacPs_IntDisable(InstancePtr, Mask) |
#define | XEmacPs_Transmit(InstancePtr) |
#define | XEmacPs_IsRxCsum(InstancePtr) |
#define | XEmacPs_IsTxCsum(InstancePtr) |
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Device configuration options. See the XEmacPs_SetOptions(), XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to use options.
The default state of the options are noted and are what the device and driver will be set to after calling XEmacPs_Reset() or XEmacPs_Initialize().
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#define | XEMACPS_PROMISC_OPTION 0x00000001 |
#define | XEMACPS_FRAME1536_OPTION 0x00000002 |
#define | XEMACPS_VLAN_OPTION 0x00000004 |
#define | XEMACPS_FLOW_CONTROL_OPTION 0x00000010 |
#define | XEMACPS_FCS_STRIP_OPTION 0x00000020 |
#define | XEMACPS_FCS_INSERT_OPTION 0x00000040 |
#define | XEMACPS_LENTYPE_ERR_OPTION 0x00000080 |
#define | XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100 |
#define | XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200 |
#define | XEMACPS_BROADCAST_OPTION 0x00000400 |
#define | XEMACPS_MULTICAST_OPTION 0x00000800 |
#define | XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000 |
#define | XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000 |
#define | XEMACPS_DEFAULT_OPTIONS |
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These constants are used as parameters to XEmacPs_SetHandler()
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#define | XEMACPS_HANDLER_DMASEND 1 |
#define | XEMACPS_HANDLER_DMARECV 2 |
#define | XEMACPS_HANDLER_ERROR 3 |
Typedefs |
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These callbacks are invoked in interrupt context.
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typedef void(* | XEmacPs_Handler )(void *CallBackRef) |
typedef void(* | XEmacPs_ErrHandler )(void *CallBackRef, u8 Direction, u32 ErrorWord) |
Functions |
int | XEmacPs_CfgInitialize (XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr, u32 EffectiveAddress) |
void | XEmacPs_Start (XEmacPs *InstancePtr) |
void | XEmacPs_Stop (XEmacPs *InstancePtr) |
void | XEmacPs_Reset (XEmacPs *InstancePtr) |
XEmacPs_Config * | XEmacPs_LookupConfig (u16 DeviceId) |
int | XEmacPs_SetHandler (XEmacPs *InstancePtr, u32 HandlerType, void *FuncPtr, void *CallBackRef) |
void | XEmacPs_IntrHandler (void *InstancePtr) |
int | XEmacPs_SetOptions (XEmacPs *InstancePtr, u32 Options) |
int | XEmacPs_ClearOptions (XEmacPs *InstancePtr, u32 Options) |
u32 | XEmacPs_GetOptions (XEmacPs *InstancePtr) |
int | XEmacPs_SetMacAddress (XEmacPs *InstancePtr, void *AddressPtr, u8 Index) |
void | XEmacPs_GetMacAddress (XEmacPs *InstancePtr, void *AddressPtr, u8 Index) |
int | XEmacPs_SetHash (XEmacPs *InstancePtr, void *AddressPtr) |
void | XEmacPs_ClearHash (XEmacPs *InstancePtr) |
void | XEmacPs_GetHash (XEmacPs *InstancePtr, void *AddressPtr) |
void | XEmacPs_SetMdioDivisor (XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor) |
void | XEmacPs_SetOperatingSpeed (XEmacPs *InstancePtr, u16 Speed) |
u16 | XEmacPs_GetOperatingSpeed (XEmacPs *InstancePtr) |
int | XEmacPs_PhyRead (XEmacPs *InstancePtr, u32 PhyAddress, u32 RegisterNum, u16 *PhyDataPtr) |
int | XEmacPs_PhyWrite (XEmacPs *InstancePtr, u32 PhyAddress, u32 RegisterNum, u16 PhyData) |
int | XEmacPs_SetTypeIdCheck (XEmacPs *InstancePtr, u32 Id_Check, u8 Index) |
int | XEmacPs_SendPausePacket (XEmacPs *InstancePtr) |
void | XEmacPs_DMABLengthUpdate (XEmacPs *InstancePtr, int BLength) |
#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080 |
Enable Length/Type error checking for incoming frames. When this option is set, the MAC will filter frames that have a mismatched type/length field and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these types of frames are encountered. When this option is cleared, the MAC will allow these types of frames to be received.
This option defaults to disabled (cleared)
int XEmacPs_PhyRead |
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XEmacPs * |
InstancePtr, |
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u32 |
PhyAddress, |
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u32 |
RegisterNum, |
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u16 * |
PhyDataPtr | |
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) |
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Read the current value of the PHY register indicated by the PhyAddress and the RegisterNum parameters. The MAC provides the driver with the ability to talk to a PHY that adheres to the Media Independent Interface (MII) as defined in the IEEE 802.3 standard.
Prior to PHY access with this function, the user should have setup the MDIO clock with XEmacPs_SetMdioDivisor().
- Parameters:
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| InstancePtr | is a pointer to the XEmacPs instance to be worked on. |
| PhyAddress | is the address of the PHY to be read (supports multiple PHYs) |
| RegisterNum | is the register number, 0-31, of the specific PHY register to read |
| PhyDataPtr | is an output parameter, and points to a 16-bit buffer into which the current value of the register will be copied. |
- Returns:
- XST_SUCCESS if the PHY was read from successfully
- XST_EMAC_MII_BUSY if there is another PHY operation in progress
- Note:
This function is not thread-safe. The user must provide mutually exclusive access to this function if there are to be multiple threads that can call it.
There is the possibility that this function will not return if the hardware is broken (i.e., it never sets the status bit indicating that the read is done). If this is of concern to the user, the user should provide a mechanism suitable to their needs for recovery.
For the duration of this function, all host interface reads and writes are blocked to the current XEmacPs instance.
int XEmacPs_PhyWrite |
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XEmacPs * |
InstancePtr, |
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u32 |
PhyAddress, |
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u32 |
RegisterNum, |
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u16 |
PhyData | |
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) |
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Write data to the specified PHY register. The Ethernet driver does not require the device to be stopped before writing to the PHY. Although it is probably a good idea to stop the device, it is the responsibility of the application to deem this necessary. The MAC provides the driver with the ability to talk to a PHY that adheres to the Media Independent Interface (MII) as defined in the IEEE 802.3 standard.
Prior to PHY access with this function, the user should have setup the MDIO clock with XEmacPs_SetMdioDivisor().
- Parameters:
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| InstancePtr | is a pointer to the XEmacPs instance to be worked on. |
| PhyAddress | is the address of the PHY to be written (supports multiple PHYs) |
| RegisterNum | is the register number, 0-31, of the specific PHY register to write |
| PhyData | is the 16-bit value that will be written to the register |
- Returns:
- XST_SUCCESS if the PHY was written to successfully. Since there is no error status from the MAC on a write, the user should read the PHY to verify the write was successful.
- XST_EMAC_MII_BUSY if there is another PHY operation in progress
- Note:
This function is not thread-safe. The user must provide mutually exclusive access to this function if there are to be multiple threads that can call it.
There is the possibility that this function will not return if the hardware is broken (i.e., it never sets the status bit indicating that the write is done). If this is of concern to the user, the user should provide a mechanism suitable to their needs for recovery.
For the duration of this function, all host interface reads and writes are blocked to the current XEmacPs instance.
void XEmacPs_Reset |
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XEmacPs * |
InstancePtr |
) |
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Perform a graceful reset of the Ethernet MAC. Resets the DMA channels, the transmitter, and the receiver.
Steps to reset
- Stops transmit and receive channels
- Stops DMA
- Configure transmit and receive buffer size to default
- Clear transmit and receive status register and counters
- Clear all interrupt sources
- Clear phy (if there is any previously detected) address
- Clear MAC addresses (1-4) as well as Type IDs and hash value
All options are placed in their default state. Any frames in the descriptor lists will remain in the lists. The side effect of doing this is that after a reset and following a restart of the device, frames were in the list before the reset may be transmitted or received.
The upper layer software is responsible for re-configuring (if necessary) and restarting the MAC after the reset. Note also that driver statistics are not cleared on reset. It is up to the upper layer software to clear the statistics if needed.
When a reset is required, the driver notifies the upper layer software of this need through the ErrorHandler callback and specific status codes. The upper layer software is responsible for calling this Reset function and then re-configuring the device.
- Parameters:
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| InstancePtr | is a pointer to the instance to be worked on. |
int XEmacPs_SetHash |
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XEmacPs * |
InstancePtr, |
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void * |
AddressPtr | |
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Set 48-bit MAC addresses in hash table. The device must be stopped before calling this function.
The hash address register is 64 bits long and takes up two locations in the memory map. The least significant bits are stored in hash register bottom and the most significant bits in hash register top.
The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. The destination address is reduced to a 6 bit index into the 64 bit hash register using the following hash function. The hash function is an XOR of every sixth bit of the destination address.
hash_index[05] = da[05]^da[11]^da[17]^da[23]^da[29]^da[35]^da[41]^da[47]
hash_index[04] = da[04]^da[10]^da[16]^da[22]^da[28]^da[34]^da[40]^da[46]
hash_index[03] = da[03]^da[09]^da[15]^da[21]^da[27]^da[33]^da[39]^da[45]
hash_index[02] = da[02]^da[08]^da[14]^da[20]^da[26]^da[32]^da[38]^da[44]
hash_index[01] = da[01]^da[07]^da[13]^da[19]^da[25]^da[31]^da[37]^da[43]
hash_index[00] = da[00]^da[06]^da[12]^da[18]^da[24]^da[30]^da[36]^da[42]
da[0] represents the least significant bit of the first byte received, that is, the multicast/unicast indicator, and da[47] represents the most significant bit of the last byte received.
If the hash index points to a bit that is set in the hash register then the frame will be matched according to whether the frame is multicast or unicast.
A multicast match will be signaled if the multicast hash enable bit is set, da[0] is logic 1 and the hash index points to a bit set in the hash register.
A unicast match will be signaled if the unicast hash enable bit is set, da[0] is logic 0 and the hash index points to a bit set in the hash register.
To receive all multicast frames, the hash register should be set with all ones and the multicast hash enable bit should be set in the network configuration register.
- Parameters:
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| InstancePtr | is a pointer to the instance to be worked on. |
| AddressPtr | is a pointer to a 6-byte MAC address. |
- Returns:
- XST_SUCCESS if the HASH MAC address was set successfully
- XST_DEVICE_IS_STARTED if the device has not yet been stopped
- XST_INVALID_PARAM if the HASH MAC address passed in does not meet requirement after calculation
- Note:
- Having Aptr be unsigned type prevents the following operations from sign extending.
Set the MDIO clock divisor.
Calculating the divisor:
f[HOSTCLK]
f[MDC] = -----------------
(1 + Divisor) * 2
where f[HOSTCLK] is the bus clock frequency in MHz, and f[MDC] is the MDIO clock frequency in MHz to the PHY. Typically, f[MDC] should not exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster access. Here is the table to show values to generate MDC,
000 : divide pclk by 8 (pclk up to 20 MHz)
001 : divide pclk by 16 (pclk up to 40 MHz)
010 : divide pclk by 32 (pclk up to 80 MHz)
011 : divide pclk by 48 (pclk up to 120 MHz)
100 : divide pclk by 64 (pclk up to 160 MHz)
101 : divide pclk by 96 (pclk up to 240 MHz)
110 : divide pclk by 128 (pclk up to 320 MHz)
111 : divide pclk by 224 (pclk up to 540 MHz)
- Parameters:
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| InstancePtr | is a pointer to the instance to be worked on. |
| Divisor | is the divisor to set. Range is 0b000 to 0b111. |
void XEmacPs_Start |
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XEmacPs * |
InstancePtr |
) |
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Start the Ethernet controller as follows:
- Enable transmitter if XTE_TRANSMIT_ENABLE_OPTION is set
- Enable receiver if XTE_RECEIVER_ENABLE_OPTION is set
- Start the SG DMA send and receive channels and enable the device interrupt
- Parameters:
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| InstancePtr | is a pointer to the instance to be worked on. |
- Returns:
- N/A
- Note:
- Hardware is configured with scatter-gather DMA, the driver expects to start the scatter-gather channels and expects that the user has previously set up the buffer descriptor lists.
This function makes use of internal resources that are shared between the Start, Stop, and Set/ClearOptions functions. So if one task might be setting device options while another is trying to start the device, the user is required to provide protection of this shared data (typically using a semaphore).
This function must not be preempted by an interrupt that may service the device.
void XEmacPs_Stop |
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XEmacPs * |
InstancePtr |
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Gracefully stop the Ethernet MAC as follows:
- Disable all interrupts from this device
- Stop DMA channels
- Disable the tansmitter and receiver
Device options currently in effect are not changed.
This function will disable all interrupts. Default interrupts settings that had been enabled will be restored when XEmacPs_Start() is called.
- Parameters:
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| InstancePtr | is a pointer to the instance to be worked on. |
- Note:
- This function makes use of internal resources that are shared between the Start, Stop, SetOptions, and ClearOptions functions. So if one task might be setting device options while another is trying to start the device, the user is required to provide protection of this shared data (typically using a semaphore).
Stopping the DMA channels causes this function to block until the DMA operation is complete.