iicps v2_2

This is an implementation of IIC driver in the PS block. The device can be either a master or a slave on the IIC bus. This implementation supports both interrupt mode transfer and polled mode transfer. Only 7-bit address is used in the driver, although the hardware also supports 10-bit address.

IIC is a 2-wire serial interface. The master controls the clock, so it can regulate when it wants to send or receive data. The slave is under control of the master, it must respond quickly since it has no control of the clock and must send/receive data as fast or as slow as the master does.

The higher level software must implement a higher layer protocol to inform the slave what to send to the master.

Initialization & Configuration

The XIicPs_Config structure is used by the driver to configure itself. This configuration structure is typically created by the tool-chain based on HW build properties.

To support multiple runtime loading and initialization strategies employed by various operating systems, the driver instance can be initialized in the following way:

• XIicPs_LookupConfig(DeviceId) - Use the device identifier to find the static configuration structure defined in xiicps_g.c. This is setup by the tools. For some operating systems the config structure will be initialized by the software and this call is not needed.

• XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a configuration structure provided by the caller. If running in a system with address translation, the provided virtual memory base address replaces the physical address in the configuration structure.

Multiple Masters

More than one master can exist, bus arbitration is defined in the IIC standard. Lost of arbitration causes arbitration loss interrupt on the device.

Multiple Slaves

Multiple slaves are supported by selecting them with unique addresses. It is up to the system designer to be sure all devices on the IIC bus have unique addresses.

Addressing

The IIC hardware can use 7 or 10 bit addresses. The driver provides the ability to control which address size is sent in messages as a master to a slave device.

FIFO Size The hardware FIFO is 32 bytes deep. The user must know the limitations of other IIC devices on the bus. Some are only able to receive a limited number of bytes in a single transfer.

Data Rates

The data rate is set by values in the control register. The formula for determining the correct register values is: Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))

When the device is configured as a slave, the slck setting controls the sample rate and so must be set to be at least as fast as the fastest scl expected to be seen in the system.

Polled Mode Operation

This driver supports polled mode transfers.

Interrupts

The user must connect the interrupt handler of the driver, XIicPs_InterruptHandler to an interrupt system such that it will be called when an interrupt occurs. This function does not save and restore the processor context such that the user must provide this processing.

The driver handles the following interrupts:

• Transfer complete
• More Data
• Transfer not Acknowledged
• Transfer Time out
• Monitored slave ready - master mode only
• Receive Overflow
• Transmit FIFO overflow
• Receive FIFO underflow
• Arbitration lost

Bus Busy

Bus busy is checked before the setup of a master mode device, to avoid unnecessary arbitration loss interrupt.

RTOS Independence

This driver is intended to be RTOS and processor independent. It works with physical addresses only. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver.

Note:

. Less than FIFO size transfers work for both 100 KHz and 400 KHz. . Larger than FIFO size interrupt-driven transfers are not reliable on busy systems where interrupt latency is high. . Larger than FIFO size interrupt-driven transfers are not reliable for data rate of 400 KHz. . Larger than FIFO size polled mode transfers work reliably.

 MODIFICATION HISTORY:

 Ver   Who     Date     Changes
 ----- ------  -------- -----------------------------------------------
 1.00a drg/jz  01/30/08 First release
 1.00a sdm     09/21/11 Fixed an issue in the XIicPs_SetOptions and
			 XIicPs_ClearOptions where the InstancePtr->Options
			 was not updated correctly.
 			 Updated the InstancePtr->Options in the
			 XIicPs_CfgInitialize by calling XIicPs_GetOptions.
			 Updated the XIicPs_SetupMaster to not check for
			 Bus Busy condition when the Hold Bit is set.
			 Removed some unused variables.
 1.01a sg      03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
			 check for transfer completion is added, which indicates
			 the completion of current transfer.
 1.02a sg	08/29/12 Updated the logic to arrive at the best divisors
			 to achieve I2C clock with minimum error for
			 CR #674195
 1.03a hk  05/04/13 Initialized BestDivA and BestDivB to 0.
			 This is fix for CR#704398 to remove warning.
 2.0   hk  03/07/14 Added check for error status in the while loop that
                    checks for completion.
                    (XIicPs_MasterSendPolled function). CR# 762244, 764875.
                    Limited frequency set when 100KHz or 400KHz is
                    selected. This is a hardware limitation. CR#779290.
 2.1   hk  04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
                    Explicitly reset CR and clear FIFO in Abort function
                    and state the same in the comments. CR# 784254.
                    Fix for CR# 761060 - provision for repeated start.