This is the main header file for Xilinx DisplayPort Receiver Subsystem core.It abstracts Subsystem cores and provides high level API's to application developer.

Core Features

For a full description of DisplayPort Receiver Subsystem core, please see the hardware specification.

Software Initialization & Configuration

The application needs to do following steps in order for preparing the DisplayPort Receiver Subsystem core to be ready.

Call XDpRxSs_LookupConfig using a device ID to find the core configuration.
Call XDpRxSs_CfgInitialize to initialize the device and the driver instance associated with it.

Interrupts

The DisplayPort RX Subsystem driver provides the interrupt handlers

XDpRxSs_DpIntrHandler
XDpRxSs_HdcpIntrHandler
XDpRxSs_TmrCtrIntrHandler, for handling the interrupt from the DisplayPort, optional HDCP and Timer Counter sub-cores respectively. The users of this driver have to register this handler with the interrupt system and provide the callback functions by using XDpRxSs_SetCallBack API.

Virtual Memory

This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.

Threads

This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.

Asserts

Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.

Building the driver

The DisplayPort Receiver Subsystem driver is composed of several source files. This allows the user to build and link only those parts of the driver that are necessary.

MODIFICATION HISTORY:

Ver  Who Date     Changes
---- --- -------- ----------------------------------------------------------
1.00 sha 05/18/15 Initial release.
2.00 sha 10/05/15 Removed HDCP interrupt handler types.
                  Added HDCP and Timer Counter support.