The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO Controller.

The GPIO Controller supports the following features:

4 banks
Masked writes (There are no masked reads)
Bypass mode
Configurable Interrupts (Level/Edge)

This driver is intended to be RTOS and processor independent. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver.

This driver supports all the features listed above, if applicable.

Driver Description

The device driver enables higher layer software (e.g., an application) to communicate to the GPIO.

Interrupts

The driver provides interrupt management functions and an interrupt handler. Users of this driver need to provide callback functions. An interrupt handler example is available with the driver.

Threads

This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.

Asserts

Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.

Building the driver

The XGpioPs driver is composed of several source files. This allows the user to build and link only those parts of the driver that are necessary.

MODIFICATION HISTORY:

Ver   Who  Date     Changes
----- ---- -------- -----------------------------------------------
1.00a sv   01/15/10 First Release
1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
                    XGpioPs_GetMode, XGpioPs_GetModePin as they are not
	      relevant to Zynq device.The interrupts are disabled
	      for output pins on all banks during initialization.
1.02a hk   08/22/13 Added low level reset API
2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
2.2	sk	 10/13/14 Used Pin number in Bank instead of pin number
					  passed to APIs. CR# 822636
3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.