usbps
Xilinx SDK Drivers API Documentation
Data Structures | Macros | Functions
xusbps.h File Reference

Data Structures

struct  XUsbPs_EpOut
 
struct  XUsbPs_EpIn
 
struct  XUsbPs_Endpoint
 
struct  XUsbPs_SetupData
 
struct  XUsbPs_EpSetup
 
struct  XUsbPs_EpConfig
 
struct  XUsbPs_DeviceConfig
 
struct  XUsbPs_Config
 
struct  XUsbPs
 

Macros

#define XUsbPs_GetFrameNum(InstancePtr)   XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET)
 
#define XUsbPs_Start(InstancePtr)   XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
 
#define XUsbPs_Stop(InstancePtr)   XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
 
#define XUsbPs_ForceFS(InstancePtr)
 
#define XUsbPs_StartTimer0(InstancePtr, Interval)
 
#define XUsbPs_StopTimer0(InstancePtr)
 
#define XUsbPs_ReadTimer0(InstancePtr)
 
#define XUsbPs_RemoteWakeup(InstancePtr)
 
#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir)
 
#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir)
 
#define XUsbPs_EpStall(InstancePtr, EpNum, Dir)
 
#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir)
 
#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir)
 
#define XUsbPs_IntrEnable(InstancePtr, IntrMask)   XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
 
#define XUsbPs_IntrDisable(InstancePtr, IntrMask)   XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
 
#define XUsbPs_NakIntrEnable(InstancePtr, NakIntrMask)   XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
 
#define XUsbPs_NakIntrDisable(InstancePtr, NakIntrMask)   XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
 
#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask)
 
#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold)
 
#define XUsbPs_SetSetupTripwire(InstancePtr)
 
#define XUsbPs_ClrSetupTripwire(InstancePtr)
 
#define XUsbPs_SetupTripwireIsSet(InstancePtr)
 
#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits)
 
#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits)
 
System hang prevention Timeout counter value.

This value is used throughout the code to initialize a Timeout counter that is used when hard polling a register.

The ides is to initialize the Timeout counter to a value that is longer than any expected Timeout but short enough so the system will continue to work and report an error while the user is still paying attention. A reasonable Timeout time would be about 10 seconds. The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would run about 10 seconds before a Timeout is detected. For example:

int Timeout = XUSBPS_TIMEOUT_COUNTER; while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET) & XUSBPS_CMD_RST_MASK) && –Timeout) { ; } if (0 == Timeout) { return XST_FAILURE; }

Endpoint Direction (bitmask)

Definitions to be used with Endpoint related function that require a 'Direction' parameter.

NOTE: The direction is always defined from the perspective of the HOST! This means that an IN endpoint on the controller is used for sending data while the OUT endpoint on the controller is used for receiving data.

#define XUSBPS_EP_DIRECTION_IN   0x01
 
#define XUSBPS_EP_DIRECTION_OUT   0x02
 
Endpoint Type

Definitions to be used with Endpoint related functions that require a 'Type' parameter.

#define XUSBPS_EP_TYPE_NONE   0
 
#define XUSBPS_EP_TYPE_BULK   3
 
Field names for status retrieval

Definitions for the XUsbPs_GetStatus() function call 'StatusType' parameter.

#define XUSBPS_EP_STS_ADDRESS   1
 
#define XUSBPS_EP_STS_CONTROLLER_STATE   2
 
USB Default alternate setting
Endpoint event types

Definitions that are used to identify events that occur on endpoints.

Passed to the endpoint event handler functions registered with XUsbPs_EpSetHandler().

#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED   0x01
 
#define XUSBPS_EP_EVENT_DATA_RX   0x02
 
#define XUSBPS_EP_EVENT_DATA_TX   0x03
 

Functions

int XUsbPs_CfgInitialize (XUsbPs *InstancePtr, const XUsbPs_Config *ConfigPtr, u32 BaseAddress)
 
int XUsbPs_ConfigureDevice (XUsbPs *InstancePtr, const XUsbPs_DeviceConfig *CfgPtr)
 
int XUsbPs_Reset (XUsbPs *InstancePtr)
 
void XUsbPs_DeviceReset (XUsbPs *InstancePtr)
 
int XUsbPs_SetDeviceAddress (XUsbPs *InstancePtr, u8 Address)
 
int XUsbPs_Suspend (const XUsbPs *InstancePtr)
 
int XUsbPs_Resume (const XUsbPs *InstancePtr)
 
int XUsbPs_RequestHostResume (const XUsbPs *InstancePtr)
 
int XUsbPs_EpBufferSend (XUsbPs *InstancePtr, u8 EpNum, const u8 *BufferPtr, u32 BufferLen)
 
int XUsbPs_EpBufferSendWithZLT (XUsbPs *InstancePtr, u8 EpNum, const u8 *BufferPtr, u32 BufferLen)
 
int XUsbPs_EpBufferReceive (XUsbPs *InstancePtr, u8 EpNum, u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle)
 
void XUsbPs_EpBufferRelease (u32 Handle)
 
int XUsbPs_EpSetHandler (XUsbPs *InstancePtr, u8 EpNum, u8 Direction, XUsbPs_EpHandlerFunc CallBackFunc, void *CallBackRef)
 
int XUsbPs_EpGetSetupData (XUsbPs *InstancePtr, int EpNum, XUsbPs_SetupData *SetupDataPtr)
 
int XUsbPs_EpPrime (XUsbPs *InstancePtr, u8 EpNum, u8 Direction)
 
int XUsbPs_ReconfigureEp (XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr, int EpNum, unsigned short NewDirection, int DirectionChanged)
 
void XUsbPs_IntrHandler (void *InstancePtr)
 
int XUsbPs_IntrSetHandler (XUsbPs *InstancePtr, XUsbPs_IntrHandlerFunc CallBackFunc, void *CallBackRef, u32 Mask)
 
XUsbPs_Config * XUsbPs_LookupConfig (u16 DeviceId)
 

Macro Definition Documentation

#define XUsbPs_ClrBits (   InstancePtr,
  RegOffset,
  Bits 
)
Value:
XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
RegOffset) & ~(Bits));
XUsbPs_ReadReg
#define XUsbPs_ReadReg(BaseAddress, RegOffset)
This macro reads the given register.
Definition: xusbps_hw.h:504
XUsbPs_WriteReg
#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data)
This macro writes the given register.
Definition: xusbps_hw.h:523

This macro clears the given bits in the register.

Parameters
InstancePtris a pointer to XUsbPs instance of the controller.
RegOffsetis the register offset to be written.
Bitsare the bits to be cleared in the register
Returns
None.
Note
C-style signature: void XUsbPs_ClrBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
#define XUsbPs_ClrSetupTripwire (   InstancePtr)
Value:
XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, \
XUSBPS_CMD_SUTW_MASK)
XUSBPS_CMD_OFFSET
#define XUSBPS_CMD_OFFSET
Configuration.
Definition: xusbps_hw.h:120
XUsbPs_ClrBits
#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits)
This macro clears the given bits in the register.
Definition: xusbps.h:1002
XUSBPS_CMD_SUTW_MASK
#define XUSBPS_CMD_SUTW_MASK
Setup TripWire.
Definition: xusbps_hw.h:208

This macro clears the Tripwire bit in the USB command register.

Parameters
InstancePtris a pointer to XUsbPs instance of the controller.
Note
C-style signature: void XUsbPs_ClrTripwire(XUsbPs *InstancePtr)

Referenced by XUsbPs_EpGetSetupData().

#define XUsbPs_EpDisable (   InstancePtr,
  EpNum,
  Dir 
)
Value:
XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
XUSBPS_EP_DIRECTION_IN
#define XUSBPS_EP_DIRECTION_IN
Endpoint direction IN.
Definition: xusbps.h:237
XUsbPs_ClrBits
#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits)
This macro clears the given bits in the register.
Definition: xusbps.h:1002
XUSBPS_EP_DIRECTION_OUT
#define XUSBPS_EP_DIRECTION_OUT
Endpoint direction OUT.
Definition: xusbps.h:238
XUSBPS_EPCR_RXE_MASK
#define XUSBPS_EPCR_RXE_MASK
Transmit enable.
Definition: xusbps_hw.h:192
XUSBPS_EPCR_TXE_MASK
#define XUSBPS_EPCR_TXE_MASK
Transmit enable - TX.
Definition: xusbps_hw.h:182

This macro disables the given endpoint for the given direction.

Parameters
InstancePtris a pointer to the XUsbPs instance of the controller.
EpNumis the number of the endpoint to disable.
Diris the direction of the endpoint (bitfield):
  • XUSBPS_EP_DIRECTION_OUT
  • XUSBPS_EP_DIRECTION_IN
Note
C-style signature: void XUsbPs_EpDisable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
#define XUsbPs_EpEnable (   InstancePtr,
  EpNum,
  Dir 
)
Value:
XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
XUSBPS_EP_DIRECTION_IN
#define XUSBPS_EP_DIRECTION_IN
Endpoint direction IN.
Definition: xusbps.h:237
XUsbPs_SetBits
#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits)
This macro sets the given bit mask in the register.
Definition: xusbps.h:980
XUSBPS_EP_DIRECTION_OUT
#define XUSBPS_EP_DIRECTION_OUT
Endpoint direction OUT.
Definition: xusbps.h:238
XUSBPS_EPCR_RXE_MASK
#define XUSBPS_EPCR_RXE_MASK
Transmit enable.
Definition: xusbps_hw.h:192
XUSBPS_EPCR_TXE_MASK
#define XUSBPS_EPCR_TXE_MASK
Transmit enable - TX.
Definition: xusbps_hw.h:182

This macro enables the given endpoint for the given direction.

Parameters
InstancePtris a pointer to the XUsbPs instance of the controller.
EpNumis number of the endpoint to enable.
Diris direction of the endpoint (bitfield):
  • XUSBPS_EP_DIRECTION_OUT
  • XUSBPS_EP_DIRECTION_IN
Note
C-style signature: void XUsbPs_EpEnable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
#define XUsbPs_EpFlush (   InstancePtr,
  EpNum,
  Dir 
)
Value:
XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET, \
EpNum << ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \
XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT)) \
XUSBPS_EPFLUSH_OFFSET
#define XUSBPS_EPFLUSH_OFFSET
Endpoint Flush.
Definition: xusbps_hw.h:145
XUsbPs_SetBits
#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits)
This macro sets the given bit mask in the register.
Definition: xusbps.h:980
XUSBPS_EP_DIRECTION_OUT
#define XUSBPS_EP_DIRECTION_OUT
Endpoint direction OUT.
Definition: xusbps.h:238

This macro flush an endpoint upon interface disable.

Parameters
InstancePtris a pointer to the XUsbPs instance of the controller.
EpNumis the number of the endpoint to flush.
Diris the direction of the endpoint (bitfield):
  • XUSBPS_EP_DIRECTION_OUT
  • XUSBPS_EP_DIRECTION_IN
Note
C-style signature: void XUsbPs_EpFlush(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
#define XUsbPs_EpStall (   InstancePtr,
  EpNum,
  Dir 
)
Value:
XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
XUSBPS_EPCR_RXS_MASK
#define XUSBPS_EPCR_RXS_MASK
Stall RX endpoint.
Definition: xusbps_hw.h:191
XUSBPS_EP_DIRECTION_IN
#define XUSBPS_EP_DIRECTION_IN
Endpoint direction IN.
Definition: xusbps.h:237
XUSBPS_EPCR_TXS_MASK
#define XUSBPS_EPCR_TXS_MASK
Stall TX endpoint.
Definition: xusbps_hw.h:181
XUsbPs_SetBits
#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits)
This macro sets the given bit mask in the register.
Definition: xusbps.h:980
XUSBPS_EP_DIRECTION_OUT
#define XUSBPS_EP_DIRECTION_OUT
Endpoint direction OUT.
Definition: xusbps.h:238

This macro stalls the given endpoint for the given direction, and flush the buffers.

Parameters
InstancePtris a pointer to the XUsbPs instance of the controller.
EpNumis number of the endpoint to stall.
Diris the direction of the endpoint (bitfield):
  • XUSBPS_EP_DIRECTION_OUT
  • XUSBPS_EP_DIRECTION_IN
Note
C-style signature: void XUsbPs_EpStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
#define XUsbPs_EpUnStall (   InstancePtr,
  EpNum,
  Dir 
)
Value:
XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
XUSBPS_EPCR_RXS_MASK
#define XUSBPS_EPCR_RXS_MASK
Stall RX endpoint.
Definition: xusbps_hw.h:191
XUSBPS_EP_DIRECTION_IN
#define XUSBPS_EP_DIRECTION_IN
Endpoint direction IN.
Definition: xusbps.h:237
XUsbPs_ClrBits
#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits)
This macro clears the given bits in the register.
Definition: xusbps.h:1002
XUSBPS_EPCR_TXS_MASK
#define XUSBPS_EPCR_TXS_MASK
Stall TX endpoint.
Definition: xusbps_hw.h:181
XUSBPS_EP_DIRECTION_OUT
#define XUSBPS_EP_DIRECTION_OUT
Endpoint direction OUT.
Definition: xusbps.h:238

This macro unstalls the given endpoint for the given direction.

Parameters
InstancePtris a pointer to the XUsbPs instance of the controller.
EpNumis the Number of the endpoint to unstall.
Diris the Direction of the endpoint (bitfield):
  • XUSBPS_EP_DIRECTION_OUT
  • XUSBPS_EP_DIRECTION_IN
Note
C-style signature: void XUsbPs_EpUnStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
#define XUsbPs_ForceFS (   InstancePtr)
Value:
XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
XUSBPS_PORTSCR_PFSC_MASK)
XUSBPS_PORTSCR_PFSC_MASK
#define XUSBPS_PORTSCR_PFSC_MASK
Port Force Full Speed Connect.
Definition: xusbps_hw.h:393
XUsbPs_SetBits
#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits)
This macro sets the given bit mask in the register.
Definition: xusbps.h:980
XUSBPS_PORTSCR1_OFFSET
#define XUSBPS_PORTSCR1_OFFSET
Port Control/Status 1.
Definition: xusbps_hw.h:134

This macro forces the USB engine to be in Full Speed (FS) mode.

Parameters
InstancePtris a pointer to the XUsbPs instance of the controller.
Note
C-style signature: void XUsbPs_ForceFS(XUsbPs *InstancePtr)
#define XUsbPs_GetFrameNum (   InstancePtr)    XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET)

This macro returns the current frame number.

Parameters
InstancePtris a pointer to the XUsbPs instance of the controller.
Returns
The current frame number.
Note
C-style signature: u32 XUsbPs_GetFrameNum(const XUsbPs *InstancePtr)
#define XUsbPs_IntrDisable (   InstancePtr,
  IntrMask 
)    XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)

This function disables the interrupts defined by the bit mask.

Parameters
InstancePtris a pointer to XUsbPs instance of the controller.
IntrMaskis a Bit mask of interrupts to be disabled.
Note
C-style signature: void XUsbPs_IntrDisable(XUsbPs *InstancePtr, u32 IntrMask)
#define XUsbPs_IntrEnable (   InstancePtr,
  IntrMask 
)    XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)

This macro enables the interrupts defined by the bit mask.

Parameters
InstancePtris a pointer to XUsbPs instance of the controller.
IntrMaskis the Bit mask of interrupts to be enabled.
Note
C-style signature: void XUsbPs_IntrEnable(XUsbPs *InstancePtr, u32 IntrMask)
#define XUsbPs_NakIntrClear (   InstancePtr,
  NakIntrMask 
)
Value:
XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XUSBPS_EPNAKISR_OFFSET, NakIntrMask)
XUSBPS_EPNAKISR_OFFSET
#define XUSBPS_EPNAKISR_OFFSET
Endpoint NAK IRQ Status.
Definition: xusbps_hw.h:132
XUsbPs_WriteReg
#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data)
This macro writes the given register.
Definition: xusbps_hw.h:523

This function clears the endpoint NAK interrupts status defined by the bit mask.

Parameters
InstancePtris a pointer to XUsbPs instance of the controller.
NakIntrMaskis the Bit mask of endpoint NAK interrupts to be cleared.
Note
C-style signature: void XUsbPs_NakIntrClear(XUsbPs *InstancePtr, u32 NakIntrMask)
#define XUsbPs_NakIntrDisable (   InstancePtr,
  NakIntrMask 
)    XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)

This macro disables the endpoint NAK interrupts defined by the bit mask.

Parameters
InstancePtris a pointer to XUsbPs instance of the controller.
NakIntrMaskis a Bit mask of endpoint NAK interrupts to be disabled.
Note
C-style signature: void XUsbPs_NakIntrDisable(XUsbPs *InstancePtr, u32 NakIntrMask)
#define XUsbPs_NakIntrEnable (   InstancePtr,
  NakIntrMask 
)    XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)

This macro enables the endpoint NAK interrupts defined by the bit mask.

Parameters
InstancePtris a pointer to XUsbPs instance of the controller.
NakIntrMaskis the Bit mask of endpoint NAK interrupts to be enabled.
Note
C-style signature: void XUsbPs_NakIntrEnable(XUsbPs *InstancePtr, u32 NakIntrMask)
#define XUsbPs_ReadTimer0 (   InstancePtr)
Value:
XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XUSBPS_TIMER0_CTL_OFFSET) & \
XUSBPS_TIMER_COUNTER_MASK
XUsbPs_ReadReg
#define XUsbPs_ReadReg(BaseAddress, RegOffset)
This macro reads the given register.
Definition: xusbps_hw.h:504

This macro reads Timer 0.

Parameters
InstancePtris a pointer to XUsbPs instance of the controller.
Note
C-style signature: void XUsbPs_ReadTimer0(XUsbPs *InstancePtr)
#define XUsbPs_RemoteWakeup (   InstancePtr)
Value:
XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
XUSBPS_PORTSCR_FPR_MASK)
XUSBPS_PORTSCR_FPR_MASK
#define XUSBPS_PORTSCR_FPR_MASK
Force Port Resume.
Definition: xusbps_hw.h:378
XUsbPs_SetBits
#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits)
This macro sets the given bit mask in the register.
Definition: xusbps.h:980
XUSBPS_PORTSCR1_OFFSET
#define XUSBPS_PORTSCR1_OFFSET
Port Control/Status 1.
Definition: xusbps_hw.h:134

This macro force remote wakeup on host.

Parameters
InstancePtris a pointer to XUsbPs instance of the controller.
Note
C-style signature: void XUsbPs_RemoteWakeup(XUsbPs *InstancePtr)
#define XUsbPs_SetBits (   InstancePtr,
  RegOffset,
  Bits 
)
Value:
XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
RegOffset) | (Bits));
XUsbPs_ReadReg
#define XUsbPs_ReadReg(BaseAddress, RegOffset)
This macro reads the given register.
Definition: xusbps_hw.h:504
XUsbPs_WriteReg
#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data)
This macro writes the given register.
Definition: xusbps_hw.h:523

This macro sets the given bit mask in the register.

Parameters
InstancePtris a pointer to XUsbPs instance of the controller.
RegOffsetis the register offset to be written.
Bitsis the Bits to be set in the register
Returns
None.
Note
C-style signature: void XUsbPs_SetBits(u32 BaseAddress, u32 RegOffset, u32 Bits)

Referenced by XUsbPs_ConfigureDevice().

#define XUsbPs_SetIntrThreshold (   InstancePtr,
  Threshold 
)
Value:
XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XUSBPS_CMD_OFFSET, (Threshold))\
XUSBPS_CMD_OFFSET
#define XUSBPS_CMD_OFFSET
Configuration.
Definition: xusbps_hw.h:120
XUsbPs_WriteReg
#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data)
This macro writes the given register.
Definition: xusbps_hw.h:523

This macro sets the Interrupt Threshold value in the control register.

Parameters
InstancePtris a pointer to XUsbPs instance of the controller.
Thresholdis the Interrupt threshold to be set. Allowed values:
  • XUSBPS_CMD_ITHRESHOLD_0 - Immediate interrupt
  • XUSBPS_CMD_ITHRESHOLD_1 - 1 Frame
  • XUSBPS_CMD_ITHRESHOLD_2 - 2 Frames
  • XUSBPS_CMD_ITHRESHOLD_4 - 4 Frames
  • XUSBPS_CMD_ITHRESHOLD_8 - 8 Frames
  • XUSBPS_CMD_ITHRESHOLD_16 - 16 Frames
  • XUSBPS_CMD_ITHRESHOLD_32 - 32 Frames
  • XUSBPS_CMD_ITHRESHOLD_64 - 64 Frames
Note
C-style signature: void XUsbPs_SetIntrThreshold(XUsbPs *InstancePtr, u8 Threshold)
#define XUsbPs_SetSetupTripwire (   InstancePtr)
Value:
XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \
XUSBPS_CMD_SUTW_MASK)
XUSBPS_CMD_OFFSET
#define XUSBPS_CMD_OFFSET
Configuration.
Definition: xusbps_hw.h:120
XUsbPs_SetBits
#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits)
This macro sets the given bit mask in the register.
Definition: xusbps.h:980
XUSBPS_CMD_SUTW_MASK
#define XUSBPS_CMD_SUTW_MASK
Setup TripWire.
Definition: xusbps_hw.h:208

This macro sets the Tripwire bit in the USB command register.

Parameters
InstancePtris a pointer to XUsbPs instance of the controller.
Note
C-style signature: void XUsbPs_SetTripwire(XUsbPs *InstancePtr)

Referenced by XUsbPs_EpGetSetupData().

#define XUsbPs_SetupTripwireIsSet (   InstancePtr)
Value:
(XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XUSBPS_CMD_OFFSET) & \
XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE)
XUSBPS_CMD_OFFSET
#define XUSBPS_CMD_OFFSET
Configuration.
Definition: xusbps_hw.h:120
XUsbPs_ReadReg
#define XUsbPs_ReadReg(BaseAddress, RegOffset)
This macro reads the given register.
Definition: xusbps_hw.h:504
XUSBPS_CMD_SUTW_MASK
#define XUSBPS_CMD_SUTW_MASK
Setup TripWire.
Definition: xusbps_hw.h:208

This macro checks if the Tripwire bit in the USB command register is set.

Parameters
InstancePtris a pointer to XUsbPs instance of the controller.
Returns
  • TRUE: The tripwire bit is still set.
  • FALSE: The tripwire bit has been cleared.
Note
C-style signature: int XUsbPs_TripwireIsSet(XUsbPs *InstancePtr)

Referenced by XUsbPs_EpGetSetupData().

#define XUsbPs_Start (   InstancePtr)    XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)

This macro starts the USB engine.

Parameters
InstancePtris a pointer to the XUsbPs instance of the controller.
Note
C-style signature: void XUsbPs_Start(XUsbPs *InstancePtr)
#define XUsbPs_StartTimer0 (   InstancePtr,
  Interval 
)
Value:
{ \
XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XUSBPS_TIMER0_LD_OFFSET, (Interval)); \
XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
XUSBPS_TIMER_RUN_MASK | \
XUSBPS_TIMER_RESET_MASK | \
XUSBPS_TIMER_REPEAT_MASK); \
} \
XUsbPs_SetBits
#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits)
This macro sets the given bit mask in the register.
Definition: xusbps.h:980
XUsbPs_WriteReg
#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data)
This macro writes the given register.
Definition: xusbps_hw.h:523

This macro starts the USB Timer 0, with repeat option for period of one second.

Parameters
InstancePtris a pointer to XUsbPs instance of the controller.
Intervalis the interval for Timer0 to generate an interrupt
Note
C-style signature: void XUsbPs_StartTimer0(XUsbPs *InstancePtr, u32 Interval)
#define XUsbPs_Stop (   InstancePtr)    XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)

This macro stops the USB engine.

Parameters
InstancePtris a pointer to the XUsbPs instance of the controller.
Note
C-style signature: void XUsbPs_Stop(XUsbPs *InstancePtr)

Referenced by XUsbPs_DeviceReset().

#define XUsbPs_StopTimer0 (   InstancePtr)
Value:
XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
XUSBPS_TIMER_RUN_MASK)
XUsbPs_ClrBits
#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits)
This macro clears the given bits in the register.
Definition: xusbps.h:1002

This macro stops Timer 0.

Parameters
InstancePtris a pointer to XUsbPs instance of the controller.
Note
C-style signature: void XUsbPs_StopTimer0(XUsbPs *InstancePtr)

Function Documentation

int XUsbPs_BusReset ( XUsbPs *  InstancePtr)

DEVICE mode specific functions.