MODIFICATION HISTORY:
Ver Who Date Changes ----- --- -------- --------------------------------------------- 1.00a hvm 02/07/11 First release 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for source/destination to the XDcfg_InitiateDma, XDcfg_Transfer APIs is words (32 bit) and not bytes. Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs to add information that 2 LSBs of the Source/Destination address when equal to 2’b01 indicate the last DMA command of an overall transfer. Updated the XDcfg_Transfer function to use the Destination Address passed to this API for secure transfers instead of using 0xFFFFFFFF for CR 662197. This issue was resulting in the failure of secure transfers of non-bitstream images. 2.01a nm 08/27/12 Updated the XDcfg_Transfer API to clear the QUARTER_PCAP_RATE_EN bit in the control register for non secure writes for CR 675543. 2.02a nm 01/31/13 Fixed CR# 679335. Added Setting and Clearing the internal PCAP loopback. Removed code for enabling/disabling AES engine as BootROM locks down this setting. Fixed CR# 681976. Skip Checking the PCFG_INIT in case of non-secure DMA loopback. Fixed CR# 699558. XDcfg_Transfer fails to transfer data in loopback mode. 2.03a nm 04/19/13 Fixed CR# 703728. Updated the register definitions as per the latest TRM version UG585 (v1.4) November 16, 2012. 3.0 kpc 21/02/14 Implemented new function XDcfg_ClearControlRegister
#include "xdevcfg.h"
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int | XDcfg_CfgInitialize (XDcfg *InstancePtr, XDcfg_Config *ConfigPtr, u32 EffectiveAddress) |
void | XDcfg_EnablePCAP (XDcfg *InstancePtr) |
void | XDcfg_DisablePCAP (XDcfg *InstancePtr) |
void | XDcfg_SetControlRegister (XDcfg *InstancePtr, u32 Mask) |
void | XDcfg_ClearControlRegister (XDcfg *InstancePtr, u32 Mask) |
u32 | XDcfg_GetControlRegister (XDcfg *InstancePtr) |
void | XDcfg_SetLockRegister (XDcfg *InstancePtr, u32 Data) |
u32 | XDcfg_GetLockRegister (XDcfg *InstancePtr) |
void | XDcfg_SetConfigRegister (XDcfg *InstancePtr, u32 Data) |
u32 | XDcfg_GetConfigRegister (XDcfg *InstancePtr) |
void | XDcfg_SetStatusRegister (XDcfg *InstancePtr, u32 Data) |
u32 | XDcfg_GetStatusRegister (XDcfg *InstancePtr) |
void | XDcfg_SetRomShadowRegister (XDcfg *InstancePtr, u32 Data) |
u32 | XDcfg_GetSoftwareIdRegister (XDcfg *InstancePtr) |
void | XDcfg_SetMiscControlRegister (XDcfg *InstancePtr, u32 Mask) |
u32 | XDcfg_GetMiscControlRegister (XDcfg *InstancePtr) |
u32 | XDcfg_IsDmaBusy (XDcfg *InstancePtr) |
void | XDcfg_InitiateDma (XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, u32 SrcWordLength, u32 DestWordLength) |
u32 | XDcfg_Transfer (XDcfg *InstancePtr, void *SourcePtr, u32 SrcWordLength, void *DestPtr, u32 DestWordLength, u32 TransferType) |
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Initialize the Device Config Interface driver. This function must be called before other functions of the driver are called.
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The function Clears the specified bit positions of the Control Register.
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The functions disables the PCAP interface by clearing the PCAP mode bit in the control register.
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The functions enables the PCAP interface by setting the PCAP mode bit in the control register.
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The function reads the contents of the Configuration Register with the given value.
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The function reads the contents of the Control Register.
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The function reads the contents of the Lock Register.
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The function reads the contents of the Miscellaneous Control Register.
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The function reads the contents of the Software ID Register.
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The function reads the contents of the Status Register.
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This function initiates the DMA transfer.
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This function checks if DMA command queue is full.
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The function sets the contents of the Configuration Register with the given value.
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The function sets the contents of the Control Register.
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The function sets the contents of the Lock Register. These bits can only be set to a 1. They will be cleared after a Power On Reset.
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The function sets the bit mask for the feature in Miscellaneous Control Register.
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The function sets the contents of the ROM Shadow Control Register.
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The function sets the contents of the Status Register.
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This function starts the DMA transfer. This function only starts the operation and returns before the operation may be completed. If the interrupt is enabled, an interrupt will be generated when the operation is completed, otherwise it is necessary to poll the Status register to determine when it is completed. It is the responsibility of the caller to determine when the operation is completed by handling the generated interrupt or polling the Status Register.
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