embeddedsw/XilinxProcessorIPLib
Andrei-Liviu Simion 0194e3fc17 video_common: Fixed pixel clock calculation for interlaced modes.
In interlaced mode, the vertical total lines for frames 0 and 1 may not
necessarily be equal (off by 1). The pixel clock calculation needs to take this
into account by taking their average.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:34:48 +05:30
..
drivers video_common: Fixed pixel clock calculation for interlaced modes. 2015-04-26 10:34:48 +05:30