24e482ef1a
This patch modifies scugic dirver for misrac rules. Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
712 lines
23 KiB
C
Executable file
712 lines
23 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xscugic.c
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*
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* Contains required functions for the XScuGic driver for the Interrupt
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* Controller. See xscugic.h for a detailed description of the driver.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- --------------------------------------------------------
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* 1.00a drg 01/19/10 First release
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* 1.01a sdm 11/09/11 Changes are made in function XScuGic_CfgInitialize. Since
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* "Config" entry is now made as pointer in the XScuGic
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* structure, necessary changes are made.
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* The HandlerTable can now be populated through the low
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* level routine XScuGic_RegisterHandler added in this
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* release. Hence necessary checks are added not to
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* overwrite the HandlerTable entriesin function
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* XScuGic_CfgInitialize.
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* 1.03a srt 02/27/13 Added APIs
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* - XScuGic_SetPriTrigTypeByDistAddr()
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* - XScuGic_GetPriTrigTypeByDistAddr()
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* Removed Offset calculation macros, defined in _hw.h
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* (CR 702687)
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* Added support to direct interrupts to the appropriate CPU. Earlier
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* interrupts were directed to CPU1 (hard coded). Now depending
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* upon the CPU selected by the user (xparameters.h), interrupts
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* will be directed to the relevant CPU. This fixes CR 699688.
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*
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* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
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* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
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* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
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* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
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* This is fix for CR#705621.
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* 1.06a asa 16/11/13 Fix for CR#749178. Assignment for EffectiveAddr
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* in function XScuGic_CfgInitialize is removed as it was
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* a bug.
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*
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* </pre>
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xscugic.h"
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#include "xparameters.h"
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Variable Definitions *****************************/
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/************************** Function Prototypes ******************************/
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static void StubHandler(void *CallBackRef);
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/*****************************************************************************/
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/**
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*
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* DistributorInit initializes the distributor of the GIC. The
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* initialization entails:
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*
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* - Write the trigger mode, priority and target CPU
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* - All interrupt sources are disabled
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* - Enable the distributor
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*
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* @param InstancePtr is a pointer to the XScuGic instance.
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* @param CpuID is the Cpu ID to be initialized.
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*
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* @return None
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*
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* @note None.
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*
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******************************************************************************/
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static void DistributorInit(XScuGic *InstancePtr, u32 CpuID)
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{
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u32 Int_Id;
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u32 LocalCpuID = CpuID;
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#if USE_AMP==1
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#warning "Building GIC for AMP"
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/*
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* The distrubutor should not be initialized by FreeRTOS in the case of
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* AMP -- it is assumed that Linux is the master of this device in that
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* case.
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*/
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return;
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#endif
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Xil_AssertVoid(InstancePtr != NULL);
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XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
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/*
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* Set the security domains in the int_security registers for
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* non-secure interrupts
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* All are secure, so leave at the default. Set to 1 for non-secure
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* interrupts.
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*/
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/*
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* For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
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*/
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/*
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* 1. The trigger mode in the int_config register
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* Only write to the SPI interrupts, so start at 32
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*/
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for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id=Int_Id+16U) {
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/*
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* Each INT_ID uses two bits, or 16 INT_ID per register
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* Set them all to be level sensitive, active HIGH.
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*/
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XScuGic_DistWriteReg(InstancePtr,
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XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
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0U);
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}
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#define DEFAULT_PRIORITY 0xa0a0a0a0U
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for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id=Int_Id+4U) {
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/*
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* 2. The priority using int the priority_level register
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* The priority_level and spi_target registers use one byte per
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* INT_ID.
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* Write a default value that can be changed elsewhere.
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*/
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XScuGic_DistWriteReg(InstancePtr,
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XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
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DEFAULT_PRIORITY);
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}
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for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
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/*
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* 3. The CPU interface in the spi_target register
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* Only write to the SPI interrupts, so start at 32
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*/
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LocalCpuID |= LocalCpuID << 8U;
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LocalCpuID |= LocalCpuID << 16U;
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XScuGic_DistWriteReg(InstancePtr,
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XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
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LocalCpuID);
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}
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for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+32U) {
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/*
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* 4. Enable the SPI using the enable_set register. Leave all
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* disabled for now.
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*/
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XScuGic_DistWriteReg(InstancePtr,
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XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, Int_Id),
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0xFFFFFFFFU);
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}
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XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET,
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XSCUGIC_EN_INT_MASK);
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}
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/*****************************************************************************/
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/**
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*
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* CPUInitialize initializes the CPU Interface of the GIC. The initialization entails:
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*
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* - Set the priority of the CPU
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* - Enable the CPU interface
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*
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* @param InstancePtr is a pointer to the XScuGic instance.
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*
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* @return None
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*
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* @note None.
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*
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******************************************************************************/
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static void CPUInitialize(XScuGic *InstancePtr)
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{
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/*
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* Program the priority mask of the CPU using the Priority mask register
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*/
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XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_CPU_PRIOR_OFFSET, 0xF0U);
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/*
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* If the CPU operates in both security domains, set parameters in the
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* control_s register.
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* 1. Set FIQen=1 to use FIQ for secure interrupts,
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* 2. Program the AckCtl bit
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* 3. Program the SBPR bit to select the binary pointer behavior
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* 4. Set EnableS = 1 to enable secure interrupts
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* 5. Set EnbleNS = 1 to enable non secure interrupts
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*/
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/*
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* If the CPU operates only in the secure domain, setup the
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* control_s register.
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* 1. Set FIQen=1,
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* 2. Set EnableS=1, to enable the CPU interface to signal secure interrupts.
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* Only enable the IRQ output unless secure interrupts are needed.
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*/
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XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_CONTROL_OFFSET, 0x07U);
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}
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/*****************************************************************************/
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/**
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*
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* CfgInitialize a specific interrupt controller instance/driver. The
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* initialization entails:
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*
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* - Initialize fields of the XScuGic structure
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* - Initial vector table with stub function calls
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* - All interrupt sources are disabled
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*
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* @param InstancePtr is a pointer to the XScuGic instance.
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* @param ConfigPtr is a pointer to a config table for the particular
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* device this driver is associated with.
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* @param EffectiveAddr is the device base address in the virtual memory
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* address space. The caller is responsible for keeping the address
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* mapping from EffectiveAddr to the device physical base address
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* unchanged once this function is invoked. Unexpected errors may
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* occur if the address mapping changes after this function is
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* called. If address translation is not used, use
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* Config->BaseAddress for this parameters, passing the physical
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* address instead.
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*
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* @return
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* - XST_SUCCESS if initialization was successful
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*
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* @note None.
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*
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******************************************************************************/
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s32 XScuGic_CfgInitialize(XScuGic *InstancePtr,
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XScuGic_Config *ConfigPtr,
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u32 EffectiveAddr)
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{
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u32 Int_Id;
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u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1;
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(void) EffectiveAddr;
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(ConfigPtr != NULL);
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if(InstancePtr->IsReady != XIL_COMPONENT_IS_READY) {
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InstancePtr->IsReady = 0;
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InstancePtr->Config = ConfigPtr;
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for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id++) {
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/*
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* Initalize the handler to point to a stub to handle an
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* interrupt which has not been connected to a handler. Only
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* initialize it if the handler is 0 which means it was not
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* initialized statically by the tools/user. Set the callback
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* reference to this instance so that unhandled interrupts
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* can be tracked.
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*/
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if ((InstancePtr->Config->HandlerTable[Int_Id].Handler == NULL)) {
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InstancePtr->Config->HandlerTable[Int_Id].Handler =
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StubHandler;
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}
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InstancePtr->Config->HandlerTable[Int_Id].CallBackRef =
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InstancePtr;
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}
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DistributorInit(InstancePtr, Cpu_Id);
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CPUInitialize(InstancePtr);
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InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
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}
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return XST_SUCCESS;
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}
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/*****************************************************************************/
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/**
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*
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* Makes the connection between the Int_Id of the interrupt source and the
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* associated handler that is to run when the interrupt is recognized. The
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* argument provided in this call as the Callbackref is used as the argument
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* for the handler when it is called.
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*
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* @param InstancePtr is a pointer to the XScuGic instance.
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* @param Int_Id contains the ID of the interrupt source and should be
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* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
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* @param Handler to the handler for that interrupt.
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* @param CallBackRef is the callback reference, usually the instance
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* pointer of the connecting driver.
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*
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* @return
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*
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* - XST_SUCCESS if the handler was connected correctly.
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*
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* @note
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*
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* WARNING: The handler provided as an argument will overwrite any handler
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* that was previously connected.
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*
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****************************************************************************/
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s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
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Xil_InterruptHandler Handler, void *CallBackRef)
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{
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/*
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* Assert the arguments
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*/
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
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Xil_AssertNonvoid(Handler != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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/*
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* The Int_Id is used as an index into the table to select the proper
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* handler
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*/
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InstancePtr->Config->HandlerTable[Int_Id].Handler = Handler;
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InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = CallBackRef;
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return XST_SUCCESS;
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}
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/*****************************************************************************/
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/**
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*
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* Updates the interrupt table with the Null Handler and NULL arguments at the
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* location pointed at by the Int_Id. This effectively disconnects that interrupt
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* source from any handler. The interrupt is disabled also.
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*
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* @param InstancePtr is a pointer to the XScuGic instance to be worked on.
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* @param Int_Id contains the ID of the interrupt source and should
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* be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
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*
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* @return None.
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*
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* @note None.
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*
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****************************************************************************/
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void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id)
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{
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u32 Mask;
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/*
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* Assert the arguments
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*/
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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/*
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* The Int_Id is used to create the appropriate mask for the
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* desired bit position. Int_Id currently limited to 0 - 31
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*/
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Mask = 0x00000001U << (Int_Id % 32U);
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/*
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* Disable the interrupt such that it won't occur while disconnecting
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* the handler, only disable the specified interrupt id without modifying
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* the other interrupt ids
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*/
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XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
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((Int_Id / 32U) * 4U), Mask);
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/*
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* Disconnect the handler and connect a stub, the callback reference
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* must be set to this instance to allow unhandled interrupts to be
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* tracked
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*/
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InstancePtr->Config->HandlerTable[Int_Id].Handler = StubHandler;
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InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr;
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}
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/*****************************************************************************/
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/**
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*
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* Enables the interrupt source provided as the argument Int_Id. Any pending
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* interrupt condition for the specified Int_Id will occur after this function is
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* called.
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*
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* @param InstancePtr is a pointer to the XScuGic instance.
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* @param Int_Id contains the ID of the interrupt source and should be
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* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
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*
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* @return None.
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*
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* @note None.
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*
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****************************************************************************/
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void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id)
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{
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u32 Mask;
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/*
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* Assert the arguments
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*/
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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/*
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* The Int_Id is used to create the appropriate mask for the
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* desired bit position. Int_Id currently limited to 0 - 31
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*/
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Mask = 0x00000001U << (Int_Id % 32U);
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/*
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* Enable the selected interrupt source by setting the
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* corresponding bit in the Enable Set register.
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*/
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XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_ENABLE_SET_OFFSET +
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((Int_Id / 32U) * 4U), Mask);
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}
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/*****************************************************************************/
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/**
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*
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* Disables the interrupt source provided as the argument Int_Id such that the
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* interrupt controller will not cause interrupts for the specified Int_Id. The
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* interrupt controller will continue to hold an interrupt condition for the
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* Int_Id, but will not cause an interrupt.
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*
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* @param InstancePtr is a pointer to the XScuGic instance.
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* @param Int_Id contains the ID of the interrupt source and should be
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* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
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*
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* @return None.
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*
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* @note None.
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*
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****************************************************************************/
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void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id)
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{
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u32 Mask;
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/*
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* Assert the arguments
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*/
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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/*
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* The Int_Id is used to create the appropriate mask for the
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* desired bit position. Int_Id currently limited to 0 - 31
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*/
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Mask = 0x00000001U << (Int_Id % 32U);
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/*
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* Disable the selected interrupt source by setting the
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* corresponding bit in the IDR.
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*/
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XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
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((Int_Id / 32U) * 4U), Mask);
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}
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/*****************************************************************************/
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/**
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*
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* Allows software to simulate an interrupt in the interrupt controller. This
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* function will only be successful when the interrupt controller has been
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* started in simulation mode. A simulated interrupt allows the interrupt
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* controller to be tested without any device to drive an interrupt input
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* signal into it.
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*
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* @param InstancePtr is a pointer to the XScuGic instance.
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* @param Int_Id is the software interrupt ID to simulate an interrupt.
|
|
* @param Cpu_Id is the list of CPUs to send the interrupt.
|
|
*
|
|
* @return
|
|
*
|
|
* XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be
|
|
* simulated
|
|
*
|
|
* @note None.
|
|
*
|
|
******************************************************************************/
|
|
s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id)
|
|
{
|
|
u32 Mask;
|
|
|
|
/*
|
|
* Assert the arguments
|
|
*/
|
|
Xil_AssertNonvoid(InstancePtr != NULL);
|
|
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
|
Xil_AssertNonvoid(Int_Id <= 15U) ;
|
|
Xil_AssertNonvoid(Cpu_Id <= 255U) ;
|
|
|
|
|
|
/*
|
|
* The Int_Id is used to create the appropriate mask for the
|
|
* desired interrupt. Int_Id currently limited to 0 - 15
|
|
* Use the target list for the Cpu ID.
|
|
*/
|
|
Mask = ((Cpu_Id << 16U) | Int_Id) &
|
|
(XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK);
|
|
|
|
/*
|
|
* Write to the Software interrupt trigger register. Use the appropriate
|
|
* CPU Int_Id.
|
|
*/
|
|
XScuGic_DistWriteReg(InstancePtr, XSCUGIC_SFI_TRIG_OFFSET, Mask);
|
|
|
|
/* Indicate the interrupt was successfully simulated */
|
|
|
|
return XST_SUCCESS;
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
*
|
|
* A stub for the asynchronous callback. The stub is here in case the upper
|
|
* layers forget to set the handler.
|
|
*
|
|
* @param CallBackRef is a pointer to the upper layer callback reference
|
|
*
|
|
* @return None.
|
|
*
|
|
* @note None.
|
|
*
|
|
******************************************************************************/
|
|
static void StubHandler(void *CallBackRef) {
|
|
/*
|
|
* verify that the inputs are valid
|
|
*/
|
|
Xil_AssertVoid(CallBackRef != NULL);
|
|
|
|
/*
|
|
* Indicate another unhandled interrupt for stats
|
|
*/
|
|
((XScuGic *)((void *)CallBackRef))->UnhandledInterrupts++;
|
|
}
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* Sets the interrupt priority and trigger type for the specificd IRQ source.
|
|
*
|
|
* @param InstancePtr is a pointer to the instance to be worked on.
|
|
* @param Int_Id is the IRQ source number to modify
|
|
* @param Priority is the new priority for the IRQ source. 0 is highest
|
|
* priority, 0xF8 (248) is lowest. There are 32 priority levels
|
|
* supported with a step of 8. Hence the supported priorities are
|
|
* 0, 8, 16, 32, 40 ..., 248.
|
|
* @param Trigger is the new trigger type for the IRQ source.
|
|
* Each bit pair describes the configuration for an INT_ID.
|
|
* SFI Read Only b10 always
|
|
* PPI Read Only depending on how the PPIs are configured.
|
|
* b01 Active HIGH level sensitive
|
|
* b11 Rising edge sensitive
|
|
* SPI LSB is read only.
|
|
* b01 Active HIGH level sensitive
|
|
* b11 Rising edge sensitive/
|
|
*
|
|
* @return None.
|
|
*
|
|
* @note None.
|
|
*
|
|
*****************************************************************************/
|
|
void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
|
|
u8 Priority, u8 Trigger)
|
|
{
|
|
u32 RegValue;
|
|
u8 LocalPriority;
|
|
LocalPriority = Priority;
|
|
|
|
Xil_AssertVoid(InstancePtr != NULL);
|
|
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
|
Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
|
|
Xil_AssertVoid(Trigger <= (u8)XSCUGIC_INT_CFG_MASK);
|
|
Xil_AssertVoid(LocalPriority <= (u8)XSCUGIC_MAX_INTR_PRIO_VAL);
|
|
|
|
/*
|
|
* Determine the register to write to using the Int_Id.
|
|
*/
|
|
RegValue = XScuGic_DistReadReg(InstancePtr,
|
|
XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
|
|
|
|
/*
|
|
* The priority bits are Bits 7 to 3 in GIC Priority Register. This
|
|
* means the number of priority levels supported are 32 and they are
|
|
* in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
|
|
* The lower order 3 bits are masked before putting it in the register.
|
|
*/
|
|
LocalPriority = LocalPriority & (u8)XSCUGIC_INTR_PRIO_MASK;
|
|
/*
|
|
* Shift and Mask the correct bits for the priority and trigger in the
|
|
* register
|
|
*/
|
|
RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
|
|
RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
|
|
|
|
/*
|
|
* Write the value back to the register.
|
|
*/
|
|
XScuGic_DistWriteReg(InstancePtr, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
|
|
RegValue);
|
|
|
|
/*
|
|
* Determine the register to write to using the Int_Id.
|
|
*/
|
|
RegValue = XScuGic_DistReadReg(InstancePtr,
|
|
XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
|
|
|
|
/*
|
|
* Shift and Mask the correct bits for the priority and trigger in the
|
|
* register
|
|
*/
|
|
RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
|
|
RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
|
|
|
|
/*
|
|
* Write the value back to the register.
|
|
*/
|
|
XScuGic_DistWriteReg(InstancePtr, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
|
|
RegValue);
|
|
|
|
}
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* Gets the interrupt priority and trigger type for the specificd IRQ source.
|
|
*
|
|
* @param InstancePtr is a pointer to the instance to be worked on.
|
|
* @param Int_Id is the IRQ source number to modify
|
|
* @param Priority is a pointer to the value of the priority of the IRQ
|
|
* source. This is a return value.
|
|
* @param Trigger is pointer to the value of the trigger of the IRQ
|
|
* source. This is a return value.
|
|
*
|
|
* @return None.
|
|
*
|
|
* @note None
|
|
*
|
|
*****************************************************************************/
|
|
void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
|
|
u8 *Priority, u8 *Trigger)
|
|
{
|
|
u32 RegValue;
|
|
|
|
Xil_AssertVoid(InstancePtr != NULL);
|
|
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
|
Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
|
|
Xil_AssertVoid(Priority != NULL);
|
|
Xil_AssertVoid(Trigger != NULL);
|
|
|
|
/*
|
|
* Determine the register to read to using the Int_Id.
|
|
*/
|
|
RegValue = XScuGic_DistReadReg(InstancePtr,
|
|
XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
|
|
|
|
/*
|
|
* Shift and Mask the correct bits for the priority and trigger in the
|
|
* register
|
|
*/
|
|
RegValue = RegValue >> ((Int_Id%4U)*8U);
|
|
*Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
|
|
|
|
/*
|
|
* Determine the register to read to using the Int_Id.
|
|
*/
|
|
RegValue = XScuGic_DistReadReg(InstancePtr,
|
|
XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
|
|
|
|
/*
|
|
* Shift and Mask the correct bits for the priority and trigger in the
|
|
* register
|
|
*/
|
|
RegValue = RegValue >> ((Int_Id%16U)*2U);
|
|
|
|
*Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
|
|
}
|
|
|