embeddedsw/XilinxProcessorIPLib
Andrei-Liviu Simion 05f71ab631 dp: rx: Waiting for PHY to be ready based on number of lanes.
If the DisplayPort core is configured for 1 or 2 maximum lanes, wait for PHY to
be ready only on those lanes rather than waiting on all 4 lanes.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:34:32 +05:30
..
drivers dp: rx: Waiting for PHY to be ready based on number of lanes. 2015-04-26 10:34:32 +05:30