2c8f92039d
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
913 lines
26 KiB
C
Executable file
913 lines
26 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xaxivdma_example_intr.c
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*
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* This example demonstrates how to use the AXI Video DMA with other video IPs
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* to do video frame transfers. This example does not work by itself. It needs
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* two other Video IPs, one for writing video frames to the memory and one for
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* reading video frames from the memory.
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*
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* To see the debug print, you need a Uart16550 or uartlite in your system,
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* and please set "-DDEBUG" in your compiler options. You need to rebuild your
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* software executable.
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*
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* @note
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* The values of DDR_BASE_ADDR and DDR_HIGH_ADDR should be as per the HW system.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a jz 07/26/10 First release
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* 1.01a jz 09/26/10 Updated callback function signature
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* 2.00a jz 12/10/10 Added support for direct register access mode, v3 core
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* 2.01a rvp 01/22/11 Renamed the example file to be consistent
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* Added support to the example to use SCU GIC interrupt
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* controller for ARM, some functions in this example have
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* changed.
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* rkv 03/28/11 Updated to support for frame store register.
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* 3.00a srt 08/26/11 Added support for Flush on Frame Sync Feature.
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* 4.00a srt 03/06/12 Modified interrupt support for Zynq.
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* 4.02a srt 09/25/12 Fixed CR 677704
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* Description - Arguments misused in function
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* XAxiVdma_IntrEnable().
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* 4.03a srt 03/01/13 Updated DDR base address for IPI designs (CR 703656).
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* </pre>
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*
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* ***************************************************************************
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*/
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#include "xaxivdma.h"
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#include "xparameters.h"
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#include "xil_exception.h"
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#ifdef XPAR_INTC_0_DEVICE_ID
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#include "xintc.h"
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#else
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#include "xscugic.h"
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#endif
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#ifndef __MICROBLAZE__
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#include "xpseudo_asm_gcc.h"
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#include "xreg_cortexa9.h"
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#endif
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#if defined(XPAR_UARTNS550_0_BASEADDR)
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#include "xuartns550_l.h" /* to use uartns550 */
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#endif
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/******************** Constant Definitions **********************************/
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/*
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* Device related constants. These need to defined as per the HW system.
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*/
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#define DMA_DEVICE_ID XPAR_AXIVDMA_0_DEVICE_ID
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#ifdef XPAR_INTC_0_DEVICE_ID
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#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID
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#define WRITE_INTR_ID XPAR_INTC_0_AXIVDMA_0_S2MM_INTROUT_VEC_ID
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#define READ_INTR_ID XPAR_INTC_0_AXIVDMA_0_MM2S_INTROUT_VEC_ID
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#else
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#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
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#define WRITE_INTR_ID XPAR_FABRIC_AXIVDMA_0_S2MM_INTROUT_VEC_ID
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#define READ_INTR_ID XPAR_FABRIC_AXIVDMA_0_MM2S_INTROUT_VEC_ID
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#endif
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#ifdef XPAR_V6DDR_0_S_AXI_BASEADDR
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#define DDR_BASE_ADDR XPAR_V6DDR_0_S_AXI_BASEADDR
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#define DDR_HIGH_ADDR XPAR_V6DDR_0_S_AXI_HIGHADDR
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#elif XPAR_S6DDR_0_S0_AXI_BASEADDR
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#define DDR_BASE_ADDR XPAR_S6DDR_0_S0_AXI_BASEADDR
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#define DDR_HIGH_ADDR XPAR_S6DDR_0_S0_AXI_HIGHADDR
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#elif XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
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#define DDR_BASE_ADDR XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
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#define DDR_HIGH_ADDR XPAR_AXI_7SDDR_0_S_AXI_HIGHADDR
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#elif XPAR_MIG7SERIES_0_BASEADDR
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#define DDR_BASE_ADDR XPAR_MIG7SERIES_0_BASEADDR
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#define DDR_HIGH_ADDR XPAR_MIG7SERIES_0_HIGHADDR
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#else
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#warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \
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DEFAULT SET TO 0x01000000
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#define DDR_BASE_ADDR 0x01000000
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#define DDR_HIGH_ADDR 0x0F000000
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#endif
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/* Memory space for the frame buffers
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*
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* This example only needs one set of frame buffers, because one video IP is
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* to write to the frame buffers, and the other video IP is to read from the
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* frame buffers.
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*
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* For 16 frames of 1080p, it needs 0x07E90000 memory for frame buffers
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*/
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#define MEM_BASE_ADDR (DDR_BASE_ADDR + 0x01000000)
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#define MEM_HIGH_ADDR DDR_HIGH_ADDR
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#define MEM_SPACE (MEM_HIGH_ADDR - MEM_BASE_ADDR)
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/* Read channel and write channel start from the same place
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*
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* One video IP write to the memory region, the other video IP read from it
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*/
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#define READ_ADDRESS_BASE MEM_BASE_ADDR
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#define WRITE_ADDRESS_BASE MEM_BASE_ADDR
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/* Frame size related constants
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*/
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#define FRAME_HORIZONTAL_LEN 0x1E00 /* 1920 pixels, each pixel 4 bytes */
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#define FRAME_VERTICAL_LEN 0x438 /* 1080 pixels */
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/* Subframe to be transferred by Video DMA
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*
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*|<----------------- FRAME_HORIZONTAL_LEN ---------------------->|
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* --------------------------------------------------------------------
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*| | ^
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*| | |
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*| |<-SUBFRAME_HORIZONTAL_SIZE ->| | FRAME_
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*| ----------------------------------- | VERTICAL_
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*| |/////////////////////////////| ^ | LEN
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*| |/////////////////////////////| | | |
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*| |/////////////////////////////| | | |
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*| |/////////////////////////////| SUBFRAME_ | |
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*| |/////////////////////////////| VERTICAL_ | |
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*| |/////////////////////////////| SIZE | |
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*| |/////////////////////////////| | | |
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*| |/////////////////////////////| v | |
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*| ---------------------------------- | |
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*| | v
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*--------------------------------------------------------------------
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*
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* Note that SUBFRAME_HORIZONTAL_SIZE and SUBFRAME_VERTICAL_SIZE must ensure
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* to be inside the frame.
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*/
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#define SUBFRAME_START_OFFSET (FRAME_HORIZONTAL_LEN * 5 + 32)
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#define SUBFRAME_HORIZONTAL_SIZE 100
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#define SUBFRAME_VERTICAL_SIZE 100
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/* Number of frames to work on, this is to set the frame count threshold
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*
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* We multiply 15 to the num stores is to increase the intervals between
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* interrupts. If you are using fsync, then it is not necessary.
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*/
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#define NUMBER_OF_READ_FRAMES 8
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#define NUMBER_OF_WRITE_FRAMES 8
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/* Number of frames to transfer
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*
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* This is used to monitor the progress of the test, test purpose only
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*/
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#define NUM_TEST_FRAME_SETS 10
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/* Delay timer counter
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*
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* WARNING: If you are using fsync, please increase the delay counter value
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* to be 255. Because with fsync, the inter-frame delay is long. If you do not
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* care about inactivity of the hardware, set this counter to be 0, which
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* disables delay interrupt.
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*/
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#define DELAY_TIMER_COUNTER 10
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/*
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* Device instance definitions
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*/
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XAxiVdma AxiVdma;
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#ifdef XPAR_INTC_0_DEVICE_ID
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static XIntc Intc; /* Instance of the Interrupt Controller */
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#else
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static XScuGic Intc; /* Instance of the Interrupt Controller */
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#endif
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/* Data address
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*
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* Read and write sub-frame use the same settings
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*/
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static u32 ReadFrameAddr;
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static u32 WriteFrameAddr;
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static u32 BlockStartOffset;
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static u32 BlockHoriz;
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static u32 BlockVert;
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/* DMA channel setup
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*/
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static XAxiVdma_DmaSetup ReadCfg;
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static XAxiVdma_DmaSetup WriteCfg;
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/* Transfer statics
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*/
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static int ReadDone;
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static int ReadError;
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static int WriteDone;
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static int WriteError;
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/******************* Function Prototypes ************************************/
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static int ReadSetup(XAxiVdma *InstancePtr);
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static int WriteSetup(XAxiVdma * InstancePtr);
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static int StartTransfer(XAxiVdma *InstancePtr);
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static int SetupIntrSystem(XAxiVdma *AxiVdmaPtr, u16 ReadIntrId,
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u16 WriteIntrId);
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static void DisableIntrSystem(u16 ReadIntrId, u16 WriteIntrId);
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/* Interrupt call back functions
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*/
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static void ReadCallBack(void *CallbackRef, u32 Mask);
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static void ReadErrorCallBack(void *CallbackRef, u32 Mask);
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static void WriteCallBack(void *CallbackRef, u32 Mask);
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static void WriteErrorCallBack(void *CallbackRef, u32 Mask);
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#if defined(XPAR_UARTNS550_0_BASEADDR)
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/*****************************************************************************/
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/*
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*
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* Uart16550 setup routine, need to set baudrate to 9600 and data bits to 8
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*
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*
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******************************************************************************/
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static void Uart550_Setup(void)
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{
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/* Set the baudrate to be predictable
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*/
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XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
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XPAR_XUARTNS550_CLOCK_HZ, 9600);
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XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
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XUN_LCR_8_DATA_BITS);
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}
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#endif
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/*****************************************************************************/
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/**
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*
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* Main function
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*
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* This function is the main entry point of the example on DMA core. It sets up
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* DMA engine to be ready to receive and send frames, and start the transfers.
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* It waits for the transfer of the specified number of frame sets, and check
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* for transfer errors.
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*
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* @return
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* - XST_SUCCESS if example finishes successfully
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* - XST_FAILURE if example fails.
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*
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* @note None.
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*
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******************************************************************************/
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int main(void)
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{
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int Status;
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XAxiVdma_Config *Config;
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XAxiVdma_FrameCounter FrameCfg;
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#if defined(XPAR_UARTNS550_0_BASEADDR)
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Uart550_Setup();
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#endif
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WriteDone = 0;
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ReadDone = 0;
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WriteError = 0;
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ReadError = 0;
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ReadFrameAddr = READ_ADDRESS_BASE;
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WriteFrameAddr = WRITE_ADDRESS_BASE;
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BlockStartOffset = SUBFRAME_START_OFFSET;
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BlockHoriz = SUBFRAME_HORIZONTAL_SIZE;
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BlockVert = SUBFRAME_VERTICAL_SIZE;
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xil_printf("\r\n--- Entering main() --- \r\n");
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/* The information of the XAxiVdma_Config comes from hardware build.
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* The user IP should pass this information to the AXI DMA core.
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*/
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Config = XAxiVdma_LookupConfig(DMA_DEVICE_ID);
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if (!Config) {
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xil_printf(
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"No video DMA found for ID %d\r\n", DMA_DEVICE_ID);
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return XST_FAILURE;
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}
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/* Initialize DMA engine */
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Status = XAxiVdma_CfgInitialize(&AxiVdma, Config, Config->BaseAddress);
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if (Status != XST_SUCCESS) {
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xil_printf(
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"Configuration Initialization failed %d\r\n", Status);
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return XST_FAILURE;
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}
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Status = XAxiVdma_SetFrmStore(&AxiVdma, NUMBER_OF_READ_FRAMES,
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XAXIVDMA_READ);
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if (Status != XST_SUCCESS) {
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xil_printf(
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"Setting Frame Store Number Failed in Read Channel"
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" %d\r\n", Status);
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return XST_FAILURE;
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}
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Status = XAxiVdma_SetFrmStore(&AxiVdma, NUMBER_OF_WRITE_FRAMES,
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XAXIVDMA_WRITE);
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if (Status != XST_SUCCESS) {
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xil_printf(
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"Setting Frame Store Number Failed in Write Channel"
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" %d\r\n", Status);
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return XST_FAILURE;
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}
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/* Setup frame counter and delay counter for both channels
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*
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* This is to monitor the progress of the test only
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*
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* WARNING: In free-run mode, interrupts may overwhelm the system.
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* In that case, it is better to disable interrupts.
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*/
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FrameCfg.ReadFrameCount = NUMBER_OF_READ_FRAMES;
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FrameCfg.WriteFrameCount = NUMBER_OF_WRITE_FRAMES;
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FrameCfg.ReadDelayTimerCount = DELAY_TIMER_COUNTER;
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FrameCfg.WriteDelayTimerCount = DELAY_TIMER_COUNTER;
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Status = XAxiVdma_SetFrameCounter(&AxiVdma, &FrameCfg);
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if (Status != XST_SUCCESS) {
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xil_printf(
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"Set frame counter failed %d\r\n", Status);
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if(Status == XST_VDMA_MISMATCH_ERROR)
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xil_printf("DMA Mismatch Error\r\n");
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return XST_FAILURE;
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}
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/*
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* Setup your video IP that writes to the memory
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*/
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/* Setup the write channel
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*/
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Status = WriteSetup(&AxiVdma);
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if (Status != XST_SUCCESS) {
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xil_printf(
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"Write channel setup failed %d\r\n", Status);
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if(Status == XST_VDMA_MISMATCH_ERROR)
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xil_printf("DMA Mismatch Error\r\n");
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return XST_FAILURE;
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}
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/*
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* Setup your video IP that reads from the memory
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*/
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/* Setup the read channel
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*/
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Status = ReadSetup(&AxiVdma);
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if (Status != XST_SUCCESS) {
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xil_printf(
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"Read channel setup failed %d\r\n", Status);
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if(Status == XST_VDMA_MISMATCH_ERROR)
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xil_printf("DMA Mismatch Error\r\n");
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return XST_FAILURE;
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}
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Status = SetupIntrSystem(&AxiVdma, READ_INTR_ID, WRITE_INTR_ID);
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if (Status != XST_SUCCESS) {
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xil_printf(
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"Setup interrupt system failed %d\r\n", Status);
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return XST_FAILURE;
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}
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/* Register callback functions
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*/
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XAxiVdma_SetCallBack(&AxiVdma, XAXIVDMA_HANDLER_GENERAL, ReadCallBack,
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(void *)&AxiVdma, XAXIVDMA_READ);
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XAxiVdma_SetCallBack(&AxiVdma, XAXIVDMA_HANDLER_ERROR,
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ReadErrorCallBack, (void *)&AxiVdma, XAXIVDMA_READ);
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XAxiVdma_SetCallBack(&AxiVdma, XAXIVDMA_HANDLER_GENERAL,
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WriteCallBack, (void *)&AxiVdma, XAXIVDMA_WRITE);
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XAxiVdma_SetCallBack(&AxiVdma, XAXIVDMA_HANDLER_ERROR,
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WriteErrorCallBack, (void *)&AxiVdma, XAXIVDMA_WRITE);
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/* Enable your video IP interrupts if needed
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*/
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/* Start the DMA engine to transfer
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*/
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Status = StartTransfer(&AxiVdma);
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if (Status != XST_SUCCESS) {
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if(Status == XST_VDMA_MISMATCH_ERROR)
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xil_printf("DMA Mismatch Error\r\n");
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return XST_FAILURE;
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}
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/* Enable DMA read and write channel interrupts
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*
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* If interrupts overwhelms the system, please do not enable interrupt
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*/
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XAxiVdma_IntrEnable(&AxiVdma, XAXIVDMA_IXR_ALL_MASK, XAXIVDMA_WRITE);
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XAxiVdma_IntrEnable(&AxiVdma, XAXIVDMA_IXR_ALL_MASK, XAXIVDMA_READ);
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/* Every set of frame buffer finish causes a completion interrupt
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*/
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while ((WriteDone < NUM_TEST_FRAME_SETS) && !ReadError &&
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(ReadDone < NUM_TEST_FRAME_SETS) && !WriteError) {
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/* NOP */
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}
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if (ReadError || WriteError) {
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xil_printf("Test has transfer error %d/%d\r\n",
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ReadError, WriteError);
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Status = XST_FAILURE;
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}
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else {
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xil_printf("Test passed\r\n");
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}
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xil_printf("--- Exiting main() --- \r\n");
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DisableIntrSystem(READ_INTR_ID, WRITE_INTR_ID);
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if (Status != XST_SUCCESS) {
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if(Status == XST_VDMA_MISMATCH_ERROR)
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xil_printf("DMA Mismatch Error\r\n");
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return XST_FAILURE;
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}
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return XST_SUCCESS;
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}
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/*****************************************************************************/
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/**
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*
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* This function sets up the read channel
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*
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* @param InstancePtr is the instance pointer to the DMA engine.
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*
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* @return XST_SUCCESS if the setup is successful, XST_FAILURE otherwise.
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*
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* @note None.
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*
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******************************************************************************/
|
|
static int ReadSetup(XAxiVdma *InstancePtr)
|
|
{
|
|
int Index;
|
|
u32 Addr;
|
|
int Status;
|
|
|
|
ReadCfg.VertSizeInput = SUBFRAME_VERTICAL_SIZE;
|
|
ReadCfg.HoriSizeInput = SUBFRAME_HORIZONTAL_SIZE;
|
|
|
|
ReadCfg.Stride = FRAME_HORIZONTAL_LEN;
|
|
ReadCfg.FrameDelay = 0; /* This example does not test frame delay */
|
|
|
|
ReadCfg.EnableCircularBuf = 1;
|
|
ReadCfg.EnableSync = 0; /* No Gen-Lock */
|
|
|
|
ReadCfg.PointNum = 0; /* No Gen-Lock */
|
|
ReadCfg.EnableFrameCounter = 0; /* Endless transfers */
|
|
|
|
ReadCfg.FixedFrameStoreAddr = 0; /* We are not doing parking */
|
|
|
|
Status = XAxiVdma_DmaConfig(InstancePtr, XAXIVDMA_READ, &ReadCfg);
|
|
if (Status != XST_SUCCESS) {
|
|
xil_printf(
|
|
"Read channel config failed %d\r\n", Status);
|
|
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
/* Initialize buffer addresses
|
|
*
|
|
* These addresses are physical addresses
|
|
*/
|
|
Addr = READ_ADDRESS_BASE + BlockStartOffset;
|
|
for(Index = 0; Index < NUMBER_OF_READ_FRAMES; Index++) {
|
|
ReadCfg.FrameStoreStartAddr[Index] = Addr;
|
|
|
|
Addr += FRAME_HORIZONTAL_LEN * FRAME_VERTICAL_LEN;
|
|
}
|
|
|
|
/* Set the buffer addresses for transfer in the DMA engine
|
|
* The buffer addresses are physical addresses
|
|
*/
|
|
Status = XAxiVdma_DmaSetBufferAddr(InstancePtr, XAXIVDMA_READ,
|
|
ReadCfg.FrameStoreStartAddr);
|
|
if (Status != XST_SUCCESS) {
|
|
xil_printf(
|
|
"Read channel set buffer address failed %d\r\n", Status);
|
|
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
return XST_SUCCESS;
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
*
|
|
* This function sets up the write channel
|
|
*
|
|
* @param InstancePtr is the instance pointer to the DMA engine.
|
|
*
|
|
* @return XST_SUCCESS if the setup is successful, XST_FAILURE otherwise.
|
|
*
|
|
* @note None.
|
|
*
|
|
******************************************************************************/
|
|
static int WriteSetup(XAxiVdma * InstancePtr)
|
|
{
|
|
int Index;
|
|
u32 Addr;
|
|
int Status;
|
|
|
|
WriteCfg.VertSizeInput = SUBFRAME_VERTICAL_SIZE;
|
|
WriteCfg.HoriSizeInput = SUBFRAME_HORIZONTAL_SIZE;
|
|
|
|
WriteCfg.Stride = FRAME_HORIZONTAL_LEN;
|
|
WriteCfg.FrameDelay = 0; /* This example does not test frame delay */
|
|
|
|
WriteCfg.EnableCircularBuf = 1;
|
|
WriteCfg.EnableSync = 0; /* No Gen-Lock */
|
|
|
|
WriteCfg.PointNum = 0; /* No Gen-Lock */
|
|
WriteCfg.EnableFrameCounter = 0; /* Endless transfers */
|
|
|
|
WriteCfg.FixedFrameStoreAddr = 0; /* We are not doing parking */
|
|
|
|
Status = XAxiVdma_DmaConfig(InstancePtr, XAXIVDMA_WRITE, &WriteCfg);
|
|
if (Status != XST_SUCCESS) {
|
|
xil_printf(
|
|
"Write channel config failed %d\r\n", Status);
|
|
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
/* Initialize buffer addresses
|
|
*
|
|
* Use physical addresses
|
|
*/
|
|
Addr = WRITE_ADDRESS_BASE + BlockStartOffset;
|
|
for(Index = 0; Index < NUMBER_OF_WRITE_FRAMES; Index++) {
|
|
WriteCfg.FrameStoreStartAddr[Index] = Addr;
|
|
|
|
Addr += FRAME_HORIZONTAL_LEN * FRAME_VERTICAL_LEN;
|
|
}
|
|
|
|
/* Set the buffer addresses for transfer in the DMA engine
|
|
*/
|
|
Status = XAxiVdma_DmaSetBufferAddr(InstancePtr, XAXIVDMA_WRITE,
|
|
WriteCfg.FrameStoreStartAddr);
|
|
if (Status != XST_SUCCESS) {
|
|
xil_printf(
|
|
"Write channel set buffer address failed %d\r\n", Status);
|
|
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
/* Clear data buffer
|
|
*/
|
|
memset((void *)WriteFrameAddr, 0,
|
|
FRAME_HORIZONTAL_LEN * FRAME_VERTICAL_LEN * NUMBER_OF_WRITE_FRAMES);
|
|
|
|
return XST_SUCCESS;
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
*
|
|
* This function starts the DMA transfers. Since the DMA engine is operating
|
|
* in circular buffer mode, video frames will be transferred continuously.
|
|
*
|
|
* @param InstancePtr points to the DMA engine instance
|
|
*
|
|
* @return XST_SUCCESS if both read and write start succesfully
|
|
* XST_FAILURE if one or both directions cannot be started
|
|
*
|
|
* @note None.
|
|
*
|
|
******************************************************************************/
|
|
static int StartTransfer(XAxiVdma *InstancePtr)
|
|
{
|
|
int Status;
|
|
|
|
Status = XAxiVdma_DmaStart(InstancePtr, XAXIVDMA_WRITE);
|
|
if (Status != XST_SUCCESS) {
|
|
xil_printf(
|
|
"Start Write transfer failed %d\r\n", Status);
|
|
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
Status = XAxiVdma_DmaStart(InstancePtr, XAXIVDMA_READ);
|
|
if (Status != XST_SUCCESS) {
|
|
xil_printf(
|
|
"Start read transfer failed %d\r\n", Status);
|
|
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
return XST_SUCCESS;
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/*
|
|
*
|
|
* This function setups the interrupt system so interrupts can occur for the
|
|
* DMA. This function assumes INTC component exists in the hardware system.
|
|
*
|
|
* @param AxiDmaPtr is a pointer to the instance of the DMA engine
|
|
* @param ReadIntrId is the read channel Interrupt ID.
|
|
* @param WriteIntrId is the write channel Interrupt ID.
|
|
*
|
|
* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
|
|
*
|
|
* @note None.
|
|
*
|
|
******************************************************************************/
|
|
static int SetupIntrSystem(XAxiVdma *AxiVdmaPtr, u16 ReadIntrId,
|
|
u16 WriteIntrId)
|
|
{
|
|
int Status;
|
|
|
|
#ifdef XPAR_INTC_0_DEVICE_ID
|
|
XIntc *IntcInstancePtr =&Intc;
|
|
|
|
|
|
/* Initialize the interrupt controller and connect the ISRs */
|
|
Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
|
|
if (Status != XST_SUCCESS) {
|
|
|
|
xil_printf( "Failed init intc\r\n");
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
Status = XIntc_Connect(IntcInstancePtr, ReadIntrId,
|
|
(XInterruptHandler)XAxiVdma_ReadIntrHandler, AxiVdmaPtr);
|
|
if (Status != XST_SUCCESS) {
|
|
|
|
xil_printf(
|
|
"Failed read channel connect intc %d\r\n", Status);
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
Status = XIntc_Connect(IntcInstancePtr, WriteIntrId,
|
|
(XInterruptHandler)XAxiVdma_WriteIntrHandler, AxiVdmaPtr);
|
|
if (Status != XST_SUCCESS) {
|
|
|
|
xil_printf(
|
|
"Failed write channel connect intc %d\r\n", Status);
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
/* Start the interrupt controller */
|
|
Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
|
|
if (Status != XST_SUCCESS) {
|
|
|
|
xil_printf( "Failed to start intc\r\n");
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
/* Enable interrupts from the hardware */
|
|
XIntc_Enable(IntcInstancePtr, ReadIntrId);
|
|
XIntc_Enable(IntcInstancePtr, WriteIntrId);
|
|
|
|
Xil_ExceptionInit();
|
|
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
|
|
(Xil_ExceptionHandler)XIntc_InterruptHandler,
|
|
(void *)IntcInstancePtr);
|
|
|
|
Xil_ExceptionEnable();
|
|
|
|
#else
|
|
|
|
XScuGic *IntcInstancePtr = &Intc; /* Instance of the Interrupt Controller */
|
|
XScuGic_Config *IntcConfig;
|
|
|
|
|
|
/*
|
|
* Initialize the interrupt controller driver so that it is ready to
|
|
* use.
|
|
*/
|
|
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
|
|
if (NULL == IntcConfig) {
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
|
|
IntcConfig->CpuBaseAddress);
|
|
if (Status != XST_SUCCESS) {
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
XScuGic_SetPriorityTriggerType(IntcInstancePtr, ReadIntrId, 0xA0, 0x3);
|
|
XScuGic_SetPriorityTriggerType(IntcInstancePtr, WriteIntrId, 0xA0, 0x3);
|
|
|
|
/*
|
|
* Connect the device driver handler that will be called when an
|
|
* interrupt for the device occurs, the handler defined above performs
|
|
* the specific interrupt processing for the device.
|
|
*/
|
|
Status = XScuGic_Connect(IntcInstancePtr, ReadIntrId,
|
|
(Xil_InterruptHandler)XAxiVdma_ReadIntrHandler,
|
|
AxiVdmaPtr);
|
|
if (Status != XST_SUCCESS) {
|
|
return Status;
|
|
}
|
|
|
|
Status = XScuGic_Connect(IntcInstancePtr, WriteIntrId,
|
|
(Xil_InterruptHandler)XAxiVdma_WriteIntrHandler,
|
|
AxiVdmaPtr);
|
|
if (Status != XST_SUCCESS) {
|
|
return Status;
|
|
}
|
|
|
|
/*
|
|
* Enable the interrupt for the DMA device.
|
|
*/
|
|
XScuGic_Enable(IntcInstancePtr, ReadIntrId);
|
|
XScuGic_Enable(IntcInstancePtr, WriteIntrId);
|
|
|
|
Xil_ExceptionInit();
|
|
|
|
/*
|
|
* Connect the interrupt controller interrupt handler to the hardware
|
|
* interrupt handling logic in the processor.
|
|
*/
|
|
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
|
|
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
|
|
IntcInstancePtr);
|
|
|
|
|
|
/*
|
|
* Enable interrupts in the Processor.
|
|
*/
|
|
Xil_ExceptionEnable();
|
|
|
|
|
|
#endif
|
|
|
|
return XST_SUCCESS;
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
*
|
|
* This function disables the interrupts
|
|
*
|
|
* @param ReadIntrId is interrupt ID associated w/ DMA read channel
|
|
* @param WriteIntrId is interrupt ID associated w/ DMA write channel
|
|
*
|
|
* @return None.
|
|
*
|
|
* @note None.
|
|
*
|
|
******************************************************************************/
|
|
static void DisableIntrSystem(u16 ReadIntrId, u16 WriteIntrId)
|
|
{
|
|
|
|
#ifdef XPAR_INTC_0_DEVICE_ID
|
|
XIntc *IntcInstancePtr =&Intc;
|
|
|
|
/* Disconnect the interrupts for the DMA TX and RX channels */
|
|
XIntc_Disconnect(IntcInstancePtr, ReadIntrId);
|
|
XIntc_Disconnect(IntcInstancePtr, WriteIntrId);
|
|
#else
|
|
XScuGic *IntcInstancePtr = &Intc;
|
|
|
|
XScuGic_Disable(IntcInstancePtr, ReadIntrId);
|
|
XScuGic_Disable(IntcInstancePtr, WriteIntrId);
|
|
|
|
XScuGic_Disconnect(IntcInstancePtr, ReadIntrId);
|
|
XScuGic_Disconnect(IntcInstancePtr, WriteIntrId);
|
|
#endif
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/*
|
|
* Call back function for read channel
|
|
*
|
|
* This callback only clears the interrupts and updates the transfer status.
|
|
*
|
|
* @param CallbackRef is the call back reference pointer
|
|
* @param Mask is the interrupt mask passed in from the driver
|
|
*
|
|
* @return None
|
|
*
|
|
******************************************************************************/
|
|
static void ReadCallBack(void *CallbackRef, u32 Mask)
|
|
{
|
|
|
|
if (Mask & XAXIVDMA_IXR_FRMCNT_MASK) {
|
|
ReadDone += 1;
|
|
}
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/*
|
|
* Call back function for read channel error interrupt
|
|
*
|
|
* @param CallbackRef is the call back reference pointer
|
|
* @param Mask is the interrupt mask passed in from the driver
|
|
*
|
|
* @return None
|
|
*
|
|
******************************************************************************/
|
|
static void ReadErrorCallBack(void *CallbackRef, u32 Mask)
|
|
{
|
|
|
|
if (Mask & XAXIVDMA_IXR_ERROR_MASK) {
|
|
ReadError += 1;
|
|
}
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/*
|
|
* Call back function for write channel
|
|
*
|
|
* This callback only clears the interrupts and updates the transfer status.
|
|
*
|
|
* @param CallbackRef is the call back reference pointer
|
|
* @param Mask is the interrupt mask passed in from the driver
|
|
*
|
|
* @return None
|
|
*
|
|
******************************************************************************/
|
|
static void WriteCallBack(void *CallbackRef, u32 Mask)
|
|
{
|
|
|
|
if (Mask & XAXIVDMA_IXR_FRMCNT_MASK) {
|
|
WriteDone += 1;
|
|
}
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/*
|
|
* Call back function for write channel error interrupt
|
|
*
|
|
* @param CallbackRef is the call back reference pointer
|
|
* @param Mask is the interrupt mask passed in from the driver
|
|
*
|
|
* @return None
|
|
*
|
|
******************************************************************************/
|
|
static void WriteErrorCallBack(void *CallbackRef, u32 Mask)
|
|
{
|
|
|
|
if (Mask & XAXIVDMA_IXR_ERROR_MASK) {
|
|
WriteError += 1;
|
|
}
|
|
}
|
|
|
|
|