274 lines
9.1 KiB
C
274 lines
9.1 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xcsudma_intr.c
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* @addtogroup csudma_v1_0
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* @{
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*
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* This file contains interrupt related functions of Xilinx CSU_DMA core.
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* Please see xcsudma.h for more details of the driver.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ------ -------- ---------------------------------------------------
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* 1.0 vnsld 22/10/14 First release
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* </pre>
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "xcsudma.h"
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/************************** Function Prototypes ******************************/
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/************************** Function Definitions *****************************/
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/*****************************************************************************/
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/**
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*
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* This function returns interrupt status read from Interrupt Status Register.
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* Use the XCSUDMA_IXR_*_MASK constants defined in xcsudma_hw.h to interpret the
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* returned value.
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*
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* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
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* @param Channel represents the type of channel either it is Source or
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* Destination.
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* Source channel - XCSUDMA_SRC_CHANNEL
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* Destination Channel - XCSUDMA_DST_CHANNEL
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*
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* @return The pending interrupts of the CSU_DMA. Use th following masks
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* to interpret the returned value.
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* XCSUDMA_IXR_SRC_MASK - For Source channel
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* XCSUDMA_IXR_DST_MASK - For Destination channel
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*
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* @note None.
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*
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******************************************************************************/
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u32 XCsuDma_IntrGetStatus(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
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{
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u32 Data;
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/* Verify arguments */
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
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(Channel == (XCSUDMA_DST_CHANNEL)));
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Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
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(u32)(XCSUDMA_I_STS_OFFSET) +
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((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)));
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return Data;
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}
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/*****************************************************************************/
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/**
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*
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* This function clears interrupt(s). Every bit set in Interrupt Status
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* Register indicates that a specific type of interrupt is occurring, and this
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* function clears one or more interrupts by writing a bit mask to Interrupt
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* Clear Register.
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*
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* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
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* @param Channel represents the type of channel either it is Source or
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* Destination.
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* Source channel - XCSUDMA_SRC_CHANNEL
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* Destination Channel - XCSUDMA_DST_CHANNEL
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* @param Mask is the mask to clear. Bit positions of 1 will be cleared.
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* Bit positions of 0 will not change the previous interrupt
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* status. This mask is formed by OR'ing XCSUDMA_IXR_* bits
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* defined in xcsudma_hw.h.
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*
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* @note None.
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*
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******************************************************************************/
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void XCsuDma_IntrClear(XCsuDma *InstancePtr, XCsuDma_Channel Channel, u32 Mask)
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{
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/* Verify arguments */
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
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(Channel == (XCSUDMA_DST_CHANNEL)));
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if (Channel == (XCSUDMA_SRC_CHANNEL)) {
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XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
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(u32)(XCSUDMA_I_STS_OFFSET),
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(Mask & (u32)(XCSUDMA_IXR_SRC_MASK)));
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}
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else {
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XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
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((u32)(XCSUDMA_I_STS_OFFSET) +
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((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
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(Mask & (u32)(XCSUDMA_IXR_DST_MASK)));
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}
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}
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/*****************************************************************************/
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/**
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*
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* This function enables the interrupt(s). Use the XCSUDMA_IXR_*_MASK constants
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* defined in xcsudma_hw.h to create the bit-mask to enable interrupts.
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*
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* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
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* @param Channel represents the type of channel either it is Source or
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* Destination.
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* Source channel - XCSUDMA_SRC_CHANNEL
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* Destination Channel - XCSUDMA_DST_CHANNEL
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* @param Mask contains interrupts to be enabled.
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* - Bit positions of 1 will be enabled.
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* This mask is formed by OR'ing XCSUDMA_IXR_*_MASK bits defined
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* in xcsudma_hw.h.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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void XCsuDma_EnableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
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u32 Mask)
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{
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u32 Data;
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/* Verify arguments */
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
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(Channel == (XCSUDMA_DST_CHANNEL)));
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if (Channel == (XCSUDMA_SRC_CHANNEL)) {
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Data = Mask & (u32)(XCSUDMA_IXR_SRC_MASK);
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}
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else {
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Data = Mask & (u32)(XCSUDMA_IXR_DST_MASK);
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}
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/*
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* Write the mask to the IER Register
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*/
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XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
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((u32)(XCSUDMA_I_EN_OFFSET) +
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((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data);
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}
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/*****************************************************************************/
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/**
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*
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* This function disables the interrupt(s). Use the XCSUDMA_IXR_*_MASK constants
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* defined in xcsudma_hw.h to create the bit-mask to disable interrupts.
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*
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* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
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* @param Channel represents the type of channel either it is Source or
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* Destination.
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* Source channel - XCSUDMA_SRC_CHANNEL
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* Destination Channel - XCSUDMA_DST_CHANNEL
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* @param Mask contains interrupts to be disabled.
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* - Bit positions of 1 will be disabled.
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* This mask is formed by OR'ing XCSUDMA_IXR_*_MASK bits defined
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* in xcsudma_hw.h.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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void XCsuDma_DisableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
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u32 Mask)
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{
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u32 Data;
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/* Verify arguments */
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
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(Channel == (XCSUDMA_DST_CHANNEL)));
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if (Channel == XCSUDMA_SRC_CHANNEL) {
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Data = (Mask) & (u32)(XCSUDMA_IXR_SRC_MASK);
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}
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else {
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Data = (Mask) & (u32)(XCSUDMA_IXR_DST_MASK);
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}
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/*
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* Write the mask to the IDR Register
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*/
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XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
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((u32)(XCSUDMA_I_DIS_OFFSET) +
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((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data);
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}
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/*****************************************************************************/
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/**
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*
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* This function returns the interrupt mask to know which interrupts are
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* enabled and which of them were disaled.
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*
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* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
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* @param Channel represents the type of channel either it is Source or
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* Destination.
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* Source channel - XCSUDMA_SRC_CHANNEL
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* Destination Channel - XCSUDMA_DST_CHANNEL
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*
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* @return The current interrupt mask. The mask indicates which interrupts
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* are enabled/disabled.
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* 0 bit represents .....corresponding interrupt is enabled.
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* 1 bit represents .....Corresponding interrupt is disabled.
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* To interpret returned mask use
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* XCSUDMA_IXR_SRC_MASK........For source channel
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* XCSUDMA_IXR_DST_MASK........For destination channel
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*
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* @note None.
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*
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******************************************************************************/
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u32 XCsuDma_GetIntrMask(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
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{
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/* Verify arguments */
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
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(Channel == (XCSUDMA_DST_CHANNEL)));
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/*
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* Read the Interrupt Mask register
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*/
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return (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
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((u32)(XCSUDMA_I_MASK_OFFSET) +
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((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))));
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}
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/** @} */
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