2dee01e56d
This patch updates the standalone files copyright information with the latest content. Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
97 lines
3.8 KiB
ArmAsm
97 lines
3.8 KiB
ArmAsm
/******************************************************************************
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*
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* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/******************************************************************************
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*
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*
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* microblaze_invalidate_icache_range(unsigned int cacheaddr, unsigned int len)
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*
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* Invalidate an ICache range
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*
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* Parameters:
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* 'cacheaddr' - address in the Icache where invalidation begins
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* 'len' - length (in bytes) worth of Icache to be invalidated
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*
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*
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*******************************************************************************/
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#include "xparameters.h"
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#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
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#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
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#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
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#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
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#endif
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#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
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#define MB_VERSION_LT_v720
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#endif
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.text
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.globl microblaze_invalidate_icache_range
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.ent microblaze_invalidate_icache_range
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.align 2
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microblaze_invalidate_icache_range:
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#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */
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mfs r9, rmsr
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andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
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mts rmsr, r10
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#endif
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beqi r6, L_done /* Skip loop if size is zero */
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add r6, r5, r6 /* Compute end address */
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addik r6, r6, -1
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andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align end down to cache line */
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andi r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align start down to cache line */
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L_start:
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cmpu r18, r5, r6 /* Are we at the end? */
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blti r18, L_done
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wic r5, r0 /* Invalidate the cache line */
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brid L_start /* Branch to the beginning of the loop */
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addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */
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L_done:
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rtsd r15, 8 /* Return */
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#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
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mts rmsr, r9
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#else
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nop
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#endif
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.end microblaze_invalidate_icache_range
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