0af75fbce8
This patch modifies the the code according to MISRAC 2012. Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
178 lines
6.3 KiB
C
Executable file
178 lines
6.3 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/****************************************************************************/
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/**
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*
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* @file xscuwdt_hw.h
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*
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* This file contains the hardware interface to the Xilinx SCU private Watch Dog
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* Timer (XSCUWDT).
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- --- -------- ---------------------------------------------
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* 1.00a sdm 01/15/10 First release
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* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
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* of 0x20 as the base address obtained from the tools
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* starts at 0x20.
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* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
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* when the xstatus.h in the common driver overwrites
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* the xstatus.h of the standalone BSP during the
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* libgen.
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* </pre>
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*
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******************************************************************************/
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#ifndef XSCUWDT_HW_H /* prevent circular inclusions */
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#define XSCUWDT_HW_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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#include "xil_io.h"
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#include "xil_assert.h"
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/************************** Constant Definitions *****************************/
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/** @name Register Map
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* Offsets of registers from the start of the device. The WDT registers start at
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* an offset 0x20
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* @{
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*/
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#define XSCUWDT_LOAD_OFFSET 0x00U /**< Watchdog Load Register */
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#define XSCUWDT_COUNTER_OFFSET 0x04U /**< Watchdog Counter Register */
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#define XSCUWDT_CONTROL_OFFSET 0x08U /**< Watchdog Control Register */
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#define XSCUWDT_ISR_OFFSET 0x0CU /**< Watchdog Interrupt Status Register */
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#define XSCUWDT_RST_STS_OFFSET 0x10U /**< Watchdog Reset Status Register */
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#define XSCUWDT_DISABLE_OFFSET 0x14U /**< Watchdog Disable Register */
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/* @} */
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/** @name Watchdog Control register
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* This register bits control the prescaler, WD/Timer mode, Intr enable,
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* auto-reload, watchdog enable.
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* @{
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*/
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#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
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#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8U
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#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008U /**< Watchdog/Timer mode */
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#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004U /**< Intr enable (in
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timer mode) */
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#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
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timer mode) */
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#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001U /**< Watchdog enable */
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/* @} */
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/** @name Interrupt Status register
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* This register indicates the Counter register has reached zero in Counter
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* mode.
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* @{
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*/
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#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
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/*@}*/
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/** @name Reset Status register
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* This register indicates the Counter register has reached zero in Watchdog
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* mode and a reset request is sent.
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* @{
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*/
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#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001U /**< Time out occured */
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/*@}*/
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/** @name Disable register
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* This register is used to switch from watchdog mode to timer mode.
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* The software must write 0x12345678 and 0x87654321 successively to the
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* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
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* Control Register is set to zero.
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* @{
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*/
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#define XSCUWDT_DISABLE_VALUE1 0x12345678U /**< Watchdog mode disable
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value 1 */
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#define XSCUWDT_DISABLE_VALUE2 0x87654321U /**< Watchdog mode disable
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value 2 */
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/*@}*/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/****************************************************************************/
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/**
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*
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* Read the given register.
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*
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* @param BaseAddr is the base address of the device
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* @param RegOffset is the register offset to be read
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*
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* @return The 32-bit value of the register
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*
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* @note C-style signature:
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* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
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*
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*****************************************************************************/
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#define XScuWdt_ReadReg(BaseAddr, RegOffset) \
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Xil_In32((BaseAddr) + ((u32)RegOffset))
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/****************************************************************************/
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/**
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*
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* Write the given register.
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*
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* @param BaseAddr is the base address of the device
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* @param RegOffset is the register offset to be written
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* @param Data is the 32-bit value to write to the register
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*
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* @return None.
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*
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* @note C-style signature:
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* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
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*
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*****************************************************************************/
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#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \
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Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
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/************************** Function Prototypes ******************************/
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/************************** Variable Definitions *****************************/
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#ifdef __cplusplus
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}
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#endif
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#endif /* end of protection macro */
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