09090a4bc5
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
261 lines
10 KiB
C
261 lines
10 KiB
C
/*
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* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*/
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/*********************************************************************
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* This file contains PM master related data structures and
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* functions for accessing them. Also, each PM masters have defined
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* data structures used for tracking it's requests for each slave's
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* capabilities/states.
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*********************************************************************/
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#ifndef PM_MASTER_H_
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#define PM_MASTER_H_
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#include "pm_slave.h"
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#include "pm_common.h"
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#include "pm_proc.h"
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#include "pm_node.h"
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#include "pm_power.h"
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#include "xil_types.h"
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typedef u8 PmMasterId;
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typedef u8 PmRequirementId;
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typedef u8 PmMasterEvent;
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typedef struct PmMaster PmMaster;
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/*********************************************************************
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* Macros
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********************************************************************/
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/* Apu slaves */
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#define PM_MASTER_APU_SLAVE_OCM0 0U
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#define PM_MASTER_APU_SLAVE_OCM1 1U
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#define PM_MASTER_APU_SLAVE_OCM2 2U
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#define PM_MASTER_APU_SLAVE_OCM3 3U
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#define PM_MASTER_APU_SLAVE_L2 4U
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#define PM_MASTER_APU_SLAVE_USB0 5U
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#define PM_MASTER_APU_SLAVE_USB1 6U
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#define PM_MASTER_APU_SLAVE_TTC0 7U
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#define PM_MASTER_APU_SLAVE_TTC1 8U
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#define PM_MASTER_APU_SLAVE_TTC2 9U
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#define PM_MASTER_APU_SLAVE_TTC3 10U
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#define PM_MASTER_APU_SLAVE_SATA 11U
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#define PM_MASTER_APU_SLAVE_APLL 12U
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#define PM_MASTER_APU_SLAVE_VPLL 13U
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#define PM_MASTER_APU_SLAVE_DPLL 14U
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#define PM_MASTER_APU_SLAVE_RPLL 15U
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#define PM_MASTER_APU_SLAVE_IOPLL 16U
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#define PM_MASTER_APU_SLAVE_GPUPP0 17U
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#define PM_MASTER_APU_SLAVE_GPUPP1 18U
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#define PM_MASTER_APU_SLAVE_UART0 19U
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#define PM_MASTER_APU_SLAVE_UART1 20U
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#define PM_MASTER_APU_SLAVE_SPI0 21U
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#define PM_MASTER_APU_SLAVE_SPI1 22U
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#define PM_MASTER_APU_SLAVE_I2C0 23U
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#define PM_MASTER_APU_SLAVE_I2C1 24U
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#define PM_MASTER_APU_SLAVE_SD0 25U
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#define PM_MASTER_APU_SLAVE_SD1 26U
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#define PM_MASTER_APU_SLAVE_CAN0 27U
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#define PM_MASTER_APU_SLAVE_CAN1 28U
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#define PM_MASTER_APU_SLAVE_ETH0 29U
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#define PM_MASTER_APU_SLAVE_ETH1 30U
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#define PM_MASTER_APU_SLAVE_ETH2 31U
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#define PM_MASTER_APU_SLAVE_ETH3 32U
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#define PM_MASTER_APU_SLAVE_ADMA 33U
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#define PM_MASTER_APU_SLAVE_GDMA 34U
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#define PM_MASTER_APU_SLAVE_DP 35U
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#define PM_MASTER_APU_SLAVE_NAND 36U
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#define PM_MASTER_APU_SLAVE_QSPI 37U
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#define PM_MASTER_APU_SLAVE_GPIO 38U
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#define PM_MASTER_APU_SLAVE_AFI 39U
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#define PM_MASTER_APU_SLAVE_MAX 40U
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/* Rpu0 slaves */
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#define PM_MASTER_RPU_0_SLAVE_TCM0A 0U
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#define PM_MASTER_RPU_0_SLAVE_TCM0B 1U
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#define PM_MASTER_RPU_0_SLAVE_TCM1A 2U
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#define PM_MASTER_RPU_0_SLAVE_TCM1B 3U
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#define PM_MASTER_RPU_0_SLAVE_OCM0 4U
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#define PM_MASTER_RPU_0_SLAVE_OCM1 5U
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#define PM_MASTER_RPU_0_SLAVE_OCM2 6U
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#define PM_MASTER_RPU_0_SLAVE_OCM3 7U
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#define PM_MASTER_RPU_0_SLAVE_USB0 8U
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#define PM_MASTER_RPU_0_SLAVE_USB1 9U
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#define PM_MASTER_RPU_0_SLAVE_TTC0 10U
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#define PM_MASTER_RPU_0_SLAVE_SATA 11U
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#define PM_MASTER_RPU_0_SLAVE_APLL 12U
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#define PM_MASTER_RPU_0_SLAVE_VPLL 13U
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#define PM_MASTER_RPU_0_SLAVE_DPLL 14U
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#define PM_MASTER_RPU_0_SLAVE_RPLL 15U
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#define PM_MASTER_RPU_0_SLAVE_IOPLL 16U
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#define PM_MASTER_RPU_0_SLAVE_MAX 17U
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/* Pm Master request info masks */
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#define PM_MASTER_WAKEUP_REQ_MASK 0x1U
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#define PM_MASTER_USING_SLAVE_MASK 0x2U
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/* Suspend request related */
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#define PM_REQUESTED_SUSPEND 0x1U
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/* Maximum number of masters currently supported */
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#define PM_MASTER_MAX 3U
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/*********************************************************************
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* Structure definitions
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********************************************************************/
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/**
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* PmRequirement - structure for tracking requirements of a master for the slave
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* setting. One structure should be statically assigned for each
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* possible combination of master/slave, because dynamic memory
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* allocation cannot be used.
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* @slave Pointer to the slave structure
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* @requestor Pointer to the master structure. Can be removed if need to
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* optimize for space instead performance
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* @info Contains information about master's request - a bit for
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* encoding has master requested or released node, and a bit to
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* encode has master requested a wake-up of this slave.
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* @defaultReq Default requirements of a master - requirements for slave
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* capabilities without which master's primary processor cannot
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* switch to active state.
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* @currReq Currently holding requirements of a master for this slave
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* @nextReq Requirements of a master to be configured when it changes the
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* state (after it goes to sleep or before it gets awake)
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*/
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typedef struct PmRequirement {
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PmSlave* const slave;
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PmMaster* const requestor;
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u8 info;
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const u32 defaultReq;
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u32 currReq;
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u32 nextReq;
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} PmRequirement;
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/**
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* PmSuspendRequest() - For tracking information about which master can/has
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* requested which master to suspend.
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* @reqMst Master which is priviledged to request suspend of respMst
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* @flags Flags storing information about the actual request
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* @ackReq Acknowledge argument provided with the request suspend call
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*/
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typedef struct {
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const PmMaster* reqMst;
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u8 flags;
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u32 ackReq;
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} PmSuspendRequest;
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/**
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* PmMaster - contains PM master related informations
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* @procs Pointer to the array of processors within the master
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* @procsCnt Number of processors within the master
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* @nid Placeholder nodeId - used to encode request suspend for group of
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* processors sharing the same communication channel. When PM
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* receives this nid as request suspend argument, it initiates
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* init suspend to the master. At the PU, in init_suspend_cb
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* implementation, the request is mappend to actual suspend of all
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* processors in the PU. In RPU case, this data could be
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* initialized from PCW, based on RPU configuration.
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* @ipiMask Mask dedicated to the master in IPI registers
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* @pmuBuffer IPI buffer address into which PMU can write (PMU's buffer)
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* @buffer IPI buffer address into which this master can write
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* (master's buffer)
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* @reqs Pointer to the masters array of requirements for slave
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* capabilities. For every slave the master can use, there has to
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* be a statically initialized structure for that master/slave pair
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* @reqsCnt Number of requirement elements (= worst case for number of
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* used slaves)
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*/
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typedef struct PmMaster {
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PmProc* const procs;
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const u8 procsCnt;
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PmNodeId nid;
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const u32 ipiMask;
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const u32 pmuBuffer;
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const u32 buffer;
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PmRequirement* const reqs;
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PmSuspendRequest pmSuspRequests;
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const PmRequirementId reqsCnt;
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} PmMaster;
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/*********************************************************************
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* Global data declarations
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********************************************************************/
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extern PmMaster pmMasterApu_g;
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extern PmMaster pmMasterRpu0_g;
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extern PmMaster pmMasterRpu1_g;
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extern PmMaster *const pmAllMasters[PM_MASTER_MAX];
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extern PmRequirement pmApuReq_g[PM_MASTER_APU_SLAVE_MAX];
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extern PmRequirement pmRpu0Req_g[PM_MASTER_RPU_0_SLAVE_MAX];
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/*********************************************************************
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* Function declarations
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********************************************************************/
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/* Get functions */
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const PmMaster* PmGetMasterByIpiMask(const u32 mask);
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PmProc* PmGetProcByWfiStatus(const u32 mask);
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PmProc* PmGetProcByWakeStatus(const u32 mask);
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PmProc* PmGetProcByNodeId(const PmNodeId nodeId);
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PmProc* PmGetProcOfThisMaster(const PmMaster* const master,
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const PmNodeId nodeId);
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PmProc* PmGetProcOfOtherMaster(const PmMaster* const master,
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const PmNodeId nodeId);
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PmRequirement* PmGetRequirementForSlave(const PmMaster* const master,
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const PmNodeId nodeId);
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/* Requirements related functions */
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int PmRequirementSchedule(PmRequirement* const masterReq, const u32 caps);
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int PmRequirementUpdate(PmRequirement* const masterReq, const u32 caps);
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/* Notify master by a primary core when changing state */
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int PmMasterNotify(PmMaster* const master, const PmProcEvent event);
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/* Call at initialization to enable all masters' IPI interrupts */
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void PmEnableAllMasterIpis(void);
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/* Call when FPD goes down to enable GIC Proxy interrupts */
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void PmEnableProxyWake(PmMaster* const master);
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bool PmCanRequestSuspend(const PmMaster* const reqMaster,
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const PmMaster* const respMaster);
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bool PmIsRequestedToSuspend(const PmMaster* const master);
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int PmRememberSuspendRequest(const PmMaster* const reqMaster,
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PmMaster* const respMaster,
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const u32 ack);
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int PmMasterSuspendAck(PmMaster* const respMaster,
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const int response);
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PmMaster* PmMasterGetPlaceholder(const PmNodeId nodeId);
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#endif
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