326 lines
13 KiB
C
Executable file
326 lines
13 KiB
C
Executable file
/* $Id: xcan_l.h,v 1.1.2.1 2009/12/02 11:23:42 svemula Exp $ */
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/******************************************************************************
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*
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* (c) Copyright 2005-2009 Xilinx, Inc. All rights reserved.
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*
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* This file contains confidential and proprietary information of Xilinx, Inc.
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* and is protected under U.S. and international copyright and other
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* intellectual property laws.
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*
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* DISCLAIMER
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* This disclaimer is not a license and does not grant any rights to the
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* materials distributed herewith. Except as otherwise provided in a valid
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* license issued to you by Xilinx, and to the maximum extent permitted by
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* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
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* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
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* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
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* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
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* and (2) Xilinx shall not be liable (whether in contract or tort, including
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* negligence, or under any other theory of liability) for any loss or damage
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* of any kind or nature related to, arising under or in connection with these
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* materials, including for any direct, or any indirect, special, incidental,
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* or consequential loss or damage (including loss of data, profits, goodwill,
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* or any type of loss or damage suffered as a result of any action brought by
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* a third party) even if such damage or loss was reasonably foreseeable or
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* Xilinx had been advised of the possibility of the same.
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*
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* CRITICAL APPLICATIONS
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* Xilinx products are not designed or intended to be fail-safe, or for use in
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* any application requiring fail-safe performance, such as life-support or
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* safety devices or systems, Class III medical devices, nuclear facilities,
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* applications related to the deployment of airbags, or any other applications
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* that could lead to death, personal injury, or severe property or
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* environmental damage (individually and collectively, "Critical
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* Applications"). Customer assumes the sole risk and liability of any use of
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* Xilinx products in Critical Applications, subject only to applicable laws
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* and regulations governing limitations on product liability.
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*
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* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
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* AT ALL TIMES.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xcan_l.h
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*
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* This header file contains the identifiers and basic driver functions (or
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* macros) that can be used to access the device. Other driver functions
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* are defined in xcan.h.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.00a xd 04/12/05 First release
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* 1.10a mta 05/13/07 Updated to new coding style
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* 2.00a ktn 10/22/09 Updated to use the HAL APIs/macros.
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* The macros have been renamed to remove _m from the name.
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*
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* </pre>
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*
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******************************************************************************/
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#ifndef XCAN_L_H /* prevent circular inclusions */
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#define XCAN_L_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xil_io.h"
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/************************** Constant Definitions *****************************/
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/** @name Register offsets for the CAN. Each register is 32 bits.
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* @{
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*/
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#define XCAN_SRR_OFFSET 0x000 /**< Software Reset Register */
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#define XCAN_MSR_OFFSET 0x004 /**< Mode Select Register */
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#define XCAN_BRPR_OFFSET 0x008 /**< Baud Rate Prescaler Register */
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#define XCAN_BTR_OFFSET 0x00C /**< Bit Timing Register */
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#define XCAN_ECR_OFFSET 0x010 /**< Error Counter Register */
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#define XCAN_ESR_OFFSET 0x014 /**< Error Status Register */
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#define XCAN_SR_OFFSET 0x018 /**< Status Register */
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#define XCAN_ISR_OFFSET 0x01C /**< Interrupt Status Register */
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#define XCAN_IER_OFFSET 0x020 /**< Interrupt Enable Register */
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#define XCAN_ICR_OFFSET 0x024 /**< Interrupt Clear Register */
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#define XCAN_TXFIFO_ID_OFFSET 0x030 /**< TX FIFO ID */
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#define XCAN_TXFIFO_DLC_OFFSET 0x034 /**< TX FIFO DLC */
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#define XCAN_TXFIFO_DW1_OFFSET 0x038 /**< TX FIFO Data Word 1 */
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#define XCAN_TXFIFO_DW2_OFFSET 0x03C /**< TX FIFO Data Word 2 */
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#define XCAN_TXBUF_ID_OFFSET 0x040 /**< TX High Priority Buffer ID */
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#define XCAN_TXBUF_DLC_OFFSET 0x044 /**< TX High Priority Buffer DLC */
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#define XCAN_TXBUF_DW1_OFFSET 0x048 /**< TX High Priority Buf Data Word 1 */
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#define XCAN_TXBUF_DW2_OFFSET 0x04C /**< TX High Priority Buf Data Word 2 */
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#define XCAN_RXFIFO_ID_OFFSET 0x050 /**< RX FIFO ID */
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#define XCAN_RXFIFO_DLC_OFFSET 0x054 /**< RX FIFO DLC */
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#define XCAN_RXFIFO_DW1_OFFSET 0x058 /**< RX FIFO Data Word 1 */
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#define XCAN_RXFIFO_DW2_OFFSET 0x05C /**< RX FIFO Data Word 2 */
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#define XCAN_AFR_OFFSET 0x060 /**< Acceptance Filter Register */
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#define XCAN_AFMR1_OFFSET 0x064 /**< Acceptance Filter Mask Register 1 */
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#define XCAN_AFIR1_OFFSET 0x068 /**< Acceptance Filter ID Register 1 */
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#define XCAN_AFMR2_OFFSET 0x06C /**< Acceptance Filter Mask Register 2 */
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#define XCAN_AFIR2_OFFSET 0x070 /**< Acceptance Filter ID Register 2 */
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#define XCAN_AFMR3_OFFSET 0x074 /**< Acceptance Filter Mask Register 3 */
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#define XCAN_AFIR3_OFFSET 0x078 /**< Acceptance Filter ID Register 3 */
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#define XCAN_AFMR4_OFFSET 0x07C /**< Acceptance Filter Mask Register 4 */
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#define XCAN_AFIR4_OFFSET 0x080 /**< Acceptance Filter ID Register 4 */
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/* @} */
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/** @name Software Reset Register
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* @{
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*/
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#define XCAN_SRR_CEN_MASK 0x00000002 /**< Can Enable Mask */
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#define XCAN_SRR_SRST_MASK 0x00000001 /**< Reset Mask */
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/* @} */
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/** @name Mode Select Register
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* @{
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*/
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#define XCAN_MSR_LBACK_MASK 0x00000002 /**< Loop Back Mode Select Mask */
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#define XCAN_MSR_SLEEP_MASK 0x00000001 /**< Sleep Mode Select Mask */
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/* @} */
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/** @name Baud Rate Prescaler register
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* @{
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*/
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#define XCAN_BRPR_BRP_MASK 0x000000FF /**< Baud Rate Prescaler Mask */
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/* @} */
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/** @name Bit Timing Register
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* @{
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*/
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#define XCAN_BTR_SJW_MASK 0x00000180 /**< Sync Jump Width Mask */
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#define XCAN_BTR_SJW_SHIFT 7 /**< Sync Jump Width Shift */
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#define XCAN_BTR_TS2_MASK 0x00000070 /**< Time Segment 2 Mask */
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#define XCAN_BTR_TS2_SHIFT 4 /**< Time Segment 2 Shift */
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#define XCAN_BTR_TS1_MASK 0x0000000F /**< Time Segment 1 Mask */
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/* @} */
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/** @name Error Counter Register
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* @{
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*/
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#define XCAN_ECR_REC_MASK 0x0000FF00 /**< Receive Error Counter Mask */
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#define XCAN_ECR_REC_SHIFT 8 /**< Receive Error Counter Shift */
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#define XCAN_ECR_TEC_MASK 0x000000FF /**< Transmit Error Counter Mask */
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/* @} */
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/** @name Error Status Register
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* @{
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*/
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#define XCAN_ESR_ACKER_MASK 0x00000010 /**< ACK Error Mask */
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#define XCAN_ESR_BERR_MASK 0x00000008 /**< Bit Error Mask */
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#define XCAN_ESR_STER_MASK 0x00000004 /**< Stuff Error Mask */
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#define XCAN_ESR_FMER_MASK 0x00000002 /**< Form Error Mask */
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#define XCAN_ESR_CRCER_MASK 0x00000001 /**< CRC Error Mask */
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/* @} */
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/** @name Status Register
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* @{
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*/
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#define XCAN_SR_ACFBSY_MASK 0x00000800 /**< Acceptance Filter busy Mask */
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#define XCAN_SR_TXFLL_MASK 0x00000400 /**< TX FIFO is full Mask */
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#define XCAN_SR_TXBFLL_MASK 0x00000200 /**< TX High Priority Buffer full */
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#define XCAN_SR_ESTAT_MASK 0x00000180 /**< Error Status Mask */
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#define XCAN_SR_ESTAT_SHIFT 7 /**< Error Status Shift */
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#define XCAN_SR_ERRWRN_MASK 0x00000040 /**< Error Warning Mask */
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#define XCAN_SR_BBSY_MASK 0x00000020 /**< Bus Busy Mask */
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#define XCAN_SR_BIDLE_MASK 0x00000010 /**< Bus Idle Mask */
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#define XCAN_SR_NORMAL_MASK 0x00000008 /**< Normal Mode Mask */
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#define XCAN_SR_SLEEP_MASK 0x00000004 /**< Sleep Mode Mask */
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#define XCAN_SR_LBACK_MASK 0x00000002 /**< Loop Back Mode Mask */
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#define XCAN_SR_CONFIG_MASK 0x00000001 /**< Configuration Mode Mask */
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/* @} */
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/** @name Interrupt Status/Enable/Clear Register
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* @{
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*/
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#define XCAN_IXR_WKUP_MASK 0x00000800 /**< Wake up Interrupt Mask */
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#define XCAN_IXR_SLP_MASK 0x00000400 /**< Sleep Interrupt Mask */
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#define XCAN_IXR_BSOFF_MASK 0x00000200 /**< Bus Off Interrupt Mask */
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#define XCAN_IXR_ERROR_MASK 0x00000100 /**< Error Interrupt Mask */
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#define XCAN_IXR_RXNEMP_MASK 0x00000080 /**< RX FIFO Not Empty Intr Mask */
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#define XCAN_IXR_RXOFLW_MASK 0x00000040 /**< RX FIFO Overflow Intr Mask */
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#define XCAN_IXR_RXUFLW_MASK 0x00000020 /**< RX FIFO Underflow Intr Mask */
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#define XCAN_IXR_RXOK_MASK 0x00000010 /**< New Message Received Intr */
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#define XCAN_IXR_TXBFLL_MASK 0x00000008 /**< TX High Priority Buf Full */
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#define XCAN_IXR_TXFLL_MASK 0x00000004 /**< TX FIFO Full Interrupt Mask */
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#define XCAN_IXR_TXOK_MASK 0x00000002 /**< TX Successful Interrupt Mask */
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#define XCAN_IXR_ARBLST_MASK 0x00000001 /**< Arbitration Lost Intr Mask */
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#define XCAN_IXR_ALL (XCAN_IXR_WKUP_MASK | \
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XCAN_IXR_SLP_MASK | \
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XCAN_IXR_BSOFF_MASK | \
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XCAN_IXR_ERROR_MASK | \
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XCAN_IXR_RXNEMP_MASK | \
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XCAN_IXR_RXOFLW_MASK | \
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XCAN_IXR_RXUFLW_MASK | \
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XCAN_IXR_RXOK_MASK | \
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XCAN_IXR_TXBFLL_MASK | \
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XCAN_IXR_TXFLL_MASK | \
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XCAN_IXR_TXOK_MASK | \
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XCAN_IXR_ARBLST_MASK)
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/* @} */
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/** @name CAN Frame Identifier (TX High Priority Buffer/TX/RX/Acceptance Filter
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Mask/Acceptance Filter ID)
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* @{
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*/
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#define XCAN_IDR_ID1_MASK 0xFFE00000 /**< Standard Messg Ident Mask */
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#define XCAN_IDR_ID1_SHIFT 21 /**< Standard Messg Ident Shift */
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#define XCAN_IDR_SRR_MASK 0x00100000 /**< Substitute Remote TX Req */
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#define XCAN_IDR_SRR_SHIFT 20
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#define XCAN_IDR_IDE_MASK 0x00080000 /**< Identifier Extension Mask */
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#define XCAN_IDR_IDE_SHIFT 19 /**< Identifier Extension Shift */
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#define XCAN_IDR_ID2_MASK 0x0007FFFE /**< Extended Message Ident Mask */
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#define XCAN_IDR_ID2_SHIFT 1 /**< Extended Message Ident Shift */
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#define XCAN_IDR_RTR_MASK 0x00000001 /**< Remote TX Request Mask */
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/* @} */
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/** @name CAN Frame Data Length Code (TX High Priority Buffer/TX/RX)
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* @{
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*/
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#define XCAN_DLCR_DLC_MASK 0xF0000000 /**< Data Length Code Mask */
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#define XCAN_DLCR_DLC_SHIFT 28 /**< Data Length Code Shift */
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/* @} */
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/** @name CAN Frame Data Word 1 (TX High Priority Buffer/TX/RX)
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* @{
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*/
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#define XCAN_DW1R_DB0_MASK 0xFF000000 /**< Data Byte 0 Mask */
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#define XCAN_DW1R_DB0_SHIFT 24 /**< Data Byte 0 Shift */
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#define XCAN_DW1R_DB1_MASK 0x00FF0000 /**< Data Byte 1 Mask */
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#define XCAN_DW1R_DB1_SHIFT 16 /**< Data Byte 1 Shift */
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#define XCAN_DW1R_DB2_MASK 0x0000FF00 /**< Data Byte 2 Mask */
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#define XCAN_DW1R_DB2_SHIFT 8 /**< Data Byte 2 Shift */
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#define XCAN_DW1R_DB3_MASK 0x000000FF /**< Data Byte 3 Mask */
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/* @} */
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/** @name CAN Frame Data Word 2 (TX High Priority Buffer/TX/RX)
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* @{
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*/
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#define XCAN_DW2R_DB4_MASK 0xFF000000 /**< Data Byte 4 Mask */
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#define XCAN_DW2R_DB4_SHIFT 24 /**< Data Byte 4 Shift */
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#define XCAN_DW2R_DB5_MASK 0x00FF0000 /**< Data Byte 5 Mask */
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#define XCAN_DW2R_DB5_SHIFT 16 /**< Data Byte 5 Shift */
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#define XCAN_DW2R_DB6_MASK 0x0000FF00 /**< Data Byte 6 Mask */
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#define XCAN_DW2R_DB6_SHIFT 8 /**< Data Byte 6 Shift */
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#define XCAN_DW2R_DB7_MASK 0x000000FF /**< Data Byte 7 */
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/* @} */
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/** @name Acceptance Filter Register
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* @{
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*/
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#define XCAN_AFR_UAF4_MASK 0x00000008 /**< Use Acceptance Filter No.4 */
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#define XCAN_AFR_UAF3_MASK 0x00000004 /**< Use Acceptance Filter No.3 */
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#define XCAN_AFR_UAF2_MASK 0x00000002 /**< Use Acceptance Filter No.2 */
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#define XCAN_AFR_UAF1_MASK 0x00000001 /**< Use Acceptance Filter No.1 */
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#define XCAN_AFR_UAF_ALL_MASK (XCAN_AFR_UAF4_MASK | XCAN_AFR_UAF3_MASK | \
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XCAN_AFR_UAF2_MASK | XCAN_AFR_UAF1_MASK)
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/* @} */
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/** @name CAN frame length constants
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* @{
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*/
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#define XCAN_MAX_FRAME_SIZE 16 /**< Maximum CAN frame length in bytes */
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/* @} */
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/****************************************************************************/
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/**
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*
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* This macro reads the given register.
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*
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* @param BaseAddress is the base address of the device
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* @param RegOffset is the register offset to be read
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*
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* @return The 32-bit value of the register
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*
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* @note C-Style signature:
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* u32 XCan_ReadReg(u32 BaseAddress, u32 RegOffset);
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*
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*****************************************************************************/
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#define XCan_ReadReg(BaseAddress, RegOffset) \
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Xil_In32((BaseAddress) + (RegOffset))
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/****************************************************************************/
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/**
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*
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* This macro writes the given register.
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*
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* @param BaseAddress is the base address of the device
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* @param RegOffset is the register offset to be written
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* @param Data is the 32-bit value to write to the register
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*
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* @return None.
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*
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* @note C-Style signature:
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* u32 XCan_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data);
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*
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*****************************************************************************/
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#define XCan_WriteReg(BaseAddress, RegOffset, Data) \
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Xil_Out32((BaseAddress) + (RegOffset), (Data))
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/************************** Function Prototypes ******************************/
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#ifdef __cplusplus
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}
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#endif
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#endif /* end of protection macro */
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