2c8f92039d
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
709 lines
26 KiB
C
Executable file
709 lines
26 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2005 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xllfifo.h
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*
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* The Xilinx Dual Channel Fifo driver component. This driver supports the
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* Virtex-5(TM) and Virtex-4(TM) XPS_ll_Fifo and the AxiFifo.
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*
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* For a full description of the bridge features, please see the HW spec. This
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* driver supports the following features:
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* - Memory mapped access to host interface registers
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* - API for polled frame transfers
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* - API for interrupt driven frame transfers
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* - Virtual memory support
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* - Full duplex operation
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*
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* <h2>Driver Description</h2>
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*
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* This driver enables higher layer software to access the XPS_llFifo core
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* using any alignment in the data buffers.
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*
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* This driver supports send and receive channels in the same instance
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* structure in the same fashion as the hardware core.
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*
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* <h2>Initialization</h2>
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*
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* An instance of this driver is initialized using a call to Initialize().
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*
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* <h2>Usage</h2>
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*
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* It is fairly simple to use the API provided by this FIFO driver. The
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* only somewhat tricky part is that the calling code must correctly call
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* a couple routines in the right sequence for receive and transmit.
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*
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* This sequence is described here. Check the routine functional
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* descriptions for information on how to use a specific API routine.
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*
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* <h3>Receive</h3>
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*
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* A frame is received by using the following sequence:<br>
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* 1) call XLlFifo_RxOccupancy() to check the occupancy count<br>
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* 2) call XLlFifo_RxGetLen() to get the length of the next incoming frame<br>
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* 3) call XLlFifo_Read() one or more times to read the number of bytes
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* reported by XLlFifo_RxGetLen().<br>
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*
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* For example:
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* <pre>
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* while (XLlFifo_RxOccupancy(&RxInstance)) {
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* frame_len = XLlFifo_RxGetLen(&RxInstance);
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* while (frame_len) {
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* unsigned bytes = min(sizeof(buffer), frame_len);
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* XLlFifo_Read(&RxInstance, buffer, bytes);
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* // ********
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* // do something with buffer here
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* // ********
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* frame_len -= bytes;
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* }
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* }
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* </pre>
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*
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* This FIFO hardware core does <b>not</b> support a sequence where the
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* calling code calls RxGetLen() twice in a row and then receive the data
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* for two frames. Each frame must be read in by calling RxGetLen() just
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* prior to reading the data.
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*
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* <h3>Transmit</h3>
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* A frame is transmittted by using the following sequence:<br>
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* 1) call XLlFifo_Write() one or more times to write all the of bytes in
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* the next frame.<br>
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* 2) call XLlFifo_TxSetLen() to begin the transmission of frame just
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* written.<br>
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*
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* For example:
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* <pre>
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* frame_left = frame_len;
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* while (frame_left) {
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* unsigned bytes = min(sizeof(buffer), frame_left);
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* XLlFifo_Write(&TxInstance, buffer, bytes);
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* // ********
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* // do something here to refill buffer
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* // ********
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* frame_left -= bytes;
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* }
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* XLlFifo_TxSetLen(&RxInstance, frame_len);
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* </pre>
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*
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* This FIFO hardware core does <b>not</b> support a sequence where the
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* calling code writes the data for two frames and then calls TxSetLen()
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* twice in a row. Each frame must be written by writting the data for one
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* frame and then calling TxSetLen().
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*
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* <h2>Interrupts</h2>
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* This driver does not handle interrupts from the FIFO hardware. The
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* software layer above may make use of the interrupts by setting up its
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* own handlers for the interrupts.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a jvb 10/12/06 First release
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* 1.01a sdm 08/22/08 Removed support for static interrupt handlers from the
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* MDD file
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* 1.02a jz 12/04/09 Hal phase 1 support
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* 2.01a asa 09/17/10 Added code for resetting Local Link/AXI Streaming
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* interface for CR574868
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* 2.02a asa 12/27/11 Changed the function XStrm_Read in xtreamer.c to reset
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* HeadIndex to zero when all bytes have been read.
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* Changed the macro XStrm_IsRxInternalEmpty in file
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* xtreamer.h to use FrmByteCnt instead of HeadIndex.
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* When FrmByteCnt is zero, this means all internal buffers
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* in streamer are empty. Earlier implementation using
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* HeadIndex was not very clear and could give improper
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* results for some cases.
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* Changed the macro XLlFifo_IsRxEmpty in file xllfifo.h
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* These changes are done to fix the CR 604650.
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* 2.03a asa 14/08/12 Added XLLF_TDR_OFFSET, XLLF_RDR_OFFSET
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* defines for the new registers, and XLLF_INT_TFPF_MASK,
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* XLLF_INT_TFPE_MASK, XLLF_INT_RFPF_MASK and
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* XLLF_INT_RFPE_MASK for the new version of the
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* AXI4-Stream FIFO core (v2.01a and later)
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*
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* 3.00a adk 08/10/13 Added support for AXI4 Datainterface.Changes are
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* In Xllfifo.c file XLlFifo_RxGetWord,XLlFifo_TxPutword.
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* In XLlfifo.h file updated XLlfifo structure for
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* Axi4BaseAddress and for Datainterface type provided
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* polling and interrupt examples. XLlfifo_IsRxDone Macro
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* Is added in the XLlfifo.h file for polledmode exmaple.
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* Added Static initialzation for the driver.
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* XLlFifo_Initialize is still used to make the driver
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* backward compatible.
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* 4.0 adk 19/12/13 Updated as per the New Tcl API's
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*
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* </pre>
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*
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*****************************************************************************/
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#ifndef XLLFIFO_H /* prevent circular inclusions */
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#define XLLFIFO_H /* by using preprocessor symbols */
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/* force C linkage */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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/* This order needs to be kept this way to avoid xstatus/xil_types conflict */
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#include "xstreamer.h"
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#include "xllfifo_hw.h"
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/**************************** Type Definitions *******************************/
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/**
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* This typedef defines a run-time instance of an XLlFifo device.
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*/
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typedef struct XLlFifo {
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u32 BaseAddress; /**< BaseAddress is the physical base address of the
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* device's registers
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*/
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u32 IsReady; /**< IsReady is non-zero if the driver instance
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* has been initialized.
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*/
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u32 Axi4BaseAddress; /**< BaseAddress if the FIFO Data interface is
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* AXI4 this address should use for FIFO
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* access
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*/
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u32 Datainterface; /**< Data interface of the FIFO. This value is zero
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* if the Datainterface is AXI4-lite.
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*/
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XStrm_RxFifoStreamer RxStreamer; /**< RxStreamer is the byte streamer
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* instance for the receive channel.
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*/
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XStrm_TxFifoStreamer TxStreamer; /**< TxStreamer is the byte streamer
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* instance for the transmit channel.
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*/
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} XLlFifo;
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typedef struct XLlFifo_Config {
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u32 DeviceId; /**< Deviceid of the AXI FIFO */
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u32 BaseAddress; /**< Base Address of the AXI FIFO */
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u32 Axi4BaseAddress; /**< Axi4 interface Base address */
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u32 Datainterface; /**< Type of Datainterface */
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}XLlFifo_Config;
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/****************************************************************************/
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/**
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*
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* XLlFifo_Reset resets both the Tx and Rx channels and the local link interface
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* the FIFO specified by <i>InstancePtr</i>. XLlFifo_TxReset resets also sends a
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* reset pulse to the downstream device (e.g. TEMAC). XLlFifo_Reset drops any
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* bytes in the FIFO not yet retrieved. XLlFifo_Reset drops any bytes in the FIFO
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* not yet transmitted.
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*
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* @param InstancePtr references the FIFO on which to operate.
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*
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* @return N/A
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*
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* @note
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* C-style signature:
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* void XLlFifo_Reset(XLlFifo *InstancePtr)
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*
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*****************************************************************************/
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#define XLlFifo_Reset(InstancePtr) \
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XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_LLR_OFFSET, \
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XLLF_LLR_RESET_MASK)
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/****************************************************************************/
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/**
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*
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* XLlFifo_Status returns a bit mask of the interrupt status register (ISR)
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* for the FIFO specified by <i>InstancePtr</i>. XLlFifo_Status can be used
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* to query the status of the FIFO without having to have interrupts enabled.
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*
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* @param InstancePtr references the FIFO on which to operate.
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*
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* @return XLlFifo_IntStatus returns a bit mask of the status conditions.
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* The mask will be a set of bitwise or'd values from the
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* <code>XLLF_INT_*_MASK</code> preprocessor symbols.
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*
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* @note
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* C-style signature:
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* u32 XLlFifo_IntStatus(XLlFifo *InstancePtr)
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*
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*****************************************************************************/
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#define XLlFifo_Status(InstancePtr) \
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XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET)
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/****************************************************************************/
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/**
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*
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* XLlFifo_IntEnable enables the interrupts specified in <i>Mask</i> for the
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* FIFO specified by <i>InstancePtr</i>. The corresponding interrupt for each bit
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* set to 1 in <i>Mask</i>, will be enabled.
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*
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* @param InstancePtr references the FIFO on which to operate.
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*
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* @param Mask contains a bit mask of the interrupts to enable. The mask
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* can be formed using a set of bitwise or'd values from the
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* <code>XLLF_INT_*_MASK</code> preprocessor symbols.
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*
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* @return N/A
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*
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* @note
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* C-style signature:
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* void XLlFifo_IntEnable(XLlFifo *InstancePtr, u32 Mask)
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*
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*****************************************************************************/
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#define XLlFifo_IntEnable(InstancePtr, Mask) \
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{ \
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u32 Reg = XLlFifo_ReadReg((InstancePtr)->BaseAddress, \
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XLLF_IER_OFFSET); \
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Reg |= ((Mask) & XLLF_INT_ALL_MASK); \
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XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET, \
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Reg); \
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}
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/****************************************************************************/
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/**
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*
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* XLlFifo_IntDisable disables the interrupts specified in <i>Mask</i> for the
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* FIFO specified by <i>InstancePtr</i>. The corresponding interrupt for each bit
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* set to 1 in <i>Mask</i>, will be disabled. In other words, XLlFifo_IntDisable
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* uses the "set a bit to clear it" scheme.
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*
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* @param InstancePtr references the FIFO on which to operate.
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*
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* @param Mask contains a bit mask of the interrupts to disable. The mask
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* can be formed using a set of bitwise or'd values from the
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* <code>XLLF_INT_*_MASK</code> preprocessor symbols.
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*
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* @return N/A
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*
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* @note
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* C-style signature:
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* void XLlFifo_IntDisable(XLlFifo *InstancePtr, u32 Mask)
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*
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*****************************************************************************/
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#define XLlFifo_IntDisable(InstancePtr, Mask) \
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{ \
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u32 Reg = XLlFifo_ReadReg((InstancePtr)->BaseAddress, \
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XLLF_IER_OFFSET); \
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Reg &= ~((Mask) & XLLF_INT_ALL_MASK); \
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XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET, \
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Reg); \
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}
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/****************************************************************************/
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/**
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*
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* XLlFifo_IntPending returns a bit mask of the pending interrupts for the
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* FIFO specified by <i>InstancePtr</i>. Each bit set to 1 in the return value
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* represents a pending interrupt.
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*
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* @param InstancePtr references the FIFO on which to operate.
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*
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* @return XLlFifo_IntPending returns a bit mask of the interrupts that are
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* pending. The mask will be a set of bitwise or'd values from the
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* <code>XLLF_INT_*_MASK</code> preprocessor symbols.
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*
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* @note
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* C-style signature:
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* u32 XLlFifo_IntPending(XLlFifo *InstancePtr)
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*
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*****************************************************************************/
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#ifdef DEBUG
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extern u32 _xllfifo_ipie_value;
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extern u32 _xllfifo_ipis_value;
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#define XLlFifo_IntPending(InstancePtr) \
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(_xllfifo_ipie_value = XLlFifo_ReadReg( \
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(InstancePtr)->BaseAddress, XLLF_IER_OFFSET), \
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_xllfifo_ipis_value = XLlFifo_ReadReg( \
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(InstancePtr)->BaseAddress, XLLF_ISR_OFFSET), \
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(_xllfifo_ipie_value & _xllfifo_ipis_value))
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#else
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#define XLlFifo_IntPending(InstancePtr) \
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(XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET) & \
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XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET))
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#endif
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/****************************************************************************/
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/**
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*
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* XLlFifo_IntClear clears pending interrupts specified in <i>Mask</i> for the
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* FIFO specified by <i>InstancePtr</i>. The corresponding pending interrupt for
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* each bit set to 1 in <i>Mask</i>, will be cleared. In other words,
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* XLlFifo_IntClear uses the "set a bit to clear it" scheme.
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*
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* @param InstancePtr references the FIFO on which to operate.
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*
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* @param Mask contains a bit mask of the pending interrupts to clear. The
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* mask can be formed using a set of bitwise or'd values from the
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* <code>XLLF_INT_*_MASK</code> preprocessor symbols.
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*
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* @note
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* C-style signature:
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* void XLlFifo_IntClear(XLlFifo *InstancePtr, u32 Mask)
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*
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*****************************************************************************/
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#define XLlFifo_IntClear(InstancePtr, Mask) \
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XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET, \
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((Mask) & XLLF_INT_ALL_MASK))
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/****************************************************************************/
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/**
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*
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* XLlFifo_RxReset resets the receive channel of the FIFO specified by
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* <i>InstancePtr</i>. XLlFifo_RxReset drops any bytes in the FIFO not yet
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* retrieved.
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*
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* The calling software may want to test for the completion of the reset by
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* reading the interrupt status (IS) register and testing for the Rx Reset
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* complete (RRC) bit.
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*
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* @param InstancePtr references the FIFO on which to operate.
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*
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* @return N/A
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*
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* @note
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* C-style signature:
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* void XLlFifo_RxReset(XLlFifo *InstancePtr)
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*
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*****************************************************************************/
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#define XLlFifo_RxReset(InstancePtr) \
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XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_RDFR_OFFSET, \
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XLLF_RDFR_RESET_MASK)
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/****************************************************************************/
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/**
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*
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* XLlFifo_IsRxEmpty returns true if the receive channel of the FIFO, specified
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* by <i>InstancePtr</i>, is empty.
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*
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* @param InstancePtr references the FIFO on which to operate.
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*
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* @return XLlFifo_IsRxEmpty returns TRUE when the receive channel of the
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* FIFO is empty. Otherwise, XLlFifo_IsRxEmpty returns FALSE.
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*
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* @note
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* C-style signature:
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* int XLlFifo_IsRxEmpty(XLlFifo *InstancePtr)
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*
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*****************************************************************************/
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#define XLlFifo_IsRxEmpty(InstancePtr) \
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((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_RDFO_OFFSET) == 0) \
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? TRUE : FALSE)
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/*****************************************************************************/
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/**
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*
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* XLlFifo_RxOccupancy returns the number of 32-bit words available (occupancy) to
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* be read from the receive channel of the FIFO, specified by <i>InstancePtr</i>.
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*
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* The xps_ll_fifo core uses the same fifo to store data values and frame length
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* values. Upon initialization, the XLlFifo_RxOccupancy will give the value of
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* 1, which means one length value (a reserved fifo location) and no data
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* values.
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*
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* @param InstancePtr references the FIFO on which to operate.
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*
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* @return XLlFifo_RxOccupancy returns the occupancy count for the specified
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* packet FIFO.
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*
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* @note
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*
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* C Signature: u32 XLlFifo_RxOccupancy(XLlFifo *InstancePtr)
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*
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******************************************************************************/
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#define XLlFifo_RxOccupancy(InstancePtr) \
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XStrm_RxOccupancy(&((InstancePtr)->RxStreamer))
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/*****************************************************************************/
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/**
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*
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* XLlFifo_RxGetLen notifies the hardware that the program is ready to receive
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* the next frame from the receive channel of the FIFO, specified by
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* <i>InstancePtr</i>.
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*
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* Note that the program must first call XLlFifo_RxGetLen before pulling data
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* out of the receive channel of the FIFO with XLlFifo_Read.
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*
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* @param InstancePtr references the FIFO on which to operate.
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*
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* @return XLlFifo_RxGetLen returns the number of bytes available in the next
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* frame.
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*
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* @note
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*
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* C Signature: u32 XLlFifo_RxGetLen(XLlFifo *InstancePtr)
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|
*
|
|
******************************************************************************/
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|
#define XLlFifo_RxGetLen(InstancePtr) \
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|
XStrm_RxGetLen(&((InstancePtr)->RxStreamer))
|
|
|
|
/*****************************************************************************/
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|
/**
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|
*
|
|
* XLlFifo_Read reads <i>Bytes</i> bytes from the receive channel of the FIFO
|
|
* referenced by <i>InstancePtr</i> to the block of memory, referenced by
|
|
* <i>BufPtr</i>.
|
|
*
|
|
* Care must be taken to ensure that the number of bytes read with one or more
|
|
* calls to XLlFifo_Read() does not exceed the number of bytes available given
|
|
* from the last call to XLlFifo_RxGetLen().
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|
*
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* @param InstancePtr references the FIFO on which to operate.
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|
*
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* @param BufPtr specifies the memory address to place the data read.
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|
*
|
|
* @param Bytes specifies the number of bytes to read.
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|
*
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|
* @return N/A
|
|
*
|
|
* @note
|
|
* Error handling is handled through hardware exceptions and interrupts.
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|
*
|
|
* C Signature: void XLlFifo_Read(XLlFifo *InstancePtr, void *BufPtr, unsigned Bytes)
|
|
*
|
|
******************************************************************************/
|
|
#define XLlFifo_Read(InstancePtr, BufPtr, Bytes) \
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|
XStrm_Read(&((InstancePtr)->RxStreamer), (BufPtr), (Bytes))
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|
|
|
/****************************************************************************/
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|
/**
|
|
*
|
|
* XLlFifo_TxReset resets the transmit channel of the FIFO specified by
|
|
* <i>InstancePtr</i>. XLlFifo_TxReset drops any bytes in the FIFO not yet
|
|
* transmitted.
|
|
*
|
|
* The calling software may want to test for the completion of the reset by
|
|
* reading the interrupt status (IS) register and testing for the Tx Reset
|
|
* complete (TRC) bit.
|
|
*
|
|
* @param InstancePtr references the FIFO on which to operate.
|
|
*
|
|
* @return N/A
|
|
*
|
|
* @note
|
|
* C-style signature:
|
|
* void XLlFifo_TxReset(XLlFifo *InstancePtr)
|
|
*
|
|
*****************************************************************************/
|
|
#define XLlFifo_TxReset(InstancePtr) \
|
|
XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_TDFR_OFFSET, \
|
|
XLLF_TDFR_RESET_MASK)
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
*
|
|
* XLlFifo_IsTxDone returns true if the transmission in the transmit channel
|
|
* of the FIFO, specified by <i>InstancePtr</i>, is complete. XLlFifo_IsTxDone
|
|
* works only if the TC bit in the IS register is cleared before sending a
|
|
* frame.
|
|
*
|
|
* @param InstancePtr references the FIFO on which to operate.
|
|
*
|
|
* @return XLlFifo_IsTxDone returns TRUE when the transmit channel of the
|
|
* FIFO is complete. Otherwise, XLlFifo_IsTxDone returns FALSE.
|
|
*
|
|
* @note
|
|
* C-style signature:
|
|
* int XLlFifo_IsTxDone(XLlFifo *InstancePtr)
|
|
*
|
|
*****************************************************************************/
|
|
#define XLlFifo_IsTxDone(InstancePtr) \
|
|
((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET) & \
|
|
XLLF_INT_TC_MASK) \
|
|
? TRUE : FALSE)
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
*
|
|
* XLlFifo_IsRxDone returns true if the reception in the receive channel
|
|
* of the FIFO, specified by <i>InstancePtr</i>, is complete. XLlFifo_IsRxDone
|
|
* works only if the RC bit in the ISR register is cleared before receiving a
|
|
* frame.
|
|
*
|
|
* @param InstancePtr references the FIFO on which to operate.
|
|
*
|
|
* @return XLlFifo_IsRxDone returns TRUE when the receive channel of the
|
|
* FIFO is complete. Otherwise, XLlFifo_IsRxDone returns FALSE.
|
|
*
|
|
* @note
|
|
* C-style signature:
|
|
* int XLlFifo_IsRxDone(XLlFifo *InstancePtr)
|
|
*
|
|
*****************************************************************************/
|
|
#define XLlFifo_IsRxDone(InstancePtr) \
|
|
((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET) & \
|
|
XLLF_INT_RC_MASK) \
|
|
? TRUE : FALSE)
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
*
|
|
* XLlFifo_TxVacancy returns the number of unused 32 bit words available
|
|
* (vacancy) in the send channel of the FIFO specified by <i>InstancePtr</i>.
|
|
*
|
|
* The xps_ll_fifo core uses tXLLF_he same fifo to store data values and frame length
|
|
* values. Upon initialization, the XLlFifo_TxVacancy will give the value of
|
|
* FIFO_WIDTH - 1, which means one length value used (a reserved fifo location)
|
|
* and no data values yet present.
|
|
*
|
|
* @param InstancePtr references the FIFO on which to operate.
|
|
*
|
|
* @return XLlFifo_TxVacancy returns the vacancy count in 32-bit words for
|
|
* the specified FIFO.
|
|
*
|
|
* @note
|
|
* C-style signature:
|
|
* u32 XLlFifo_TxVacancy(XLlFifo *InstancePtr)
|
|
*
|
|
*****************************************************************************/
|
|
#define XLlFifo_TxVacancy(InstancePtr) \
|
|
XStrm_TxVacancy(&((InstancePtr)->TxStreamer))
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
*
|
|
* XLlFifo_TxSetLen begins a hardware transfer of <i>Bytes</i> bytes out of the
|
|
* transmit channel of the FIFO specified by <i>InstancePtr</i>.
|
|
*
|
|
* @param InstancePtr references the FIFO on which to operate.
|
|
*
|
|
* @param Bytes specifies the frame length in bytes.
|
|
*
|
|
* @return N/A
|
|
*
|
|
* @note
|
|
*
|
|
* C Signature: void XLlFifo_TxSetLen(XLlFifo *InstancePtr, u32 Bytes)
|
|
*
|
|
******************************************************************************/
|
|
#define XLlFifo_TxSetLen(InstancePtr, Bytes) \
|
|
XStrm_TxSetLen(&((InstancePtr)->TxStreamer), (Bytes))
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
*
|
|
* XLlFifo_Write writes <i>Bytes</i> bytes of the block of memory, referenced by
|
|
* <i>BufPtr</i>, to the transmit channel of the FIFO referenced by
|
|
* <i>InstancePtr</i>.
|
|
*
|
|
* Care must be taken to ensure that the number of bytes written with one or
|
|
* more calls to XLlFifo_Write() matches the number of bytes given in the next
|
|
* call to XLlFifo_TxSetLen().
|
|
*
|
|
* @param InstancePtr references the FIFO on which to operate.
|
|
*
|
|
* @param BufPtr specifies the memory address of data to write.
|
|
*
|
|
* @param Bytes specifies the number of bytes to write.
|
|
*
|
|
* @return N/A
|
|
*
|
|
* @note
|
|
* Error handling is handled through hardware exceptions and interrupts.
|
|
*
|
|
* C Signature: void XLlFifo_Write(XLlFifo *InstancePtr, void *BufPtr, unsigned Bytes)
|
|
*
|
|
******************************************************************************/
|
|
#define XLlFifo_Write(InstancePtr, BufPtr, Bytes) \
|
|
XStrm_Write(&((InstancePtr)->TxStreamer), (BufPtr), (Bytes))
|
|
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
*
|
|
* XLlFifo_WriteTdr writes to the Transmit Destination Register (TDR)
|
|
*
|
|
* The TDR stores the destination address corresponding to the packet to be
|
|
* transmitted. When presenting a transmit packet to the AXI4-Stream FIFO core
|
|
* the following sequence should be followed
|
|
* - Write the destination address into TDR first,
|
|
* - Write the packet data to the Transmit Data FIFO next
|
|
* - Write the length of the packet into the Transmit Length Register.
|
|
*
|
|
* @param InstancePtr references the FIFO on which to operate.
|
|
* @param Tdest is the Transmit Destination address to be written to TDR.
|
|
*
|
|
* @return N/A
|
|
*
|
|
* @note C Signature:
|
|
* void XLlFifo_WriteTdr(XLlFifo *InstancePtr, u32 Tdest);
|
|
*
|
|
******************************************************************************/
|
|
#define XLlFifo_WriteTdr(InstancePtr, Tdest) \
|
|
XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_TDR_OFFSET, \
|
|
Tdest & 0xF)
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
*
|
|
* XLlFifo_ReadTdr returns the contents of the Receive Destination Register(RDR).
|
|
*
|
|
* The RDR contains destination address corresponding to the valid packet that
|
|
* is received. The RDR should only be read when a receive packet is available
|
|
* for processing (the receive occupancy is not zero).
|
|
* Once the RDR is read, the receive packet data should be read from the receive
|
|
* data FIFO before the RDR is read again. The RDR values are stored in the
|
|
* receive data FIFO by the AXI4-Stream FIFO core with the data of each packet.
|
|
* The RDR value for the subsequent packet to be processed is moved to the RDR
|
|
* when the previous RDR value has been read.
|
|
*
|
|
* @param InstancePtr references the FIFO on which to operate.
|
|
*
|
|
* @return The Receive Destination address read from the RDR.
|
|
*
|
|
* @note C Signature:
|
|
* u32 XLlFifo_ReadRdr(XLlFifo *InstancePtr)
|
|
*
|
|
******************************************************************************/
|
|
#define XLlFifo_ReadRdr(InstancePtr) \
|
|
XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_RDR_OFFSET)
|
|
|
|
/************************** Function Prototypes ******************************/
|
|
/*
|
|
* Initialization functions xllfifo.c
|
|
*/
|
|
int XLlFifo_CfgInitialize(XLlFifo *InstancePtr,
|
|
XLlFifo_Config *Config, u32 EffectiveAddress);
|
|
void XLlFifo_Initialize(XLlFifo *InstancePtr, u32 BaseAddress);
|
|
XLlFifo_Config *XLlFfio_LookupConfig(u32 DeviceId);
|
|
u32 XLlFifo_iRxOccupancy(XLlFifo *InstancePtr);
|
|
u32 XLlFifo_iRxGetLen(XLlFifo *InstancePtr);
|
|
u32 XLlFifo_iTxVacancy(XLlFifo *InstancePtr);
|
|
void XLlFifo_iTxSetLen(XLlFifo *InstancePtr, u32 Bytes);
|
|
u32 XLlFifo_RxGetWord(XLlFifo *InstancePtr);
|
|
void XLlFifo_TxPutWord(XLlFifo *InstancePtr, u32 Word);
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
#endif /* XLLFIFO_H end of preprocessor protection symbols */
|