2ba225fa69
Change CR_RESET_STATE defintion to include required bits to be set and reset. When writing to the configuration register, read the register and OR the required value to leave the reserved bits untouched. Changes done in XQspiPs_Reset function and HW reset function. The default value written was expanded to include setting hold bit and using manual chip select (This is recommended and already explicitly followed in all the examples). Removed check for register values in selftest because a reset is done in just the previous step where default values are already written. Signed-off-by: Harini Katakam <harinik@xilinx.com> Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
783 lines
32 KiB
C
Executable file
783 lines
32 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xqspips.h
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*
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* This file contains the implementation of the XQspiPs driver. It supports only
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* master mode. User documentation for the driver functions is contained in this
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* file in the form of comment blocks at the front of each function.
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*
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* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
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* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
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* between one master and one slave. The device is always full-duplex,
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* which means that for every byte sent, one is received, and vice-versa.
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* The master controls the clock, so it can regulate when it wants to
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* send or receive data. The slave is under control of the master, it must
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* respond quickly since it has no control of the clock and must send/receive
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* data as fast or as slow as the master does.
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*
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* <b> Linear Mode </b>
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* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller<65>s
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* functionality by adding a linear addressing scheme that allows the SPI flash
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* memory subsystem to behave like a typical ROM device. The new feature hides
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* the normal SPI protocol from a master reading from the SPI flash memory. The
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* feature improves both the user friendliness and the overall read memory
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* throughput over that of the current Quad-SPI Controller by lessening the
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* amount of software overheads required and by the use of the faster AXI
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* interface.
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*
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* <b>Initialization & Configuration</b>
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*
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* The XQspiPs_Config structure is used by the driver to configure itself. This
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* configuration structure is typically created by the tool-chain based on HW
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* build properties.
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*
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* To support multiple runtime loading and initialization strategies employed by
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* various operating systems, the driver instance can be initialized in the
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* following way:
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* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
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* static configuration structure defined in xqspips_g.c. This is setup
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* by the tools. For some operating systems the config structure will be
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* initialized by the software and this call is not needed.
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* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
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* configuration structure provided by the caller. If running in a system
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* with address translation, the provided virtual memory base address
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* replaces the physical address present in the configuration structure.
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*
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* <b>Multiple Masters</b>
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*
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* More than one master can exist, but arbitration is the responsibility of
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* the higher layer software. The device driver does not perform any type of
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* arbitration.
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*
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* <b>Modes of Operation</b>
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*
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* There are four modes to perform a data transfer and the selection of a mode
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* is based on Chip Select(CS) and Start. These two options individually, can
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* be controlled either by software(Manual) or hardware(Auto).
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* - Auto CS: Chip select is automatically asserted as soon as the first word
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* is written into the TXFIFO and de asserted when the TXFIFO becomes
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* empty
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* - Manual CS: Software must assert and de assert CS.
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* - Auto Start: Data transmission starts as soon as there is data in the
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* TXFIFO and stalls when the TXFIFO is empty
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* - Manual Start: Software must start data transmission at the beginning of
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* the transaction or whenever the TXFIFO has become empty
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*
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* The preferred combination is Manual CS and Auto Start.
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* In this combination, the software asserts CS before loading any data into
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* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
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* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
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* data is available. If no further data, software disables CS.
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*
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* Risks/challenges of other combinations:
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* - Manual CS and Manual Start: Manual Start bit should be set after each
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* TXFIFO write otherwise there could be a race condition where the TXFIFO
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* becomes empty before the new word is written. In that case the
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* transmission stops.
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* - Auto CS with Manual or Auto Start: It is very difficult for software to
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* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
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* This results in a single transaction to be split into multiple pieces each
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* with its own chip select. This will result in garbage data to be sent.
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*
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* <b>Interrupts</b>
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*
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* The user must connect the interrupt handler of the driver,
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* XQspiPs_InterruptHandler, to an interrupt system such that it will be
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* called when an interrupt occurs. This function does not save and restore
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* the processor context such that the user must provide this processing.
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*
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* The driver handles the following interrupts:
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* - Data Transmit Register/FIFO Underflow
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* - Data Receive Register/FIFO Not Empty
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* - Data Transmit Register/FIFO Overwater
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* - Data Receive Register/FIFO Overrun
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*
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* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
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* QSPI device has transmitted the data available to transmit, and now its data
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* register and FIFO is ready to accept more data. The driver uses this
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* interrupt to indicate progress while sending data. The driver may have
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* more data to send, in which case the data transmit register and FIFO is
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* filled for subsequent transmission. When this interrupt arrives and all
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* the data has been sent, the driver invokes the status callback with a
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* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
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* all data has been sent.
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*
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* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
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* as slave, the QSPI device was required to transmit but there was no data
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* available to transmit in the transmit register (or FIFO). This may not
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* be an error if the master is not expecting data. But in the case where
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* the master is expecting data, this serves as a notification of such a
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* condition. The driver reports this condition to the upper layer
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* software through the status handler.
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*
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* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
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* device received data and subsequently dropped the data because the data
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* receive register and FIFO was full. The driver reports this condition to the
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* upper layer software through the status handler. This likely indicates a
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* problem with the higher layer protocol, or a problem with the slave
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* performance.
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*
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*
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* <b>Polled Operation</b>
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*
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* Transfer in polled mode is supported through a separate interface function
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* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
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* this function blocks until all data has been sent/received.
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*
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* <b>Device Busy</b>
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*
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* Some operations are disallowed when the device is busy. The driver tracks
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* whether a device is busy. The device is considered busy when a data transfer
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* request is outstanding, and is considered not busy only when that transfer
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* completes (or is aborted with a mode fault error).
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*
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* <b>Device Configuration</b>
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*
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* The device can be configured in various ways during the FPGA implementation
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* process. Configuration parameters are stored in the xqspips_g.c file or
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* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
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* contains configuration information for an QSPI device, including the base
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* address for the device.
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*
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* <b>RTOS Independence</b>
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*
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* This driver is intended to be RTOS and processor independent. It works with
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* physical addresses only. Any needs for dynamic memory management, threads or
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* thread mutual exclusion, virtual memory, or cache control must be satisfied
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* by the layer above this driver.
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*
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* NOTE: This driver was always tested with endianess set to little-endian.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- --- -------- -----------------------------------------------
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* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
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* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
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* in xparameters.h
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* 2.00a kka 07/25/12 Added a few register defines for CR 670297
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* Removed code related to mode fault for CR 671468
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* The XQspiPs_SetSlaveSelect has been modified to remove
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* the argument of the slave select as the QSPI controller
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* only supports one slave.
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* XQspiPs_GetSlaveSelect API has been removed
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* Added a flag ShiftReadData to the instance structure
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*. and is used in the XQspiPs_GetReadData API.
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* The ShiftReadData Flag indicates whether the data
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* read from the Rx FIFO needs to be shifted
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* in cases where the data is less than 4 bytes
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* Removed the selection for the following options:
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* Master mode (XQSPIPS_MASTER_OPTION) and
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* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
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* as the QSPI driver supports the Master mode
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* and Flash Interface mode and doesnot support
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* Slave mode or the legacy mode.
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* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
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* APIs so that the last argument (IsInst) specifying whether
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* it is instruction or data has been removed. The first byte
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* in the SendBufPtr argument of these APIs specify the
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* instruction to be sent to the Flash Device.
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* This version of the driver fixes CRs 670197/663787/
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* 670297/671468.
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* Added the option for setting the Holdb_dr bit in the
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* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
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* is the option to be used for setting this bit in the
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* configuration register.
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* The XQspiPs_PolledTransfer function has been updated
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* to fill the data to fifo depth.
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* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
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* Added macros for Set/Get Rx Watermark. Changed QSPI
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* Enable/Disable macro argument from BaseAddress to
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* Instance Pointer. Added DelayNss argument to SetDelays
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* and GetDelays API's.
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* Created macros XQspiPs_IsManualStart and
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* XQspiPs_IsManualChipSelect.
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* Changed QSPI transfer logic for polled and interrupt
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* modes to be based on filled tx fifo count and receive
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* based on it. RXNEMPTY interrupt is not used.
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* Added assertions to XQspiPs_LqspiRead function.
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* SetDelays and GetDelays API's include DelayNss parameter.
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* Added defines for DelayNss,Rx Watermark,Interrupts
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* which need write to clear. Removed Read zeros mask from
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* LQSPI Config register. Renamed Fixed burst error to
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* data FSM error in LQSPI Status register.
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*
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* 2.02a hk 05/07/13 Added ConnectionMode to config structure.
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* Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
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* Added enable and disable to the XQspiPs_LqspiRead() function
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* Removed XQspi_Reset() in Set_Options() function when
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* LQSPI_MODE_OPTION is set.
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* Added instructions for bank selection, die erase and
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* flag status register to the flash instruction table
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* Handling for instructions not in flash instruction
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* table added. Checking for Tx FIFO empty when switching from
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* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
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* byte count 3 (spansion), instruction size and TXD register
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* changed accordingly. CR# 712502 and 703869.
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* Added prefix to constant definitions for ConnectionMode
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* Added (#ifdef linear base address) in the Linear read function.
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* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
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* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
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* XQspiPs_LqspiRead function. Fix for CR#718141.
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*
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* 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of
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* thresholds. This is to improve performance.
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* Added API's for QSPI reset and
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* linear mode initialization for boot.
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* Added RX and TX threshold reset to one in XQspiPs_Abort.
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* Added RX threshold reset(1) after transfer in polled and
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* interrupt transfers. Made changes to make sure threshold
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* change is done only when no transfer is in progress.
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* Updated linear init API for parallel and stacked modes.
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* CR#737760.
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* 3.1 hk 06/19/14 When writng configuration register, set/reset
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* required bits leaving reserved bits untouched. CR# 796813.
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*
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* </pre>
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*
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******************************************************************************/
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#ifndef XQSPIPS_H /* prevent circular inclusions */
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#define XQSPIPS_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xstatus.h"
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#include "xqspips_hw.h"
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#include <string.h>
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/************************** Constant Definitions *****************************/
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/** @name Configuration options
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*
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* The following options are supported to enable/disable certain features of
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* an QSPI device. Each of the options is a bit mask, so more than one may be
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* specified.
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*
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*
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* The <b>Active Low Clock option</b> configures the device's clock polarity.
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* Setting this option means the clock is active low and the SCK signal idles
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* high. By default, the clock is active high and SCK idles low.
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*
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* The <b>Clock Phase option</b> configures the QSPI device for one of two
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* transfer formats. A clock phase of 0, the default, means data is valid on
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* the first SCK edge (rising or falling) after the slave select (SS) signal
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* has been asserted. A clock phase of 1 means data is valid on the second SCK
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* edge (rising or falling) after SS has been asserted.
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*
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*
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* The <b>QSPI Force Slave Select option</b> is used to enable manual control of
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* the slave select signal.
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* 0: The SPI_SS signal is controlled by the QSPI controller during
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* transfers. (Default)
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* 1: The SPI_SS signal is forced active (driven low) regardless of any
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* transfers in progress.
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*
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* NOTE: The driver will handle setting and clearing the Slave Select when
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* the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
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* QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
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* processor cannot empty and refill the FIFOs before the TX FIFO is empty
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* When the QSPI hardware is controlling the Slave Select signals, this
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* will cause slave to be de-selected and terminate the transfer.
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*
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* The <b>Manual Start option</b> is used to enable manual control of
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* the Start command to perform data transfer.
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* 0: The Start command is controlled by the QSPI controller during
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* transfers(Default). Data transmission starts as soon as there is data in
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* the TXFIFO and stalls when the TXFIFO is empty
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* 1: The Start command must be issued by software to perform data transfer.
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* Bit 15 of Configuration register is used to issue Start command. This bit
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* must be set whenever TXFIFO is filled with new data.
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*
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* NOTE: The driver will set the Manual Start Enable bit in Configuration
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* Register, if Manual Start option is selected. Software will issue
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* Manual Start command whenever TXFIFO is filled with data. When there is
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* no further data, driver will clear the Manual Start Enable bit.
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*
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* @{
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*/
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#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */
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#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */
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#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */
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#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */
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#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */
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#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */
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/*@}*/
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/** @name QSPI Clock Prescaler options
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* The QSPI Clock Prescaler Configuration bits are used to program master mode
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* bit rate. The bit rate can be programmed in divide-by-two decrements from
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* pclk/2 to pclk/256.
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*
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* @{
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*/
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#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */
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#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */
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#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */
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#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */
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#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */
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#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */
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#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */
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#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */
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/*@}*/
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/** @name Callback events
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*
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* These constants specify the handler events that are passed to
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* a handler from the driver. These constants are not bit masks such that
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* only one will be passed at a time to the handler.
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*
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* @{
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*/
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#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */
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#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
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#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because
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RX FIFO full */
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/*@}*/
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/** @name Flash commands
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*
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* The following constants define most of the commands supported by flash
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* devices. Users can add more commands supported by the flash devices
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*
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* @{
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*/
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#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */
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#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */
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#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */
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#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */
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#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */
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#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */
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#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */
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#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */
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#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */
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#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */
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#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */
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#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */
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#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */
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#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */
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#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */
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#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */
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#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/
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||
#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
|
||
#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
|
||
#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */
|
||
#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */
|
||
/* Extende Address Register Write - Micron's equivalent of Bank Register */
|
||
#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5
|
||
/* Extende Address Register Read - Micron's equivalent of Bank Register */
|
||
#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8
|
||
#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4
|
||
#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70
|
||
#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50
|
||
#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock register Read */
|
||
#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Register Write */
|
||
|
||
/*@}*/
|
||
|
||
/** @name Instruction size
|
||
*
|
||
* The following constants define numbers 1 to 4.
|
||
* Used to identify whether TXD0,1,2 or 3 is to be used.
|
||
*
|
||
* @{
|
||
*/
|
||
#define XQSPIPS_SIZE_ONE 1
|
||
#define XQSPIPS_SIZE_TWO 2
|
||
#define XQSPIPS_SIZE_THREE 3
|
||
#define XQSPIPS_SIZE_FOUR 4
|
||
|
||
/*@}*/
|
||
|
||
/** @name ConnectionMode
|
||
*
|
||
* The following constants are the possible values of ConnectionMode in
|
||
* Config structure.
|
||
*
|
||
* @{
|
||
*/
|
||
#define XQSPIPS_CONNECTION_MODE_SINGLE 0
|
||
#define XQSPIPS_CONNECTION_MODE_STACKED 1
|
||
#define XQSPIPS_CONNECTION_MODE_PARALLEL 2
|
||
|
||
/*@}*/
|
||
|
||
/** @name FIFO threshold value
|
||
*
|
||
* This is the Rx FIFO threshold (in words) that was found to be most
|
||
* optimal in terms of performance
|
||
*
|
||
* @{
|
||
*/
|
||
#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32
|
||
|
||
/*@}*/
|
||
|
||
/**************************** Type Definitions *******************************/
|
||
/**
|
||
* The handler data type allows the user to define a callback function to
|
||
* handle the asynchronous processing for the QSPI device. The application
|
||
* using this driver is expected to define a handler of this type to support
|
||
* interrupt driven mode. The handler executes in an interrupt context, so
|
||
* only minimal processing should be performed.
|
||
*
|
||
* @param CallBackRef is the callback reference passed in by the upper
|
||
* layer when setting the callback functions, and passed back to
|
||
* the upper layer when the callback is invoked. Its type is
|
||
* not important to the driver, so it is a void pointer.
|
||
* @param StatusEvent holds one or more status events that have occurred.
|
||
* See the XQspiPs_SetStatusHandler() for details on the status
|
||
* events that can be passed in the callback.
|
||
* @param ByteCount indicates how many bytes of data were successfully
|
||
* transferred. This may be less than the number of bytes
|
||
* requested if the status event indicates an error.
|
||
*/
|
||
typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
|
||
unsigned ByteCount);
|
||
|
||
/**
|
||
* This typedef contains configuration information for the device.
|
||
*/
|
||
typedef struct {
|
||
u16 DeviceId; /**< Unique ID of device */
|
||
u32 BaseAddress; /**< Base address of the device */
|
||
u32 InputClockHz; /**< Input clock frequency */
|
||
u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
|
||
} XQspiPs_Config;
|
||
|
||
/**
|
||
* The XQspiPs driver instance data. The user is required to allocate a
|
||
* variable of this type for every QSPI device in the system. A pointer
|
||
* to a variable of this type is then passed to the driver API functions.
|
||
*/
|
||
typedef struct {
|
||
XQspiPs_Config Config; /**< Configuration structure */
|
||
u32 IsReady; /**< Device is initialized and ready */
|
||
|
||
u8 *SendBufferPtr; /**< Buffer to send (state) */
|
||
u8 *RecvBufferPtr; /**< Buffer to receive (state) */
|
||
int RequestedBytes; /**< Number of bytes to transfer (state) */
|
||
int RemainingBytes; /**< Number of bytes left to transfer(state) */
|
||
u32 IsBusy; /**< A transfer is in progress (state) */
|
||
XQspiPs_StatusHandler StatusHandler;
|
||
void *StatusRef; /**< Callback reference for status handler */
|
||
u32 ShiftReadData; /**< Flag to indicate whether the data
|
||
* read from the Rx FIFO needs to be shifted
|
||
* in cases where the data is less than 4
|
||
* bytes
|
||
*/
|
||
} XQspiPs;
|
||
|
||
/***************** Macros (Inline Functions) Definitions *********************/
|
||
|
||
/****************************************************************************/
|
||
/*
|
||
*
|
||
* Check in OptionsTable if Manual Start Option is enabled or disabled.
|
||
*
|
||
* @param InstancePtr is a pointer to the XQspiPs instance.
|
||
*
|
||
* @return
|
||
* - TRUE if option is set
|
||
* - FALSE if option is not set
|
||
*
|
||
* @note C-Style signature:
|
||
* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
|
||
*
|
||
*****************************************************************************/
|
||
#define XQspiPs_IsManualStart(InstancePtr) \
|
||
((XQspiPs_GetOptions(InstancePtr) & \
|
||
XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
|
||
|
||
/****************************************************************************/
|
||
/*
|
||
*
|
||
* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
|
||
*
|
||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||
*
|
||
* @return
|
||
* - TRUE if option is set
|
||
* - FALSE if option is not set
|
||
*
|
||
* @note C-Style signature:
|
||
* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
|
||
*
|
||
*****************************************************************************/
|
||
#define XQspiPs_IsManualChipSelect(InstancePtr) \
|
||
((XQspiPs_GetOptions(InstancePtr) & \
|
||
XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
|
||
|
||
/****************************************************************************/
|
||
/**
|
||
*
|
||
* Set the contents of the slave idle count register.
|
||
*
|
||
* @param InstancePtr is a pointer to the XQspiPs instance.
|
||
* @param RegisterValue is the value to be written, valid values are
|
||
* 0-255.
|
||
*
|
||
* @return None
|
||
*
|
||
* @note
|
||
* C-Style signature:
|
||
* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr, u32 RegisterValue)
|
||
*
|
||
*****************************************************************************/
|
||
#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
|
||
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
|
||
XQSPIPS_SICR_OFFSET, (RegisterValue))
|
||
|
||
/****************************************************************************/
|
||
/**
|
||
*
|
||
* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
|
||
* constants defined in xqspips_hw.h to interpret the bit-mask returned.
|
||
*
|
||
* @param InstancePtr is a pointer to the XQspiPs instance.
|
||
*
|
||
* @return An 8-bit value representing Slave Idle Count.
|
||
*
|
||
* @note C-Style signature:
|
||
* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
|
||
*
|
||
*****************************************************************************/
|
||
#define XQspiPs_GetSlaveIdle(InstancePtr) \
|
||
XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
|
||
XQSPIPS_SICR_OFFSET)
|
||
|
||
/****************************************************************************/
|
||
/**
|
||
*
|
||
* Set the contents of the transmit FIFO watermark register.
|
||
*
|
||
* @param InstancePtr is a pointer to the XQspiPs instance.
|
||
* @param RegisterValue is the value to be written, valid values are 1-63.
|
||
*
|
||
* @return None.
|
||
*
|
||
* @note
|
||
* C-Style signature:
|
||
* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
|
||
*
|
||
*****************************************************************************/
|
||
#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \
|
||
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
|
||
XQSPIPS_TXWR_OFFSET, (RegisterValue))
|
||
|
||
/****************************************************************************/
|
||
/**
|
||
*
|
||
* Get the contents of the transmit FIFO watermark register.
|
||
* Valid values are in the range 1-63.
|
||
*
|
||
* @param InstancePtr is a pointer to the XQspiPs instance.
|
||
*
|
||
* @return A 6-bit value representing Tx Watermark level.
|
||
*
|
||
* @note C-Style signature:
|
||
* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
|
||
*
|
||
*****************************************************************************/
|
||
#define XQspiPs_GetTXWatermark(InstancePtr) \
|
||
XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
|
||
|
||
/****************************************************************************/
|
||
/**
|
||
*
|
||
* Set the contents of the receive FIFO watermark register.
|
||
*
|
||
* @param InstancePtr is a pointer to the XQspiPs instance.
|
||
* @param RegisterValue is the value to be written, valid values are 1-63.
|
||
*
|
||
* @return None.
|
||
*
|
||
* @note
|
||
* C-Style signature:
|
||
* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
|
||
*
|
||
*****************************************************************************/
|
||
#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \
|
||
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
|
||
XQSPIPS_RXWR_OFFSET, (RegisterValue))
|
||
|
||
/****************************************************************************/
|
||
/**
|
||
*
|
||
* Get the contents of the receive FIFO watermark register.
|
||
* Valid values are in the range 1-63.
|
||
*
|
||
* @param InstancePtr is a pointer to the XQspiPs instance.
|
||
*
|
||
* @return A 6-bit value representing Rx Watermark level.
|
||
*
|
||
* @note C-Style signature:
|
||
* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
|
||
*
|
||
*****************************************************************************/
|
||
#define XQspiPs_GetRXWatermark(InstancePtr) \
|
||
XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
|
||
|
||
/****************************************************************************/
|
||
/**
|
||
*
|
||
* Enable the device and uninhibit master transactions.
|
||
*
|
||
* @param InstancePtr is a pointer to the XQspiPs instance.
|
||
*
|
||
* @return None.
|
||
*
|
||
* @note C-Style signature:
|
||
* void XQspiPs_Enable(XQspiPs *InstancePtr)
|
||
*
|
||
*****************************************************************************/
|
||
#define XQspiPs_Enable(InstancePtr) \
|
||
XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
|
||
XQSPIPS_ER_ENABLE_MASK)
|
||
|
||
/****************************************************************************/
|
||
/**
|
||
*
|
||
* Disable the device.
|
||
*
|
||
* @param InstancePtr is a pointer to the XQspiPs instance.
|
||
*
|
||
* @return None.
|
||
*
|
||
* @note C-Style signature:
|
||
* void XQspiPs_Disable(XQspiPs *InstancePtr)
|
||
*
|
||
*****************************************************************************/
|
||
#define XQspiPs_Disable(InstancePtr) \
|
||
XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
|
||
|
||
/****************************************************************************/
|
||
/**
|
||
*
|
||
* Set the contents of the Linear QSPI Configuration register.
|
||
*
|
||
* @param InstancePtr is a pointer to the XQspiPs instance.
|
||
* @param RegisterValue is the value to be written to the Linear QSPI
|
||
* configuration register.
|
||
*
|
||
* @return None.
|
||
*
|
||
* @note
|
||
* C-Style signature:
|
||
* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
|
||
* u32 RegisterValue)
|
||
*
|
||
*****************************************************************************/
|
||
#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \
|
||
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
|
||
XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
|
||
|
||
/****************************************************************************/
|
||
/**
|
||
*
|
||
* Get the contents of the Linear QSPI Configuration register.
|
||
*
|
||
* @param InstancePtr is a pointer to the XQspiPs instance.
|
||
*
|
||
* @return A 32-bit value representing the contents of the LQSPI Config
|
||
* register.
|
||
*
|
||
* @note C-Style signature:
|
||
* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
|
||
*
|
||
*****************************************************************************/
|
||
#define XQspiPs_GetLqspiConfigReg(InstancePtr) \
|
||
XQspiPs_In32((InstancePtr->Config.BaseAddress) + \
|
||
XQSPIPS_LQSPI_CR_OFFSET)
|
||
|
||
/************************** Function Prototypes ******************************/
|
||
|
||
/*
|
||
* Initialization function, implemented in xqspips_sinit.c
|
||
*/
|
||
XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
|
||
|
||
/*
|
||
* Functions implemented in xqspips.c
|
||
*/
|
||
int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config * Config,
|
||
u32 EffectiveAddr);
|
||
void XQspiPs_Reset(XQspiPs *InstancePtr);
|
||
void XQspiPs_Abort(XQspiPs *InstancePtr);
|
||
|
||
int XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
|
||
unsigned ByteCount);
|
||
int XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
|
||
u8 *RecvBufPtr, unsigned ByteCount);
|
||
int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
|
||
u32 Address, unsigned ByteCount);
|
||
|
||
int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
|
||
|
||
void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
|
||
XQspiPs_StatusHandler FuncPtr);
|
||
void XQspiPs_InterruptHandler(void *InstancePtr);
|
||
|
||
/*
|
||
* Functions for selftest, in xqspips_selftest.c
|
||
*/
|
||
int XQspiPs_SelfTest(XQspiPs *InstancePtr);
|
||
|
||
/*
|
||
* Functions for options, in xqspips_options.c
|
||
*/
|
||
int XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
|
||
u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
|
||
|
||
int XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
|
||
u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
|
||
|
||
int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
|
||
u8 DelayAfter, u8 DelayInit);
|
||
void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
|
||
u8 *DelayAfter, u8 *DelayInit);
|
||
#ifdef __cplusplus
|
||
}
|
||
#endif
|
||
|
||
#endif /* end of protection macro */
|
||
|