903d859429
Copied v1.0 directory to v2.0. Deprecated version 1.0. Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
339 lines
10 KiB
C
339 lines
10 KiB
C
/*******************************************************************************
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*
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* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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*******************************************************************************/
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/******************************************************************************/
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/**
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*
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* @file xdp_selftest.c
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*
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* This file contains a diagnostic self-test function for the XDp driver. It
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* will check many of the DisplayPort core's register values against the default
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* reset values as a sanity-check that the core is ready to be used.
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*
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* @note None.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.0 als 01/20/15 Initial release. TX code merged from the dptx driver.
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* </pre>
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*
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*******************************************************************************/
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/******************************* Include Files ********************************/
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#include "xdp.h"
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/**************************** Function Prototypes *****************************/
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static u32 XDp_TxSelfTest(XDp *InstancePtr);
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static u32 XDp_RxSelfTest(XDp *InstancePtr);
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/**************************** Variable Definitions ****************************/
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/**
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* This table contains the default values for the DisplayPort TX core's general
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* usage registers.
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*/
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u32 TxResetValues[53][2] =
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{
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{XDP_TX_LINK_BW_SET, 0},
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{XDP_TX_LANE_COUNT_SET, 0},
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{XDP_TX_ENHANCED_FRAME_EN, 0},
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{XDP_TX_TRAINING_PATTERN_SET, 0},
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{XDP_TX_LINK_QUAL_PATTERN_SET, 0},
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{XDP_TX_SCRAMBLING_DISABLE, 0},
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{XDP_TX_DOWNSPREAD_CTRL, 0},
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{XDP_TX_SOFT_RESET, 0},
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{XDP_TX_ENABLE, 0},
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{XDP_TX_ENABLE_MAIN_STREAM, 0},
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{XDP_TX_ENABLE_SEC_STREAM, 0},
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{XDP_TX_FORCE_SCRAMBLER_RESET, 0},
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{XDP_TX_MST_CONFIG, 0},
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{XDP_TX_AUX_CMD, 0},
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{XDP_TX_AUX_WRITE_FIFO, 0},
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{XDP_TX_AUX_ADDRESS, 0},
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{XDP_TX_AUX_CLK_DIVIDER, 0},
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{XDP_TX_USER_FIFO_OVERFLOW, 0},
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{XDP_TX_AUX_REPLY_DATA, 0},
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{XDP_TX_AUX_REPLY_CODE, 0},
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{XDP_TX_AUX_REPLY_COUNT, 0},
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{XDP_TX_INTERRUPT_MASK, 0x3F},
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{XDP_TX_REPLY_DATA_COUNT, 0},
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{XDP_TX_REPLY_STATUS, 0x10},
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{XDP_TX_STREAM1, 0},
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{XDP_TX_STREAM2, 0},
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{XDP_TX_STREAM3, 0},
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{XDP_TX_STREAM4, 0},
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{XDP_TX_PHY_CONFIG, 0x03},
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{XDP_TX_PHY_VOLTAGE_DIFF_LANE_0, 0},
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{XDP_TX_PHY_VOLTAGE_DIFF_LANE_1, 0},
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{XDP_TX_PHY_VOLTAGE_DIFF_LANE_2, 0},
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{XDP_TX_PHY_VOLTAGE_DIFF_LANE_3, 0},
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{XDP_TX_PHY_TRANSMIT_PRBS7, 0},
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{XDP_TX_PHY_CLOCK_SELECT, 0},
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{XDP_TX_PHY_POWER_DOWN, 0},
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{XDP_TX_PHY_PRECURSOR_LANE_0, 0},
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{XDP_TX_PHY_PRECURSOR_LANE_1, 0},
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{XDP_TX_PHY_PRECURSOR_LANE_2, 0},
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{XDP_TX_PHY_PRECURSOR_LANE_3, 0},
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{XDP_TX_PHY_POSTCURSOR_LANE_0, 0},
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{XDP_TX_PHY_POSTCURSOR_LANE_1, 0},
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{XDP_TX_PHY_POSTCURSOR_LANE_2, 0},
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{XDP_TX_PHY_POSTCURSOR_LANE_3, 0},
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{XDP_TX_GT_DRP_COMMAND, 0},
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{XDP_TX_GT_DRP_READ_DATA, 0},
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{XDP_TX_GT_DRP_CHANNEL_STATUS, 0},
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{XDP_TX_AUDIO_CONTROL, 0},
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{XDP_TX_AUDIO_CHANNELS, 0},
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{XDP_TX_AUDIO_INFO_DATA(1), 0},
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{XDP_TX_AUDIO_MAUD, 0},
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{XDP_TX_AUDIO_NAUD, 0},
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{XDP_TX_AUDIO_EXT_DATA(1), 0}
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};
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/**
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* This table contains the default values for the DisplayPort TX core's main
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* stream attribute (MSA) registers.
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*/
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u32 TxResetValuesMsa[20][2] =
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{
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{XDP_TX_MAIN_STREAM_HTOTAL, 0},
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{XDP_TX_MAIN_STREAM_VTOTAL, 0},
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{XDP_TX_MAIN_STREAM_POLARITY, 0},
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{XDP_TX_MAIN_STREAM_HSWIDTH, 0},
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{XDP_TX_MAIN_STREAM_VSWIDTH, 0},
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{XDP_TX_MAIN_STREAM_HRES, 0},
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{XDP_TX_MAIN_STREAM_VRES, 0},
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{XDP_TX_MAIN_STREAM_HSTART, 0},
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{XDP_TX_MAIN_STREAM_VSTART, 0},
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{XDP_TX_MAIN_STREAM_MISC0, 0},
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{XDP_TX_MAIN_STREAM_MISC1, 0},
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{XDP_TX_M_VID, 0},
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{XDP_TX_TU_SIZE, 0},
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{XDP_TX_N_VID, 0},
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{XDP_TX_USER_PIXEL_WIDTH, 0},
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{XDP_TX_USER_DATA_COUNT_PER_LANE, 0},
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{XDP_TX_MAIN_STREAM_INTERLACED, 0},
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{XDP_TX_MIN_BYTES_PER_TU, 0},
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{XDP_TX_FRAC_BYTES_PER_TU, 0},
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{XDP_TX_INIT_WAIT, 32}
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};
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/**
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* This table contains the default values for the DisplayPort RX core's general
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* usage registers.
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*/
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u32 RxResetValues[46][2] =
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{
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{XDP_RX_LINK_ENABLE, 0},
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{XDP_RX_AUX_CLK_DIVIDER, 0},
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{XDP_RX_DTG_ENABLE, 0},
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{XDP_RX_USER_PIXEL_WIDTH, 0},
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{XDP_RX_INTERRUPT_MASK, 0x7FFF},
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{XDP_RX_MISC_CTRL, 0},
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{XDP_RX_SOFT_RESET, 0},
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{XDP_RX_AUX_REQ_IN_PROGRESS, 0},
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{XDP_RX_REQ_ERROR_COUNT, 0},
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{XDP_RX_REQ_COUNT, 0},
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{XDP_RX_HPD_INTERRUPT, 0},
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{XDP_RX_REQ_CLK_WIDTH, 0},
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{XDP_RX_REQ_CMD, 0},
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{XDP_RX_REQ_ADDRESS, 0},
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{XDP_RX_REQ_LENGTH, 0},
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{XDP_RX_INTERRUPT_CAUSE, 0},
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{XDP_RX_INTERRUPT_MASK_1, 0},
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{XDP_RX_INTERRUPT_CAUSE_1, 0},
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{XDP_RX_HSYNC_WIDTH, 0xF0F},
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{XDP_RX_FAST_I2C_DIVIDER, 0},
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{XDP_RX_LOCAL_EDID_VIDEO, 0},
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{XDP_RX_LOCAL_EDID_AUDIO, 0},
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{XDP_RX_REMOTE_CMD, 0},
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{XDP_RX_DEVICE_SERVICE_IRQ, 0},
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{XDP_RX_VIDEO_UNSUPPORTED, 0},
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{XDP_RX_AUDIO_UNSUPPORTED, 0},
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{XDP_RX_OVER_LINK_BW_SET, 0},
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{XDP_RX_OVER_LANE_COUNT_SET, 0},
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{XDP_RX_OVER_TP_SET, 0},
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{XDP_RX_OVER_TRAINING_LANE0_SET, 0},
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{XDP_RX_OVER_TRAINING_LANE1_SET, 0},
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{XDP_RX_OVER_TRAINING_LANE2_SET, 0},
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{XDP_RX_OVER_TRAINING_LANE3_SET, 0},
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{XDP_RX_OVER_CTRL_DPCD, 0},
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{XDP_RX_OVER_DOWNSPREAD_CTRL, 0},
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{XDP_RX_OVER_LINK_QUAL_LANE0_SET, 0},
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{XDP_RX_OVER_LINK_QUAL_LANE1_SET, 0},
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{XDP_RX_OVER_LINK_QUAL_LANE2_SET, 0},
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{XDP_RX_OVER_LINK_QUAL_LANE3_SET, 0},
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{XDP_RX_MST_CAP, 0},
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{XDP_RX_SINK_COUNT, 0},
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{XDP_RX_GUID0, 0},
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{XDP_RX_GUID1, 0},
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{XDP_RX_GUID2, 0},
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{XDP_RX_GUID3, 0},
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{XDP_RX_OVER_GUID, 0}
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};
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/**************************** Function Definitions ****************************/
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/******************************************************************************/
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/**
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* This function runs a self-test on the XDp driver/device depending on whether
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* the core is operating in TX or RX mode. The sanity test checks whether or not
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* all tested registers hold their default reset values.
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*
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* @param InstancePtr is a pointer to the XDp instance.
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*
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* @return
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* - XST_SUCCESS if the self-test passed - all tested registers
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* hold their default reset values.
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* - XST_FAILURE otherwise.
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*
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* @note None.
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*
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*******************************************************************************/
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u32 XDp_SelfTest(XDp *InstancePtr)
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{
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u32 Status;
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/* Verify arguments. */
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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if (XDp_GetCoreType(InstancePtr) == XDP_TX) {
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Status = XDp_TxSelfTest(InstancePtr);
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}
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else {
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Status = XDp_RxSelfTest(InstancePtr);
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}
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return Status;
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}
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/******************************************************************************/
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/**
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* This function runs a self-test on the XDp driver/device. The sanity test
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* checks whether or not all tested registers hold their default reset values.
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*
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* @param InstancePtr is a pointer to the XDp instance.
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*
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* @return
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* - XST_SUCCESS if the self-test passed - all tested registers
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* hold their default reset values.
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* - XST_FAILURE otherwise.
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*
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* @note None.
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*
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*******************************************************************************/
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static u32 XDp_TxSelfTest(XDp *InstancePtr)
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{
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u8 Index;
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u8 StreamIndex;
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u32 StreamOffset;
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u32 Val;
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/* Compare general usage registers with their default values. */
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for (Index = 0; Index < 53; Index++) {
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Val = XDp_ReadReg(InstancePtr->Config.BaseAddr,
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TxResetValues[Index][0]);
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/* Fail if register does not hold default value. */
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if (Val != TxResetValues[Index][1]) {
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return XST_FAILURE;
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}
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}
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/* Compare main stream attribute (MSA) registers for all 4 streams with
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* their default values. */
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for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) {
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/* Determine the MSA register offset for each stream. */
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if (StreamIndex == 0) {
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StreamOffset = 0;
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}
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else if (StreamIndex == 1) {
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StreamOffset = XDP_TX_STREAM2_MSA_START_OFFSET;
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}
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else if (StreamIndex == 2) {
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StreamOffset = XDP_TX_STREAM3_MSA_START_OFFSET;
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}
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else if (StreamIndex == 3) {
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StreamOffset = XDP_TX_STREAM4_MSA_START_OFFSET;
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}
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for (Index = 0; Index < 20; Index++) {
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Val = XDp_ReadReg(InstancePtr->Config.BaseAddr,
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StreamOffset + TxResetValuesMsa[Index][0]);
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/* Fail if register does not hold default value. */
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if (Val != TxResetValuesMsa[Index][1]) {
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return XST_FAILURE;
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}
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}
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}
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/* All tested registers hold their default reset values. */
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return XST_SUCCESS;
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}
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/******************************************************************************/
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/**
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* This function runs a self-test on the XDp driver/device running in RX mode.
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* The sanity test checks whether or not all tested registers hold their default
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* reset values.
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*
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* @param InstancePtr is a pointer to the XDp instance.
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*
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* @return
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* - XST_SUCCESS if the self-test passed - all tested registers
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* hold their default reset values.
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* - XST_FAILURE otherwise.
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*
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* @note None.
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*
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*******************************************************************************/
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static u32 XDp_RxSelfTest(XDp *InstancePtr)
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{
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u8 Index;
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u32 Val;
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/* Compare general usage registers with their default values. */
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for (Index = 0; Index < 46; Index++) {
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Val = XDp_ReadReg(InstancePtr->Config.BaseAddr,
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RxResetValues[Index][0]);
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/* Fail if register does not hold default value. */
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if (Val != RxResetValues[Index][1]) {
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return XST_FAILURE;
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}
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}
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/* All tested registers hold their default reset values. */
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return XST_SUCCESS;
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}
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