2c8f92039d
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
504 lines
15 KiB
C
Executable file
504 lines
15 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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* @file xiic_multi_master_example.c
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*
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* This file consists of a Interrupt mode design example which uses the Xilinx
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* IIC device and XIic driver to exercise the EEPROM on the Xilinx boards in a
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* Multi master mode. This example has been tested with an off-board external
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* IIC Master connected on the IIC bus.
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*
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* This example writes/reads from the lower 256 bytes of the IIC EEPROMS. Please
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* refer to the datasheets of the IIC EEPROM's for details about the internal
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* addressing and page size of these devices.
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*
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* The XIic_MasterSend() API is used to transmit the data and XIic_MasterRecv()
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* API is used to receive the data.
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*
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* The example is tested on ML300/ML310/ML403/ML501 Xilinx boards.
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*
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* The ML310/ML410/ML510 boards have a on-board 64 Kb serial IIC EEPROM
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* (Microchip 24LC64A). The WP pin of the IIC EEPROM is hardwired to ground on
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* this board.
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*
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* The ML300 board has an on-board 32 Kb serial IIC EEPROM(Microchip 24LC32A).
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* The WP pin of the IIC EEPROM has to be connected to ground for this example.
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* The WP is connected to pin Y3 of the FPGA.
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*
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* The ML403 board has an on-board 4 Kb serial IIC EEPROM(Microchip 24LC04A).
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* The WP pin of the IIC EEPROM is hardwired to ground on this board.
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*
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* The ML501/ML505/ML507/ML605/SP601/SP605 boards have an on-board 8 Kb serial
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* IIC EEPROM(STM M24C08). The WP pin of the IIC EEPROM is hardwired to
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* ground on these boards.
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*
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* The AddressType for ML300/ML310/ML410/ML510 boards should be u16 as the
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* address pointer in the on board EEPROM is 2 bytes.
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*
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* The AddressType for ML403/ML501/ML505/ML507/ML605/SP601/SP605 boards should
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* be u8 as the address pointer for the on board EEPROM is 1 byte.
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*
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* The 7 bit IIC Slave address of the IIC EEPROM on the ML300/ML310/ML403/ML410/
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* ML501/ML505/ML507/ML510 boards is 0x50.
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* The 7 bit IIC Slave address of the IIC EEPROM on the ML605/SP601/SP605 boards
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* is 0x54.
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* Refer to the User Guide's of the respective boards for further information
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* about the IIC slave address of IIC EEPROM's.
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*
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* The define EEPROM_ADDRESS in this file needs to be changed depending on
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* the board on which this example is to be run.
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* This code assumes that no Operating System is being used.
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*
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* @note
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*
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* None.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.00a mta 03/01/06 Created.
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* 2.00a sdm 09/22/09 Converted all register accesses to 32 bit access.
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* Updated to use the HAL APIs, replaced call to
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* XIic_Initialize API with XIic_LookupConfig and
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* XIic_CfgInitialize.
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* 2.01a ktn 03/17/10 Updated the information about the EEPROM's used on
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* ML605/SP601/SP605 boards.
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*
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* </pre>
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "xparameters.h"
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#include "xiic.h"
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#include "xintc.h"
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#include "xil_exception.h"
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/************************** Constant Definitions *****************************/
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/*
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* The following constants map to the XPAR parameters created in the
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* xparameters.h file. They are defined here such that a user can easily
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* change all the needed parameters in one place.
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*/
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#define IIC_DEVICE_ID XPAR_IIC_0_DEVICE_ID
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#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID
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#define IIC_INTR_ID XPAR_INTC_0_IIC_0_VEC_ID
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/*
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* The following constant defines the address of the IIC Slave device on the
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* IIC bus. Note that since the address is only 7 bits, this constant is the
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* address divided by 2.
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* The 7 bit IIC Slave address of the IIC EEPROM on the ML300/ML310/ML403/ML501/
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* ML410/ML505/ML507/ML510 boards is 0x50. The 7 bit IIC Slave address of the
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* IIC EEPROM on the ML605/SP601/SP605 boards is 0x54.
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* Please refer the User Guide's of the respective boards for further
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* information about the IIC slave address of IIC EEPROM's.
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*/
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#define EEPROM_ADDRESS 0x50 /* 0xA0 as an 8 bit number. */
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/*
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* The page size determines how much data should be written at a time.
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* The ML300 board supports a page size of 32 and 16.
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* The write function should be called with this as a maximum byte count.
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*/
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#define PAGE_SIZE 16
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/*
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* The Starting address in the IIC EEPROM on which this test is performed.
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*/
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#define EEPROM_TEST_START_ADDRESS 128
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/**************************** Type Definitions *******************************/
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/*
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* The AddressType for ML300/ML310/ML410/ML510 boards should be u16 as the
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* address pointer in the on board EEPROM is 2 bytes.
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* The AddressType for ML403/ML501/ML505/ML507/ML605/SP601/SP605 boards should
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* be u8 as the address pointer in the on board EEPROM is 1 bytes.
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*/
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typedef u8 AddressType;
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Function Prototypes ******************************/
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int IicMultiMasterExample();
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static int SetupInterruptSystem(XIic *IicInstPtr);
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static void SendHandler(XIic *InstancePtr);
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static void StatusHandler(XIic *InstancePtr, int Event);
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/************************** Variable Definitions *****************************/
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XIic IicInstance; /* The instance of the IIC device. */
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XIntc InterruptController; /* The instance of the Interrupt Controller. */
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/*
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* Write buffer for writing a page.
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*/
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u8 WriteBuffer[sizeof(AddressType) + PAGE_SIZE];
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volatile u8 TransmitComplete;
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volatile u8 ReceiveComplete;
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volatile u8 BusNotBusy;
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/************************** Function Definitions *****************************/
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/*****************************************************************************/
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/**
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* Main function to call the Multi Master example.
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*
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* @param None.
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*
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* @return XST_SUCCESS if successful else XST_FAILURE.
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*
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* @note None.
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*
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******************************************************************************/
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int main(void)
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{
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int Status;
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/*
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* Run the Multi master example.
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*/
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Status = IicMultiMasterExample();
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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return XST_SUCCESS;
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}
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/*****************************************************************************/
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/**
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* This function writes the data to the IIC EEPROM.
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*
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* @param None.
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*
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* @return XST_SUCCESS if successful else XST_FAILURE.
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*
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* @note None.
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*
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****************************************************************************/
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int IicMultiMasterExample()
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{
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u8 Index;
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int Status;
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XIic_Config *ConfigPtr; /* Pointer to configuration data */
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AddressType Address = EEPROM_TEST_START_ADDRESS;
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/*
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* Initialize the data to write and the read buffer.
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*/
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if (sizeof(Address) == 1) {
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WriteBuffer[0] = (u8) (Address);
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}
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else {
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WriteBuffer[0] = (u8) (Address >> 8);
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WriteBuffer[1] = (u8) (Address);
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}
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for (Index = 0; Index < PAGE_SIZE; Index++) {
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WriteBuffer[sizeof(Address) + Index] = 0xFF;
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}
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/*
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* Include the multi master functionality.
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*/
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XIic_MultiMasterInclude();
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/*
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* Initialize the IIC driver so that it is ready to use.
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*/
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ConfigPtr = XIic_LookupConfig(XPAR_IIC_0_DEVICE_ID);
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if (ConfigPtr == NULL) {
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return XST_FAILURE;
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}
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Status = XIic_CfgInitialize(&IicInstance, ConfigPtr,
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ConfigPtr->BaseAddress);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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/*
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* Setup the Interrupt System.
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*/
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Status = SetupInterruptSystem(&IicInstance);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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/*
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* Set the Transmit and status handlers.
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*/
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XIic_SetSendHandler(&IicInstance, &IicInstance,
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(XIic_Handler) SendHandler);
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XIic_SetStatusHandler(&IicInstance, &IicInstance,
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(XIic_StatusHandler) StatusHandler);
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/*
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* Set the address of the slave.
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*/
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Status = XIic_SetAddress(&IicInstance, XII_ADDR_TO_SEND_TYPE,
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EEPROM_ADDRESS);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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IicInstance.Stats.TxErrors = 0;
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/*
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* Set the defaults.
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*/
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TransmitComplete = 1;
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/*
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* Start the IIC device.
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*/
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Status = XIic_Start(&IicInstance);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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/*
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* Write to the EEPROM.
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*/
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XIic_MasterSend(&IicInstance, WriteBuffer, PAGE_SIZE);
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while (1) {
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/*
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* If arbitration is lost and some time later Bus if bus
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* becomes free transmit the data.
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*/
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if (BusNotBusy) {
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/*
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* Start the IIC device.
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*/
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Status = XIic_Start(&IicInstance);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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/*
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* Send the data.
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*/
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XIic_MasterSend(&IicInstance, WriteBuffer, PAGE_SIZE);
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/*
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* Clear the Flag.
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*/
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BusNotBusy = 0;
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}
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/*
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* This condition is required to be checked in the case where we
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* are writing two consecutive buffers of data to the EEPROM.
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* The EEPROM takes about 2 milliseconds time to update the data
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* internally after a STOP has been sent on the bus.
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* A NACK will be generated in the case of a second write before
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* the EEPROM updates the data internally resulting in a
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* Transmission Error.
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*/
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if (IicInstance.Stats.TxErrors != 0) {
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/*
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* If the Slave didn't acknowledge then we should keep
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* making attempts to transmit the data.
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*/
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IicInstance.Stats.TxErrors = 0;
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/*
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* Start the IIC device.
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*/
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Status = XIic_Start(&IicInstance);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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/*
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* Send the data.
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*/
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XIic_MasterSend(&IicInstance, WriteBuffer, PAGE_SIZE);
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}
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if ((!TransmitComplete) &&
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(XIic_IsIicBusy(&IicInstance) == FALSE))
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break;
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}
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/*
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* Stop the IIC device.
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*/
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Status = XIic_Stop(&IicInstance);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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return XST_SUCCESS;
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}
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/****************************************************************************/
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/**
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* This function setups the interrupt system so interrupts can occur for the
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* IIC. The function is application-specific since the actual system may or
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* may not have an interrupt controller. The IIC device could be directly
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* connected to a processor without an interrupt controller. The user should
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* modify this function to fit the application.
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*
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* @param IicInstPtr contains a pointer to the instance of the IIC which
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* is going to be connected to the interrupt controller.
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*
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* @return XST_SUCCESS if successful else XST_FAILURE.
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*
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* @note None.
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*
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****************************************************************************/
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static int SetupInterruptSystem(XIic *IicInstPtr)
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{
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int Status;
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if (InterruptController.IsStarted == XIL_COMPONENT_IS_STARTED) {
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return XST_SUCCESS;
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}
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/*
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* Initialize the interrupt controller driver so that it's ready to use.
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*/
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Status = XIntc_Initialize(&InterruptController, INTC_DEVICE_ID);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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/*
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* Connect the device driver handler that will be called when an
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* interrupt for the device occurs, the handler defined above performs
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* the specific interrupt processing for the device.
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*/
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Status = XIntc_Connect(&InterruptController, IIC_INTR_ID,
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(XInterruptHandler) XIic_InterruptHandler,
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IicInstPtr);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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/*
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* Start the interrupt controller so interrupts are enabled for all
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* devices that cause interrupts.
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*/
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Status = XIntc_Start(&InterruptController, XIN_REAL_MODE);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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/*
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* Enable the interrupts for the IIC device.
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*/
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XIntc_Enable(&InterruptController, IIC_INTR_ID);
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/*
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* Initialize the exception table.
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*/
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Xil_ExceptionInit();
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/*
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* Register the interrupt controller handler with the exception table.
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*/
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Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
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(Xil_ExceptionHandler) XIntc_InterruptHandler,
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&InterruptController);
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/*
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* Enable non-critical exceptions.
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*/
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Xil_ExceptionEnable();
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return XST_SUCCESS;
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}
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/*****************************************************************************/
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/**
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* The Send handler is called asynchronously from an interrupt context and
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* indicates that data in the specified buffer has been sent.
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*
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* @param InstancePtr is a pointer to the IIC driver instance for which
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* the handler is being called for.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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static void SendHandler(XIic *InstancePtr)
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{
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TransmitComplete = 0;
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}
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/*****************************************************************************/
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/**
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* The Status handler is called asynchronously from an interrupt context and
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* indicates the events that have occured.
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*
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* @param InstancePtr is a pointer to the IIC driver instance for which
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* the handler is being called for.
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* @param Event indicates the condition that has occurred.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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static void StatusHandler(XIic *InstancePtr, int Event)
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{
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if (Event == XII_ARB_LOST_EVENT) {
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XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET,
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XIIC_CR_ENABLE_DEVICE_MASK);
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XIic_WriteIisr(InstancePtr->BaseAddress, XIIC_INTR_BNB_MASK);
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XIic_WriteIier(InstancePtr->BaseAddress, XIIC_INTR_BNB_MASK);
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InstancePtr->BNBOnly = TRUE;
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}
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else if (Event == XII_BUS_NOT_BUSY_EVENT) {
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XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET,
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0x0);
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BusNotBusy = 1;
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}
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}
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