f82f6df813
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com> Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
366 lines
8.9 KiB
C
366 lines
8.9 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xil_testcache.c
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*
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* Contains utility functions to test cache.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a hbm 07/28/09 Initial release
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* 4.1 asa 05/09/14 Ensured that the address uses for cache test is aligned
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* cache line.
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* </pre>
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*
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* @note
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*
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* This file contain functions that all operate on HAL.
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*
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******************************************************************************/
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#ifdef __ARM__
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#include "xil_cache.h"
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#include "xil_testcache.h"
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#include "xil_types.h"
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#include "xpseudo_asm.h"
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#ifdef __aarch64__
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#include "xreg_cortexa53.h"
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#else
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#include "xreg_cortexr5.h"
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#endif
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#include "xil_types.h"
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extern void xil_printf(const char8 *ctrl1, ...);
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#define DATA_LENGTH 128
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#ifdef __aarch64__
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static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
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#else
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static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
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#endif
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/**
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* Perform DCache range related API test such as Xil_DCacheFlushRange and
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* Xil_DCacheInvalidateRange. This test function writes a constant value
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* to the Data array, flushes the range, writes a new value, then invalidates
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* the corresponding range.
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*
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* @return
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*
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* - 0 is returned for a pass
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* - -1 is returned for a failure
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*/
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s32 Xil_TestDCacheRange(void)
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{
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s32 Index;
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s32 Status = 0;
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u32 CtrlReg;
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INTPTR Value;
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xil_printf("-- Cache Range Test --\n\r");
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = 0xA0A00505;
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xil_printf(" initialize Data done:\r\n");
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Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
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xil_printf(" flush range done\r\n");
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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Status = 0;
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for (Index = 0; Index < DATA_LENGTH; Index++) {
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Value = Data[Index];
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if (Value != 0xA0A00505) {
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Status = -1;
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xil_printf("Data[%d] = %x\r\n", Index, Value);
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break;
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}
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}
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if (!Status) {
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xil_printf(" Flush worked\r\n");
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}
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else {
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xil_printf("Error: flush dcache range not working\r\n");
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}
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = 0xA0A0C505;
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Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = Index + 3;
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Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
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xil_printf(" invalidate dcache range done\r\n");
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = 0xA0A0A05;
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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Status = 0;
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for (Index = 0; Index < DATA_LENGTH; Index++) {
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Value = Data[Index];
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if (Value != 0xA0A0A05) {
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Status = -1;
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xil_printf("Data[%d] = %x\r\n", Index, Value);
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break;
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}
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}
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if (!Status) {
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xil_printf(" Invalidate worked\r\n");
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}
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else {
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xil_printf("Error: Invalidate dcache range not working\r\n");
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}
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xil_printf("-- Cache Range Test Complete --\r\n");
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return Status;
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}
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/**
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* Perform DCache all related API test such as Xil_DCacheFlush and
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* Xil_DCacheInvalidate. This test function writes a constant value
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* to the Data array, flushes the DCache, writes a new value, then invalidates
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* the DCache.
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*
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* @return
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* - 0 is returned for a pass
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* - -1 is returned for a failure
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*/
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s32 Xil_TestDCacheAll(void)
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{
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s32 Index;
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s32 Status;
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INTPTR Value;
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u32 CtrlReg;
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xil_printf("-- Cache All Test --\n\r");
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = 0x50500A0A;
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xil_printf(" initialize Data done:\r\n");
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Xil_DCacheFlush();
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xil_printf(" flush all done\r\n");
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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Status = 0;
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for (Index = 0; Index < DATA_LENGTH; Index++) {
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Value = Data[Index];
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if (Value != 0x50500A0A) {
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Status = -1;
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xil_printf("Data[%d] = %x\r\n", Index, Value);
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break;
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}
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}
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if (!Status) {
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xil_printf(" Flush all worked\r\n");
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}
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else {
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xil_printf("Error: Flush dcache all not working\r\n");
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}
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = 0x505FFA0A;
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Xil_DCacheFlush();
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = Index + 3;
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Xil_DCacheInvalidate();
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xil_printf(" invalidate all done\r\n");
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = 0x50CFA0A;
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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Status = 0;
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for (Index = 0; Index < DATA_LENGTH; Index++) {
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Value = Data[Index];
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if (Value != 0x50CFA0A) {
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Status = -1;
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xil_printf("Data[%d] = %x\r\n", Index, Value);
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break;
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}
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}
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if (!Status) {
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xil_printf(" Invalidate all worked\r\n");
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}
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else {
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xil_printf("Error: Invalidate dcache all not working\r\n");
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}
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xil_printf("-- DCache all Test Complete --\n\r");
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return Status;
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}
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/**
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* Perform Xil_ICacheInvalidateRange() on a few function pointers.
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*
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* @return
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*
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* - 0 is returned for a pass
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* The function will hang if it fails.
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*/
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s32 Xil_TestICacheRange(void)
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{
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Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
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Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
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Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
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xil_printf("-- Invalidate icache range done --\r\n");
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return 0;
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}
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/**
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* Perform Xil_ICacheInvalidate().
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*
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* @return
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*
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* - 0 is returned for a pass
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* The function will hang if it fails.
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*/
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s32 Xil_TestICacheAll(void)
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{
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Xil_ICacheInvalidate();
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xil_printf("-- Invalidate icache all done --\r\n");
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return 0;
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}
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#endif
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