5e98df225c
Added new lines in example prints. Modified CRC calculation API name and provided backward compatability. Signed-off-by: VNSL Durga <vnsldurg@xilinx.com> Reviewed-by: Harini Katakam <harinik@xilinx.com>
722 lines
28 KiB
C
722 lines
28 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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* @file xilskey_input.h
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*
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*
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* @note
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*
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* User configurable parameters for PS eFUSE
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* ---------------------------------------------------------------------------
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* #define XSK_EFUSEPS_ENABLE_WRITE_PROTECT FALSE
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*
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* TRUE to burn the write protect bits in eFUSE array. Write protect
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* has two bits, when any of the bit is blown, it is considered as write
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* protected. So, while burning the Write protect bits, even if one bit is
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* blown, write API returns success. Note that, POR reset is required after
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* burning, for write protection of the eFUSE bits to come into effect.
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* It is recommended to do the POR reset after write protection.
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* Also note that, once write protect bits are burned, no more eFUSE writes
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* are possible. So, please be sure when burning the write protect bits.
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* If the Write protect macro is TRUE with other macros, write protect will
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* be burned in the last, after burning all the defined values, so that for
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* any error while burning other macros will not effect the total eFUSE array.
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* FALSE will not modify the write protect bits.
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*
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* #define XSK_EFUSEPS_ENABLE_RSA_AUTH FALSE
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*
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* TRUE to burn the RSA enable bit in PS eFUSE array. After enabling the bit,
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* every successive boot must be RSA enabled apart from JTAG. Before burning
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* this bit, make sure that eFUSE array has the valid PPK hash.If the PPK hash
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* burning is enabled, only after writing the hash successfully, RSA enable
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* bit will be blown. Note that, for RSA enable bit to take effect, POR reset
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* is required.
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* FALSE will not modify the RSA enable bit.
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*
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* #define XSK_EFUSEPS_ENABLE_ROM_128K_CRC FALSE
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* TRUE will burn the ROM 128k crc bit. Every successive boot after this,
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* BootROM will calculate 128k crc. FALSE will not modify the ROM CRC128K bit.
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*
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* #define XSK_EFUSEPS_DISABLE_DFT_JTAG FALSE
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* TRUE will disable DFT JTAG permanently.
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* FALSE will not modify the eFuse PS DFT JTAG disable bit
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*
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* #define XSK_EFUSEPS_DISABLE_DFT_MODE FALSE
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* TRUE will disable DFT mode permanently.
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* FALSE will not modify the eFuse PS DFT mode disable bit
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*
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* #define XSK_EFUSEPS_ENABLE_RSA_KEY_HASH FALSE
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* TRUE will burn the eFUSE hash, that is given in XSK_EFUSEPS_RSA_KEY_HASH_VALUE
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* when write API is used. TRUE will read the eFUSE hash when read API is used
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* and will be read into structure. FALSE will ignore the value given.
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*
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* #define XSK_EFUSEPS_RSA_KEY_HASH_VALUE
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* "c8bb4d9e1fcdbd27b99d48a3df5720b98f35bafabb1e10333a78322fb82ce63d"
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*
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* The value mentioned in this will be converted to hex buffer and written
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* into the PS eFUSE array when write API used. This value should be the
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* PPK(Primary Public Key) hash given in string format. It should be 64
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* characters long, valid characters are 0-9,a-f,A-F. Any other character
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* is considered as invalid string and will not burn RSA hash.
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*
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* Note: When XilSKey_EfusePs_Write() API is used, above mentioned RSA hash
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* is written and XSK_EFUSEPS_ENABLE_RSA_KEY_HASH should have TRUE value.
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*
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* User configurable parameters for PL eFUSE for Zynq
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* -----------------------------------------------------------------------
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* #define XSK_EFUSEPL_FORCE_PCYCLE_RECONFIG FALSE
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* TRUE then part has to be power cycled to be able to be reconfigured.
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* FALSE will not set the eFUSE control bit.
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*
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* #define XSK_EFUSEPL_DISABLE_KEY_WRITE FALSE
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* TRUE will disable eFUSE write to FUSE_AES and FUSE_USER blocks
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* XFLASE will enable eFUSE write to FUSE_AES and FUSE_USER blocks
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*
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* #define XSK_EFUSEPL_DISABLE_AES_KEY_READ FALSE
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* TRUE will disable the write to FUSE_AES & FUSE_USER key & disables
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* read of FUSE_AES.
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* FALSE will enable eFUSE read from & write to FUSE_AES and FUSE_USER blocks
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*
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* #define XSK_EFUSEPL_DISABLE_USER_KEY_READ FALSE
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* TRUE will disable the write to FUSE_AES & FUSE_USER key & disables read of
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* FUSE_USER
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* FALSE will enable eFUSE read from & write to FUSE_AES and FUSE_USER blocks
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*
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* Note: If any one of the above two definitions are FALSE then reading of
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* FUSE_AES & FUSE_USER is not possible
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*
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* #define XSK_EFUSEPL_DISABLE_FUSE_CNTRL_WRITE FALSE
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* TRUE will disable the eFUSE write to FUSE_CTRL block
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* FALSE will not set the eFUSE control bit, so that user can write into
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* FUSE_CTRL block later.
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*
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* #define XSK_EFUSEPL_FORCE_USE_AES_ONLY FALSE
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* TRUE will force to use secure boot with eFUSE AES key only
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* FALSE will not set the eFUSE control bit so that user can use non-secure
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* boot.
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*
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* #define XSK_EFUSEPL_DISABLE_JTAG_CHAIN FALSE
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* If TRUE then permanently sets the Zynq ARM DAP controller in bypass mode.
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* FALSE will allow Zynq ARM DAP visible through JTAG.
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*
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* #define XSK_EFUSEPL_BBRAM_KEY_DISABLE FALSE
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* XTURE will force eFUSE key to be used if booting Secure Image.
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* FALSE will not set the eFUSE control bit so that user can use secure boot
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* with BBRAM key.
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*
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* Following are the MIO pins used for PL JTAG operations.
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* User can change these pins as their discretion.
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* #define XSK_EFUSEPL_MIO_JTAG_TDI (17)
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* #define XSK_EFUSEPL_MIO_JTAG_TDO (18)
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* #define XSK_EFUSEPL_MIO_JTAG_TCK (19)
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* #define XSK_EFUSEPL_MIO_JTAG_TMS (20)
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*
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* MUX selection pin:
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* #define XSK_EFUSEPL_MIO_JTAG_MUX_SELECT (21)
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* This pin is used to select between the external JTAG or MIO driving JTAG
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* operations.
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*
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* #define XSK_EFUSEPL_MIO_MUX_SEL_DEFAULT_VAL LOW
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* LOW writes zero on the mux select line before writing the PL eFUSE
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* HIGH writes one on the mux select line before writing the PL eFUSE
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*
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* #define XSK_EFUSEPL_PROGRAM_AES_AND_USER_LOW_KEY FALSE
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* TRUE will burn the AES & User Low hash key, that is given in
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* XSK_EFUSEPL_AES_KEY & XSK_EFUSEPL_USER_LOW_KEY respectively.
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* FALSE will ignore the values given.
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*
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* Note: User cannot write AES Key & User Low Key separately.
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*
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* #define XSK_EFUSEPL_PROGRAM_USER_HIGH_KEY FALSE
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* TRUE will burn the User High hash key, that is given in
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* XSK_EFUSEPL_AES_KEY & XSK_EFUSEPL_USER_LOW_KEY respectively.
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* FALSE will ignore the values given.
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*
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* #define XSK_EFUSEPL_AES_KEY
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* "0000000000000000000000000000000000000000000000000000000000000000"
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* The value mentioned in this will be converted to hex buffer and written
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* into the PL eFUSE array when write API used. This value should be the
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* PPK(Primary Public Key) hash given in string format. It should be 64
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* characters long, valid characters are 0-9,a-f,A-F. Any other character
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* is considered as invalid string and will not burn AES Key. Note that,
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* for writing the AES Key, XSK_EFUSEPL_PROGRAM_AES_AND_USER_LOW_KEY should
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* have TRUE value.
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*
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* #define XSK_EFUSEPL_USER_LOW_KEY "00"
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* The value mentioned in this will be converted to hex buffer and written
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* into the PL eFUSE array when write API used. This value should be the
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* User Low Key given in string format. It should be 2 characters long, valid
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* characters are 0-9,a-f,A-F. Any other character is considered as invalid
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* string and will not burn User Low Key. Note that, for writing the AES Key,
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* XSK_EFUSEPL_PROGRAM_AES_AND_USER_LOW_KEY should have TRUE value.
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*
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*
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* #define XSK_EFUSEPL_USER_HIGH_KEY "000000"
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* The value mentioned in this will be converted to hex buffer and written
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* into the PL eFUSE array when write API used. This value should be the User
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* High Key given in string format. It should be 6 characters long, valid
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* characters are 0-9,a-f,A-F. Any other character is considered as invalid
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* string and will not burn User High Key. Note that, for writing the AES
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* Key, XSK_EFUSEPL_PROGRAM_USER_HIGH_KEY should have TRUE value.
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*
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* BBRAM related definitions:
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*-----------------------------------------------------------------------------
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* #define XSK_BBRAM_FORCE_PCYCLE_RECONFIG FALSE
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* If TRUE then part has to be power cycled to be
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* able to be reconfigured
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* #define XSK_BBRAM_DISABLE_JTAG_CHAIN FALSE
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* If TRUE then permanently sets the Zynq
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* ARM DAP controller in bypass mode
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* MIO pins used for JTAG signals. Can be changed as per hardware.
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* #define XSK_BBRAM_MIO_JTAG_TDI (17)
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* #define XSK_BBRAM_MIO_JTAG_TDO (21)
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* #define XSK_BBRAM_MIO_JTAG_TCK (19)
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* #define XSK_BBRAM_MIO_JTAG_TMS (20)
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* #define XSK_BBRAM_MIO_JTAG_MUX_SELECT (11)
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* #define XSK_BBRAM_MIO_MUX_SEL_DEFAULT_VAL LOW
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* Default value to enable the PL JTAG
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* This is the 256 bit key to be programmed into BBRAM.
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* This should entered by user in HEX.
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* #define XSK_BBRAM_AES_KEY
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* "349de4571ae6d88de23de65489acf67000ff5ec901ae3d409aabbce4549812dd"
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* #define XSK_BBRAM_AES_KEY_SIZE_IN_BITS 256
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*
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* User configurable parameters for PL eFUSE for Kintex Ultrascale
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* -----------------------------------------------------------------------
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* #define XSK_EFUSEPL_DISABLE_AES_KEY_READ FALSE
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* TRUE will permanently disables the write to FUSE_AES and
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* check CRC for AES key by programming control bit of FUSE.
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* FALSE will not modify this control bit of eFuse.
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*
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* #define XSK_EFUSEPL_DISABLE_USER_KEY_READ FALSE
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* TRUE will permanently disables the write to FUSE_USER and
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* read of FUSE_USER key by programming control bit of FUSE.
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* FALSE will not modify this control bit of eFuse.
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*
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* #define XSK_EFUSEPL_DISABLE_SECURE_READ FALSE
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* TRUE will permanently disables the write to FUSE_Secure block
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* and reading of secure block by programming control bit of FUSE.
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* FALSE will not modify this control bit of eFuse.
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*
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* #define XSK_EFUSEPL_DISABLE_FUSE_CNTRL_WRITE FALSE
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* TRUE will permanently disables the write to FUSE_CNTRL block
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* by programming control bit of FUSE.
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* FALSE will not modify this control bit of eFuse.
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*
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* #define XSK_EFUSEPL_DISABLE_RSA_KEY_READ FALSE
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* TRUE will permanently disables the write to FUSE_RSA block and
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* reading of FUSE_RSA Hash by programming control bit of FUSE.
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* FALSE will not modify this control bit of eFuse.
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*
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* #define XSK_EFUSEPL_DISABLE_KEY_WRITE FALSE
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* TRUE will permanently disables the write to FUSE_AES block by
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* programming control bit of FUSE.
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* FALSE will not modify this control bit of eFuse.
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*
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* #define XSK_EFUSEPL_DISABLE_USER_KEY_WRITE FALSE
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* TRUE will permanently disables the write to FUSE_USER block
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* by programming control bit of FUSE.
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* FALSE will not modify this control bit of eFuse.
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*
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* #define XSK_EFUSEPL_DISABLE_SECURE_WRITE FALSE
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* TRUE will permanently disables the write to FUSE_SECURE block
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* by programming control bit of FUSE.
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* FALSE will not modify this control bit of eFuse.
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*
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* #define XSK_EFUSEPL_DISABLE_RSA_HASH_WRITE FALSE
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* TRUE will permanently disables the write to FUSE_RSA authentication
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* key by programming control bit of FUSE.
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* FALSE will not modify this control bit of eFuse.
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*
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* #define XSK_EFUSEPL_ALLOW_ENCRYPTED_ONLY FALSE
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* TRUE will permanently allows encrypted bitstream only.
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* FALSE will not modify this Secure bit of eFuse.
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*
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* #define XSK_EFUSEPL_FORCE_USE_FUSE_AES_ONLY FALSE
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* TRUE then allows only FUSE's AES key as source of encryption
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* FALSE then allows FPGA to configure an unencrypted bitstream or
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* bitstream encrypted using key stored BBRAM or eFuse.
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*
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* #define XSK_EFUSEPL_ENABLE_RSA_AUTH FALSE
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* TRUE will enable RSA authentication of bitstream
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* FALSE will not modify this secure bit of eFuse.
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*
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* #define XSK_EFUSEPL_DISABLE_JTAG_CHAIN FALSE
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* TRUE will disable JTAG permanently.
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* FALSE will not modify this secure bit of eFuse.
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*
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* #define XSK_EFUSEPL_DISABLE_TEST_ACCESS FALSE
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* TRUE will disables Xilinx test access.
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* FALSE will not modify this secure bit of eFuse.
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*
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* #define XSK_EFUSEPL_DISABLE_DECODER FALSE
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* TRUE will disables decoder completely.
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* FALSE will not modify this secure bit of eFuse.
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*
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* In Ultrascale GPIO pins used for connecting MASTER_JTAG pins to access
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* eFUSE
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* Following are the GPIO pins and user can change these pins
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* #define XSK_EFUSEPL_AXI_GPIO_JTAG_TDO (0)
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* #define XSK_EFUSEPL_AXI_GPIO_JTAG_TDI (0)
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* #define XSK_EFUSEPL_AXI_GPIO_JTAG_TMS (1)
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* #define XSK_EFUSEPL_AXI_GPIO_JTAG_TCK (2)
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*
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* #define XSK_EFUSEPL_GPIO_INPUT_CH (2)
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* This macro is for providing channel number of ALL INPUTS connected (TDO)
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* #define XSK_EFUSEPL_GPIO_OUTPUT_CH (1)
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* This macro is for providing channel number of ALL OUTPUTS connected
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* (TDI, TCK, TMS)
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*
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* NOTE: All inputs and outputs of GPIO can be configured in single
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* channel also
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* i.e XSK_EFUSEPL_GPIO_INPUT_CH = XSK_EFUSEPL_GPIO_OUTPUT_CH = 1 or 2.
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* Among (TDI, TCK, TMS) Outputs of GPIO cannot be connected to different
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* GPIO channels all the 3 signals should be in same channel.
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* TDO can be a other channel of (TDI, TCK, TMS) or the same.
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*
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* #define XSK_EFUSEPL_PROGRAM_AES_KEY_ULTRA FALSE
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* TRUE will burn the AES key given in XSK_EFUSEPL_AES_KEY.
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* FALSE will ignore the values given.
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*
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* #define XSK_EFUSEPL_PROGRAM_USER_KEY_ULTRA FALSE
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* TRUE will burn User key given in XSK_EFUSEPL_USER_KEY
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* FALSE will ignore the values given.
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*
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* #define XSK_EFUSEPL_PROGRAM_RSA_HASH_ULTRA FALSE
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* TRUE will burn RSA hash given in XSK_EFUSEPL_RSA_KEY_HASH_VALUE
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* FALSE will ignore the values given.
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*
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* #define XSK_EFUSEPL_CHECK_AES_KEY_ULTRA FALSE
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* TRUE will perform CRC check of FUSE_AES with provided CRC value in macro
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* XSK_EFUSEPL_CRC_OF_EXPECTED_AES_KEY.
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* And result of CRC checck will be updated in XilSKey_EPl instance
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* parameter AESKeyMatched with either TRUE or FALSE.
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* FALSE CRC check of FUSE_AES will not be performed.
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*
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* #define XSK_EFUSEPL_READ_USER_KEY_ULTRA FALSE
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* TRUE will read FUSE_USER from Ultrascale's eFuse and updates in
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* XilSKey_EPl instance parameter UserKeyReadback
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* FALSE FUSE_USER key read will not be performed.
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*
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* #define XSK_EFUSEPL_READ_RSA_HASH_ULTRA FALSE
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* TRUE will read FUSE_USER from Ultrascale's eFuse and updates in
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* XilSKey_EPl instance parameter RSAHashReadback
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* FALSE FUSE_RSA_HASH read will not be performed.
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*
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* #define XSK_EFUSEPL_AES_KEY
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* "0000000000000000000000000000000000000000000000000000000000000000"
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* The value mentioned in this will be converted to hex buffer and written
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* into the PL eFUSE array when write API used. This value should be the
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* PPK(Primary Public Key) hash given in string format. It should be 64
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* characters long, valid characters are 0-9,a-f,A-F. Any other character
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* is considered as invalid string and will not burn AES Key. Note that,
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* for writing the AES Key, XSK_EFUSEPL_PROGRAM_AES_KEY_ULTRA should
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* have TRUE value.
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*
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* #define XSK_EFUSEPL_USER_KEY "00000000"
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* The value mentioned in this will be converted to hex buffer and written
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* into the PL eFUSE array when write API used. This value should be the
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* User Key given in string format. It should be 8 characters long, valid
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* characters are 0-9,a-f,A-F. Any other character is considered as invalid
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* string and will not burn User Key. Note that, for writing the User Key,
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* XSK_EFUSEPL_PROGRAM_USER_KEY_ULTRA should have TRUE value.
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*
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* #define XSK_EFUSEPL_RSA_KEY_HASH_VALUE
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* "0000000000000000000000000000000000000000000000 \
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* 00000000000000000000000000000000000000000000000000"
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* The value mentioned in this will be converted to hex buffer and written
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* into the PL eFUSE array when write API used. This value should be the
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* RSA Key hash given in string format. It should be 96 characters long,
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* valid characters are 0-9,a-f,A-F. Any other character is considered as
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* invalid string and will not burn RSA hash value. Note that, for writing
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* the RSA hash, XSK_EFUSEPL_PROGRAM_RSA_HASH_ULTRA should have TRUE value.
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*
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* #define XSK_EFUSEPL_CRC_OF_EXPECTED_AES_KEY 0x621C42AA
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* 0x621C42AA is hexadecimal CRC value of FUSE_AES with all Zeros.
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* Expected FUSE_AES key's CRC value has to be updated in place of
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* 0x621C42AA.
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* For Checking CRC of FUSE_AES XSK_EFUSEPL_CHECK_AES_KEY_ULTRA macro
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* should be TRUE otherwise CRC check will not be performed.
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* For calculation of AES key's CRC one can use
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* u32 XilSKey_CrcCalculation(u8 *Key) API or reverse polynomial
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* 0x82F63B78.
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*
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* NOTE:Please make sure you have sufficient heap and stack to run this
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* application.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- --------------------------------------------------------
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* 1.00a rpoolla 04/26/13 First release
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* 1.01a hk 09/18/13 Added BBRAM related definitions
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* 3.00 vns 31/07/15 Added efuse functionality for Ultrascale.
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* In Ultrascale GPIO pins and channels macros are added
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* to access Master Jtag primitive and also added
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* extra control bits and secure bits for Ultrascale's
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* eFuse.
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* 4.00 vns 09/10/15 Added DFT JTAG disable and DFT MODE disable programming
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* options for Zynq eFuse PS.
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*
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* </pre>
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*
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*
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******************************************************************************/
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#ifndef XILSKEY_INPUT_H
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#define XILSKEY_INPUT_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions ******************************/
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/***************** Macros (Inline Functions) Definitions ********************/
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#define XSK_EFUSEPL_DRIVER
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#define XSK_EFUSEPS_DRIVER
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#ifdef XSK_EFUSEPL_DRIVER
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/**
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* Voltage level definitions
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*/
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#define LOW 0
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#define HIGH 1
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/**
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* Definition of Zynq PL
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* ----------------------------------------------------------
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*/
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#ifdef XSK_ARM_PLATFORM
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/**
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* Following defines should be defined either TRUE or FALSE.
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* --------------------------------------------------------
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*/
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#define XSK_EFUSEPL_FORCE_PCYCLE_RECONFIG FALSE /**< If TRUE then part
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* has to be power cycled to be
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* able to be reconfigured
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*/
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#define XSK_EFUSEPL_DISABLE_KEY_WRITE FALSE /**< If TRUE will disable
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* eFUSE write to FUSE_AES and
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* FUSE_USER blocks
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*/
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#define XSK_EFUSEPL_DISABLE_AES_KEY_READ FALSE /**< If TRUE will disable
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* eFUSE read to FUSE_AES block and
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* also disables eFUSEwrite to
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* FUSE_AES and FUSE_USER blocks
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*/
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#define XSK_EFUSEPL_DISABLE_USER_KEY_READ FALSE /**< If TRUE will disable
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* eFUSE read to FUSE_USER block
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* and also disables eFUSE write
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* to FUSE_AES and FUSE_USER
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* blocks
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*/
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#define XSK_EFUSEPL_DISABLE_FUSE_CNTRL_WRITE FALSE /**< If TRUE will
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* disable eFUSE write to
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* FUSE_CNTRL block
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*/
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#define XSK_EFUSEPL_FORCE_USE_AES_ONLY FALSE /**< If TRUE will force
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* to use Secure boot with eFUSE
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* key only
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*/
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#define XSK_EFUSEPL_DISABLE_JTAG_CHAIN FALSE /**< If TRUE then
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* permanently sets the Zynq
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* ARM DAP controller in bypass
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* mode
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*/
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#define XSK_EFUSEPL_BBRAM_KEY_DISABLE FALSE /**< If TRUE will force
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* eFUSE key to be used if
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* booting Secure Image
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*/
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/**
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* Following defines should be given in the decimal/hexa-decimal values.
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* For example :
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* XSK_EFUSEPL_MIO_JTAG_TCK 34 OR 0x22
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* XSK_EFUSEPL_MIO_JTAG_TMS 35 OR 0x23
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* etc...
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*/
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#define XSK_EFUSEPL_MIO_JTAG_TDI (17) /**< JTAG MIO pin for TDI */
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#define XSK_EFUSEPL_MIO_JTAG_TDO (21) /**< JTAG MIO pin for TDO */
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#define XSK_EFUSEPL_MIO_JTAG_TCK (19) /**< JTAG MIO pin for TCK */
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#define XSK_EFUSEPL_MIO_JTAG_TMS (20) /**< JTAG MIO pin for TMS */
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#define XSK_EFUSEPL_MIO_JTAG_MUX_SELECT (11) /**< JTAG MIO pin for
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* MUX selection line
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*/
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/**
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*
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*/
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#define XSK_EFUSEPL_MIO_MUX_SEL_DEFAULT_VAL LOW /**< Default value to
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* enable the PL JTAG
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*/
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/**
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* Following is the define to select if the user wants to select AES key and USER
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* low key OR USER high key or BOTH
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*/
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#define XSK_EFUSEPL_PROGRAM_AES_AND_USER_LOW_KEY FALSE /**< TRUE burns
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* the AES & user low key
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*/
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#define XSK_EFUSEPL_PROGRAM_USER_HIGH_KEY FALSE /**< TRUE burns
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* the user high key
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*/
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/**
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* Following defines should be given in the form of hex string.
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* The length of AES_KEY string must me 64 and for USER_KEY must be 8.
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*/
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#define XSK_EFUSEPL_AES_KEY "0000000000000000000000000000000000000000000000000000000000000000"
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#define XSK_EFUSEPL_USER_LOW_KEY "00"
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#define XSK_EFUSEPL_USER_HIGH_KEY "000000"
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/**
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* Definitions for Kintex Ultrascale's eFuse
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* ---------------------------------------------
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*/
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#else
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/**
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* Following is the define to select if the user wants to program control bits
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*/
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#define XSK_EFUSEPL_DISABLE_AES_KEY_READ FALSE /**< If TRUE will disable
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* AES key crc check
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* andprogramming
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*/
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#define XSK_EFUSEPL_DISABLE_USER_KEY_READ FALSE /**< If TRUE will disable
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* User key reading and
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* programming
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*/
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#define XSK_EFUSEPL_DISABLE_SECURE_READ FALSE /**< If TRUE will disable
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* secure block reading
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* and programming
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*/
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#define XSK_EFUSEPL_DISABLE_FUSE_CNTRL_WRITE FALSE /**< If TRUE will disable
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* programming control
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* bits
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*/
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#define XSK_EFUSEPL_DISABLE_RSA_KEY_READ FALSE /**< If TRUE will disable
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* RSA key hash reading
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* and programming
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*/
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#define XSK_EFUSEPL_DISABLE_KEY_WRITE FALSE /**< If TRUE will disable
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* AES key programming
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*/
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#define XSK_EFUSEPL_DISABLE_USER_KEY_WRITE FALSE /**< If TRUE will disable
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* Programming User
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* key
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*/
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#define XSK_EFUSEPL_DISABLE_SECURE_WRITE FALSE /**< If TRUE will disable
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* programming Secure block
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*/
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#define XSK_EFUSEPL_DISABLE_RSA_HASH_WRITE FALSE /**< If TRUE will disable
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* programming to RSA key
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* hash
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*/
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/**
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* Following is the define to select if the user wants to program Secure bits
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*/
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#define XSK_EFUSEPL_ALLOW_ENCRYPTED_ONLY FALSE /**< If TRUE will force
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* to use only encrypted
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* bitstreams
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*/
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#define XSK_EFUSEPL_FORCE_USE_FUSE_AES_ONLY FALSE /**< If TRUE will force
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* to use Secure boot
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* with eFUSE key only.
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*/
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#define XSK_EFUSEPL_ENABLE_RSA_AUTH FALSE /**< If TRUE will enable
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* RSA authentication of
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* bitstream */
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#define XSK_EFUSEPL_DISABLE_JTAG_CHAIN FALSE /**< If TRUE then
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* permanently sets the Ultrascale
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* device in bypass mode
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*/
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#define XSK_EFUSEPL_DISABLE_TEST_ACCESS FALSE /**< If TRUE will disable internal
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* test access for ULTRASCALE
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*/
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#define XSK_EFUSEPL_DISABLE_DECODER FALSE /**< If TRUE will
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* Disable's decoder
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*/
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/**
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* Following defines should be given in decimal/hexa-decimal values.
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* These are to be defined for Ultrascale Microblaze
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* AXI GPIO pin numbers connected to MASTER JTAG primitive and corresponding
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* channel numbers for GPIO pins
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*/
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#define XSK_EFUSEPL_AXI_GPIO_JTAG_TDO (0) /**< MASTER JTAG GPIO
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* pin for TDO */
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#define XSK_EFUSEPL_AXI_GPIO_JTAG_TDI (0) /**< MASTER JTAG GPIO
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* pin for TDI */
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#define XSK_EFUSEPL_AXI_GPIO_JTAG_TMS (1) /**< MASTER JTAG GPIO
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* pin for TMS */
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#define XSK_EFUSEPL_AXI_GPIO_JTAG_TCK (2) /**< MASTER JTAG GPIO
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* pin for TCK */
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#define XSK_EFUSEPL_GPIO_INPUT_CH (2) /**< GPIO Channel of TDO
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* pin connected */
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#define XSK_EFUSEPL_GPIO_OUTPUT_CH (1) /**< GPIO Channel of TDI,
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* * TMS and TCK pin connected */
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/**
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* Following is the define to select if the user wants to select AES, User, RSA and RES keys
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* for Ultrascale
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*/
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/* For Programming keys */
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#define XSK_EFUSEPL_PROGRAM_AES_KEY FALSE /**< TRUE burns
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* the AES key
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*/
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#define XSK_EFUSEPL_PROGRAM_USER_KEY FALSE /**< TRUE burns
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* the USER key
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*/
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#define XSK_EFUSEPL_PROGRAM_RSA_KEY_HASH FALSE /**< TRUE burns
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* the RSA hash
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*/
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/* For reading keys */
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#define XSK_EFUSEPL_CHECK_AES_KEY_CRC FALSE /**< TRUE checks
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* AES key with
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* below provided CRC
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*/
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#define XSK_EFUSEPL_READ_USER_KEY FALSE /**< TRUE read
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* USER key
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*/
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#define XSK_EFUSEPL_READ_RSA_KEY_HASH FALSE /**< TRUE read
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* RSA Hash value
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*/
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/**
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* Following defines should be given in the form of hex string.
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* The length of AES_KEY string must me 64 and for USER_KEY must be 8.
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*/
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#define XSK_EFUSEPL_AES_KEY "0000000000000000000000000000000000000000000000000000000000000000"
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#define XSK_EFUSEPL_USER_KEY "00000000"
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/**
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* Following defines should be given only for Ultrascale the length of
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* RSA string must be 96
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*/
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#define XSK_EFUSEPL_RSA_KEY_HASH_VALUE "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
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/**
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* Following define is CRC value of expected AES key
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*/
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#define XSK_EFUSEPL_CRC_OF_EXPECTED_AES_KEY 0x621C42AA
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#endif
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#endif /*XSK_EFUSEPL_DRIVER*/
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/**
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* Similarly we can define PS eFUSE related data
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* ---------------------------------------------
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*/
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#ifdef XSK_EFUSEPS_DRIVER
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#define XSK_EFUSEPS_ENABLE_WRITE_PROTECT FALSE /**< Enable the eFUSE Array
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* write protection
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*/
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#define XSK_EFUSEPS_ENABLE_RSA_AUTH FALSE /**< Enable the RSA
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* Authentication eFUSE Bit
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*/
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#define XSK_EFUSEPS_ENABLE_ROM_128K_CRC FALSE /**< Enable the ROM
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* code 128K crc eFUSE Bit
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*/
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#define XSK_EFUSEPS_DISABLE_DFT_JTAG FALSE /**< DFT jtag
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* Disable
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*/
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#define XSK_EFUSEPS_DISABLE_DFT_MODE FALSE /**< DFT mode
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* Disable
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*/
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#define XSK_EFUSEPS_ENABLE_RSA_KEY_HASH FALSE /**< Enabling this
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* RsaKeyHashValue[64] is
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* written to eFUSE array
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*/
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#define XSK_EFUSEPS_RSA_KEY_HASH_VALUE "0000000000000000000000000000000000000000000000000000000000000000"
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#endif /* End of XSK_EFUSEPS_DRIVER */
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/*
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* Definitions for BBRAM
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*/
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/**< If TRUE then part
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|
* has to be power cycled to be
|
|
* able to be reconfigured
|
|
*/
|
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#define XSK_BBRAM_FORCE_PCYCLE_RECONFIG FALSE
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|
|
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/**< If TRUE then
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|
* permanently sets the Zynq
|
|
* ARM DAP controller in bypass
|
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* mode
|
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*/
|
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#define XSK_BBRAM_DISABLE_JTAG_CHAIN FALSE
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#define XSK_BBRAM_MIO_JTAG_TDI (17) /**< JTAG MIO pin for TDI */
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#define XSK_BBRAM_MIO_JTAG_TDO (21) /**< JTAG MIO pin for TDO */
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#define XSK_BBRAM_MIO_JTAG_TCK (19) /**< JTAG MIO pin for TCK */
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#define XSK_BBRAM_MIO_JTAG_TMS (20) /**< JTAG MIO pin for TMS */
|
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#define XSK_BBRAM_MIO_JTAG_MUX_SELECT (11) /**< JTAG MIO pin for
|
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* MUX selection line
|
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*/
|
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/**< Default value to
|
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* enable the PL JTAG
|
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*/
|
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#define XSK_BBRAM_MIO_MUX_SEL_DEFAULT_VAL 0
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/**
|
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* This is the 256 bit key to be programmed into BBRAM.
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* This should entered by user in HEX.
|
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*/
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#define XSK_BBRAM_AES_KEY "349de4571ae6d88de23de65489acf67000ff5ec901ae3d409aabbce4549812dd"
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|
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#define XSK_BBRAM_AES_KEY_SIZE_IN_BITS 256
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|
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/*
|
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* End of definitions for BBRAM
|
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*/
|
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|
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/************************** Function Prototypes *****************************/
|
|
/****************************************************************************/
|
|
#ifdef __cplusplus
|
|
}
|
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#endif
|
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|
#endif /*XILSKEY_INPUT_H*/
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