365de9549f
To add ultrascale's efuse functionality added GPIO pins and GPIO channels to access master JTAG, Fpga_Flag to tell the FPGA series, AES CRC check flag and AES CRC value, RSA key hash to program and RSA key hash read back and control and secure parameters in PL instance and modified IR length macro ZYNQ_TAP_IR_LENGTH to TAP_IR_LENGTH as IR length is same for both Zynq and Ultrasale. Signed-off-by: VNSL Durga <vnsldurg@xilinx.com> Reviewed-by: Harini Katakam <harinik@xilinx.com> |
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| bsp | ||
| sw_apps | ||
| sw_services | ||