2c8f92039d
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
727 lines
28 KiB
C
Executable file
727 lines
28 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xaxidma.h
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*
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* This is the driver API for the AXI DMA engine.
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*
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* For a full description of DMA features, please see the hardware spec. This
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* driver supports the following features:
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*
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* - Scatter-Gather DMA (SGDMA)
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* - Simple DMA
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* - Interrupts
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* - Programmable interrupt coalescing for SGDMA
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* - APIs to manage Buffer Descriptors (BD) movement to and from the SGDMA
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* engine
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*
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* <b>Simple DMA</b>
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*
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* Simple DMA allows the application to define a single transaction between DMA
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* and Device. It has two channels: one from the DMA to Device and the other
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* from Device to DMA. Application has to set the buffer address and
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* length fields to initiate the transfer in respective channel.
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*
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* <b>Transactions</b>
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*
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* The object used to describe a transaction is referred to as a Buffer
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* Descriptor (BD). Buffer descriptors are allocated in the user application.
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* The user application needs to set buffer address, transfer length, and
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* control information for this transfer. The control information includes
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* SOF and EOF. Definition of those masks are in xaxidma_hw.h
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*
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* <b>Scatter-Gather DMA</b>
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*
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* SGDMA allows the application to define a list of transactions in memory which
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* the hardware will process without further application intervention. During
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* this time, the application is free to continue adding more work to keep the
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* Hardware busy.
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*
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* User can check for the completion of transactions through polling the
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* hardware, or interrupts.
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*
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* SGDMA processes whole packets. A packet is defined as a series of
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* data bytes that represent a message. SGDMA allows a packet of data to be
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* broken up into one or more transactions. For example, take an Ethernet IP
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* packet which consists of a 14 byte header followed by a 1 or more bytes of
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* payload. With SGDMA, the application may point a BD to the header and another
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* BD to the payload, then transfer them as a single message. This strategy can
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* make a TCP/IP stack more efficient by allowing it to keep packet header and
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* data in different memory regions instead of assembling packets into
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* contiguous blocks of memory.
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*
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* <b>BD Ring Management</b>
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*
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* BD rings are shared by the software and the hardware.
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*
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* The hardware expects BDs to be setup as a linked list. The DMA hardware walks
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* through the list by following the next pointer field of a completed BD.
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* The hardware stops processing when the just completed BD is the same as the
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* BD specified in the Tail Ptr register in the hardware.
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*
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* The last BD in the ring is linked to the first BD in the ring.
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*
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* All BD management are done inside the driver. The user application should not
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* directly modify the BD fields. Modifications to the BD fields should always
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* go through the specific API functions.
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*
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* Within the ring, the driver maintains four groups of BDs. Each group consists
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* of 0 or more adjacent BDs:
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*
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* - Free: The BDs that can be allocated by the application with
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* XAxiDma_BdRingAlloc().
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*
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* - Pre-process: The BDs that have been allocated with
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* XAxiDma_BdRingAlloc(). These BDs are under application control. The
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* application modifies these BDs through driver API to prepare them
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* for DMA transactions.
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*
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* - Hardware: The BDs that have been enqueued to hardware with
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* XAxiDma_BdRingToHw(). These BDs are under hardware control and may be in a
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* state of awaiting hardware processing, in process, or processed by
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* hardware. It is considered an error for the application to change BDs
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* while they are in this group. Doing so can cause data corruption and lead
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* to system instability.
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*
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* - Post-process: The BDs that have been processed by hardware and have
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* been extracted from the Hardware group with XAxiDma_BdRingFromHw().
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* These BDs are under application control. The application can check the
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* transfer status of these BDs. The application use XAxiDma_BdRingFree()
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* to put them into the Free group.
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*
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* BDs are expected to transition in the following way for continuous
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* DMA transfers:
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* <pre>
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*
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* XAxiDma_BdRingAlloc() XAxiDma_BdRingToHw()
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* Free ------------------------> Pre-process ----------------------> Hardware
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* |
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* /|\ |
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* | XAxiDma_BdRingFree() XAxiDma_BdRingFromHw() |
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* +--------------------------- Post-process <----------------------+
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*
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* </pre>
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*
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* When a DMA transfer is to be cancelled before enqueuing to hardware,
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* application can return the requested BDs to the Free group using
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* XAxiDma_BdRingUnAlloc(), as shown below:
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* <pre>
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*
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* XAxiDma_BdRingUnAlloc()
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* Free <----------------------- Pre-process
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*
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* </pre>
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*
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* The API provides functions for BD list traversal:
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* - XAxiDma_BdRingNext()
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* - XAxiDma_BdRingPrev()
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*
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* These functions should be used with care as they do not understand where
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* one group ends and another begins.
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*
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* <b>SGDMA Descriptor Ring Creation</b>
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*
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* BD ring is created using XAxiDma_BdRingCreate(). The memory for the BD ring
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* is allocated by the application, and it has to be contiguous. Physical
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* address is required to setup the BD ring.
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*
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* The applicaiton can use XAxiDma_BdRingMemCalc() to find out the amount of
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* memory needed for a certain number of BDs. XAxiDma_BdRingCntCalc() can be
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* used to find out how many BDs can be allocated for certain amount of memory.
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*
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* A helper function, XAxiDma_BdRingClone(), can speed up the BD ring setup if
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* the BDs have same types of controls, for example, SOF and EOF. After
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* using the XAxiDma_BdRingClone(), the application only needs to setup the
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* buffer address and transfer length. Note that certain BDs in one packet,
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* for example, the first BD and the last BD, may need to setup special
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* control information.
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*
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* <b>Descriptor Ring State Machine</b>
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*
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* There are two states of the BD ring:
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*
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* - HALTED (H), where hardware is not running
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*
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* - NOT HALTED (NH), where hardware is running
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*
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* The following diagram shows the state transition for the DMA engine:
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*
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* <pre>
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* _____ XAxiDma_StartBdRingHw(), or XAxiDma_BdRingStart(), ______
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* | | or XAxiDma_Resume() | |
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* | H |----------------------------------------------------->| NH |
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* | |<-----------------------------------------------------| |
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* ----- XAxiDma_Pause() or XAxiDma_Reset() ------
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* </pre>
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*
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* <b>Interrupt Coalescing</b>
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*
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* SGDMA provides control over the frequency of interrupts through interrupt
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* coalescing. The DMA engine provides two ways to tune the interrupt
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* coalescing:
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*
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* - The packet threshold counter. Interrupt will fire once the
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* programmable number of packets have been processed by the engine.
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*
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* - The packet delay timer counter. Interrupt will fire once the
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* programmable amount of time has passed after processing the last packet,
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* and no new packets to process. Note that the interrupt will only fire if
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* at least one packet has been processed.
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*
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* <b> Interrupt </b>
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*
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* Interrupts are handled by the user application. Each DMA channel has its own
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* interrupt ID. The driver provides APIs to enable/disable interrupt,
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* and tune the interrupt frequency regarding to packet processing frequency.
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*
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* <b> Software Initialization </b>
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*
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*
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* To use the Simple mode DMA engine for transfers, the following setup is
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* required:
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*
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* - DMA Initialization using XAxiDma_CfgInitialize() function. This step
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* initializes a driver instance for the given DMA engine and resets the
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* engine.
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*
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* - Enable interrupts if chosen to use interrupt mode. The application is
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* responsible for setting up the interrupt system, which includes providing
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* and connecting interrupt handlers and call back functions, before
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* enabling the interrupts.
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*
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* - Set the buffer address and length field in respective channels to start
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* the DMA transfer
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*
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* To use the SG mode DMA engine for transfers, the following setup are
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* required:
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*
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* - DMA Initialization using XAxiDma_CfgInitialize() function. This step
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* initializes a driver instance for the given DMA engine and resets the
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* engine.
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*
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* - BD Ring creation. A BD ring is needed per DMA channel and can be built by
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* calling XAxiDma_BdRingCreate().
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*
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* - Enable interrupts if chose to use interrupt mode. The application is
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* responsible for setting up the interrupt system, which includes providing
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* and connecting interrupt handlers and call back functions, before
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* enabling the interrupts.
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*
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* - Start a DMA transfer: Call XAxiDma_BdRingStart() to start a transfer for
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* the first time or after a reset, and XAxiDma_BdRingToHw() if the channel
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* is already started. Calling XAxiDma_BdRingToHw() when a DMA channel is not
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* running will not put the BDs to the hardware, and the BDs will be processed
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* later when the DMA channel is started through XAxiDma_BdRingStart().
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*
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* <b> How to start DMA transactions </b>
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*
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* The user application uses XAxiDma_BdRingToHw() to submit BDs to the hardware
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* to start DMA transfers.
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*
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* For both channels, if the DMA engine is currently stopped (using
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* XAxiDma_Pause()), the newly added BDs will be accepted but not processed
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* until the DMA engine is started, using XAxiDma_BdRingStart(), or resumed,
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* using XAxiDma_Resume().
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*
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* <b> Software Post-Processing on completed DMA transactions </b>
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*
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* If the interrupt system has been set up and the interrupts are enabled,
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* a DMA channels notifies the software about the completion of a transfer
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* through interrupts. Otherwise, the user application can poll for
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* completions of the BDs, using XAxiDma_BdRingFromHw() or
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* XAxiDma_BdHwCompleted().
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*
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* - Once BDs are finished by a channel, the application first needs to fetch
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* them from the channel using XAxiDma_BdRingFromHw().
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*
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* - On the TX side, the application now could free the data buffers attached to
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* those BDs as the data in the buffers has been transmitted.
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*
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* - On the RX side, the application now could use the received data in the
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* buffers attached to those BDs.
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*
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* - For both channels, completed BDs need to be put back to the Free group
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* using XAxiDma_BdRingFree(), so they can be used for future transactions.
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*
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* - On the RX side, it is the application's responsibility to have BDs ready
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* to receive data at any time. Otherwise, the RX channel refuses to
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* accept any data if it has no RX BDs.
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*
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* <b> Examples </b>
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*
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* We provide five examples to show how to use the driver API:
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* - One for SG interrupt mode (xaxidma_example_sg_intr.c), multiple BD/packets transfer
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* - One for SG polling mode (xaxidma_example_sg_poll.c), single BD transfer.
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* - One for SG polling mode (xaxidma_poll_multi_pkts.c), multiple BD/packets transfer
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* - One for simple polling mode (xaxidma_example_simple_poll.c)
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* - One for simple Interrupt mode (xaxidma_example_simple_intr.c)
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*
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* <b> Address Translation </b>
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*
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* All buffer addresses and BD addresses for the hardware are physical
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* addresses. The user application is responsible to provide physical buffer
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* address for the BD upon BD ring creation. The user application accesses BD
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* through its virtual addess. The driver maintains the address translation
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* between the physical and virtual address for BDs.
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*
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* <b> Cache Coherency </b>
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*
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* This driver expects all application buffers attached to BDs to be in cache
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* coherent memory. If cache is used in the system, buffers for transmit MUST
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* be flushed from the cache before passing the associated BD to this driver.
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* Buffers for receive MUST be invalidated before accessing the data.
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*
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* <b> Alignment </b>
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*
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* For BDs:
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*
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* Minimum alignment is defined by the constant XAXIDMA_BD_MINIMUM_ALIGNMENT.
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* This is the smallest alignment allowed by both hardware and software for them
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* to properly work.
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*
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* If the descriptor ring is to be placed in cached memory, alignment also MUST
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* be at least the processor's cache-line size. Otherwise, system instability
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* occurs. For alignment larger than the cache line size, multiple cache line
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* size alignment is required.
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*
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* Aside from the initial creation of the descriptor ring (see
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* XAxiDma_BdRingCreate()), there are no other run-time checks for proper
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* alignment of BDs.
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*
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* For application data buffers:
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*
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* Application data buffers may reside on any alignment if DRE is built into the
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* hardware. Otherwise, application data buffer must be word-aligned. The word
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* is defined by XPAR_AXIDMA_0_M_AXIS_MM2S_TDATA_WIDTH for transmit and
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* XPAR_AXIDMA_0_S_AXIS_S2MM_TDATA_WIDTH for receive.
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*
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* For scatter gather transfers that have more than one BDs in the chain of BDs,
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* Each BD transfer length must be multiple of word too. Otherwise, internal
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* error happens in the hardware.
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*
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* <b> Error Handling </b>
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*
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* The DMA engine will halt on all error conditions. It requires the software
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* to do a reset before it can start process new transfer requests.
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*
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* <b> Restart After Stopping </b>
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*
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* After the DMA engine has been stopped (through reset or reset after an error)
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* the software keeps track of the current BD pointer when reset happens, and
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* processing of BDs can be resumed through XAxiDma_BdRingStart().
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*
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* <b> Limitations </b>
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*
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* This driver does not have any mechanisms for mutual exclusion. It is up to
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* the application to provide this protection.
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*
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* <b> Hardware Defaults & Exclusive Use </b>
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*
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* After the initialization or reset, the DMA engine is in the following
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* default mode:
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* - All interrupts are disabled.
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*
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* - Interrupt coalescing counter is 1.
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*
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* - The DMA engine is not running (halted). Each DMA channel is started
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* separately, using XAxiDma_StartBdRingHw() if no BDs are setup for transfer
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* yet, or XAxiDma_BdRingStart() otherwise.
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*
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* The driver has exclusive use of the registers and BDs. All accesses to the
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* registers and BDs should go through the driver interface.
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*
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* <b> Debug Print </b>
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*
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* To see the debug print for the driver, please put "-DDEBUG" as the extra
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* compiler flags in software platform settings. Also comment out the line in
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* xdebug.h: "#undef DEBUG".
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*
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* <b>Changes From v1.00a</b>
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*
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* . We have changes return type for XAxiDma_BdSetBufAddr() from void to int
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* . We added XAxiDma_LookupConfig() so that user does not need to look for the
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* hardware settings anymore.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a jz 05/18/10 First release
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* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
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* updated tcl file, added xaxidma_porting_guide.h
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* 3.00a jz 11/22/10 Support IP core parameters change
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* 4.00a rkv 02/22/11 Added support for simple DMA mode
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* New API added for simple DMA mode are
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* - XAxiDma_Busy
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* - XAxiDma_SimpleTransfer
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* New Macros added for simple DMA mode are
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* - XAxiDma_HasSg
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* - XAxiDma_IntrEnable
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* - XAxiDma_IntrGetEnabled
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* - XAxiDma_IntrDisable
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* - XAxiDma_IntrGetIrq
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* - XAxiDma_IntrAckIrq
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* 5.00a srt 08/25/11 Added support for memory barrier and modified
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* Cache Macros to have a common API for Microblaze
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* and Zynq.
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* 6.00a srt 01/24/12 Added support for Multi-Channel DMA mode.
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* - Changed APIs:
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* * XAxiDma_GetRxRing(InstancePtr, RingIndex)
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* * XAxiDma_Start(XAxiDma * InstancePtr, int RingIndex)
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* * XAxiDma_Started(XAxiDma * InstancePtr, int RingIndex)
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* * XAxiDma_Pause(XAxiDma * InstancePtr, int RingIndex)
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* * XAxiDma_Resume(XAxiDma * InstancePtr, int RingIndex)
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* * XAxiDma_SimpleTransfer(XAxiDma *InstancePtr,
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* u32 BuffAddr, u32 Length,
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* int Direction, int RingIndex)
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* * XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr,
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* int RingIndex)
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* * XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr,
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* int RingIndex)
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* * XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr,
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* int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex)
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* * XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr,
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* int RingIndex)
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* * XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr,
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* int RingIndex)
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* * XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr,
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* u32 LenBytes, u32 LengthMask)
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* * XAxiDma_BdGetActualLength(BdPtr, LengthMask)
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* * XAxiDma_BdGetLength(BdPtr, LengthMask)
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* - New APIs
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* * XAxiDma_SelectKeyHole(XAxiDma *InstancePtr,
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* int Direction, int Select)
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* * XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr,
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* int RingIndex)
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* 7.00a srt 06/18/12 All the APIs changed in v6_00_a are reverted back for
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* backward compatibility.
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* - New API:
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* XAxiDma_GetRxIndexRing(InstancePtr, RingIndex)
|
|
* 7.01a srt 10/26/12 - Fixed issue with driver as it fails with IP version
|
|
* < 6.00a as the parameter C_NUM_*_CHANNELS is not
|
|
* applicable.
|
|
* - Changed the logic of MCDMA BD fields Set APIs, to
|
|
* clear the field first and then set it.
|
|
* 7.02a srt 01/23/13 Replaced *_TDATA_WIDTH parameters to *_DATA_WIDTH
|
|
* (CR 691867)
|
|
* Updated DDR base address for IPI designs (CR 703656).
|
|
* 8.0 adk 19/12/13 Updated as per the New Tcl API's
|
|
* srt 01/29/14 Added support for Micro DMA Mode and cyclic mode of
|
|
* operations.
|
|
* - New APIs:
|
|
* * XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr,
|
|
* int Direction, int Select)
|
|
* * XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd*, u32)
|
|
*
|
|
* </pre>
|
|
*
|
|
******************************************************************************/
|
|
|
|
#ifndef XAXIDMA_H_ /* prevent circular inclusions */
|
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#define XAXIDMA_H_
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|
|
|
#ifdef __cplusplus
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extern "C" {
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#endif
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|
|
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/***************************** Include Files *********************************/
|
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#include "xaxidma_bdring.h"
|
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#ifdef __MICROBLAZE__
|
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#include "xenv.h"
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#else
|
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#include <string.h>
|
|
#include "xil_cache.h"
|
|
#endif
|
|
|
|
/************************** Constant Definitions *****************************/
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|
|
|
|
|
/**************************** Type Definitions *******************************/
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|
|
|
/**
|
|
* The XAxiDma driver instance data. An instance must be allocated for each DMA
|
|
* engine in use.
|
|
*/
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typedef struct XAxiDma {
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u32 RegBase; /* Virtual base address of DMA engine */
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|
|
|
int HasMm2S; /* Has transmit channel */
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int HasS2Mm; /* Has receive channel */
|
|
int Initialized; /* Driver has been initialized */
|
|
int HasSg;
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|
|
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XAxiDma_BdRing TxBdRing; /* BD container management for TX channel */
|
|
XAxiDma_BdRing RxBdRing[16]; /* BD container management for RX channel */
|
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int TxNumChannels;
|
|
int RxNumChannels;
|
|
int MicroDmaMode;
|
|
} XAxiDma;
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|
|
|
/**
|
|
* The configuration structure for AXI DMA engine
|
|
*
|
|
* This structure passes the hardware building information to the driver
|
|
*/
|
|
typedef struct {
|
|
u32 DeviceId;
|
|
u32 BaseAddr;
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|
|
|
int HasStsCntrlStrm;
|
|
int HasMm2S;
|
|
int HasMm2SDRE;
|
|
int Mm2SDataWidth;
|
|
int HasS2Mm;
|
|
int HasS2MmDRE;
|
|
int S2MmDataWidth;
|
|
int HasSg;
|
|
int Mm2sNumChannels;
|
|
int S2MmNumChannels;
|
|
int Mm2SBurstSize;
|
|
int S2MmBurstSize;
|
|
int MicroDmaMode;
|
|
} XAxiDma_Config;
|
|
|
|
|
|
/***************** Macros (Inline Functions) Definitions *********************/
|
|
/*****************************************************************************/
|
|
/**
|
|
* Get Transmit (Tx) Ring ptr
|
|
*
|
|
* Warning: This has a different API than the LLDMA driver. It now returns
|
|
* the pointer to the BD ring.
|
|
*
|
|
* @param InstancePtr is a pointer to the DMA engine instance to be
|
|
* worked on.
|
|
*
|
|
* @return Pointer to the Tx Ring
|
|
*
|
|
* @note C-style signature:
|
|
* XAxiDma_BdRing * XAxiDma_GetTxRing(XAxiDma * InstancePtr)
|
|
* This function is used only when system is configured as SG mode
|
|
*
|
|
*****************************************************************************/
|
|
#define XAxiDma_GetTxRing(InstancePtr) \
|
|
(&((InstancePtr)->TxBdRing))
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
* Get Receive (Rx) Ring ptr
|
|
*
|
|
* Warning: This has a different API than the LLDMA driver. It now returns
|
|
* the pointer to the BD ring.
|
|
*
|
|
* @param InstancePtr is a pointer to the DMA engine instance to be
|
|
* worked on.
|
|
*
|
|
* @return Pointer to the Rx Ring
|
|
*
|
|
* @note
|
|
* C-style signature:
|
|
* XAxiDma_BdRing * XAxiDma_GetRxRing(XAxiDma * InstancePtr)
|
|
* This function is used only when system is configured as SG mode
|
|
*
|
|
*****************************************************************************/
|
|
#define XAxiDma_GetRxRing(InstancePtr) \
|
|
(&((InstancePtr)->RxBdRing[0]))
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
* Get Receive (Rx) Ring ptr of a Index
|
|
*
|
|
* Warning: This has a different API than the LLDMA driver. It now returns
|
|
* the pointer to the BD ring.
|
|
*
|
|
* @param InstancePtr is a pointer to the DMA engine instance to be
|
|
* worked on.
|
|
* @param RingIndex is the channel Index.
|
|
*
|
|
* @return Pointer to the Rx Ring
|
|
*
|
|
* @note
|
|
* C-style signature:
|
|
* XAxiDma_BdRing * XAxiDma_GetRxIndexRing(XAxiDma * InstancePtr,
|
|
int RingIndex)
|
|
* This function is used only when system is configured as SG mode
|
|
*
|
|
*****************************************************************************/
|
|
#define XAxiDma_GetRxIndexRing(InstancePtr, RingIndex) \
|
|
(&((InstancePtr)->RxBdRing[RingIndex]))
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
* This function checks whether system is configured as Simple or
|
|
* Scatter Gather mode
|
|
*
|
|
* @param InstancePtr is a pointer to the DMA engine instance to be
|
|
* worked on.
|
|
*
|
|
* @return
|
|
* - TRUE if configured as SG mode
|
|
* - FALSE if configured as simple mode
|
|
*
|
|
* @note None
|
|
*
|
|
*****************************************************************************/
|
|
#define XAxiDma_HasSg(InstancePtr) ((InstancePtr)->HasSg) ? TRUE : FALSE
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
* This function enables interrupts specified by the Mask in specified
|
|
* direction, Interrupts that are not in the mask are not affected.
|
|
*
|
|
* @param InstancePtr is the driver instance we are working on
|
|
* @param Mask is the mask for the interrupts to be enabled
|
|
* @param Direction is DMA transfer direction, valid values are
|
|
* - XAXIDMA_DMA_TO_DEVICE.
|
|
* - XAXIDMA_DEVICE_TO_DMA.
|
|
* @return None
|
|
*
|
|
* @note None
|
|
*
|
|
*****************************************************************************/
|
|
#define XAxiDma_IntrEnable(InstancePtr, Mask, Direction) \
|
|
XAxiDma_WriteReg((InstancePtr)->RegBase + \
|
|
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET, \
|
|
(XAxiDma_ReadReg((InstancePtr)->RegBase + \
|
|
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET)) \
|
|
| (Mask & XAXIDMA_IRQ_ALL_MASK))
|
|
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
* This function gets the mask for the interrupts that are currently enabled
|
|
*
|
|
* @param InstancePtr is the driver instance we are working on
|
|
* @param Direction is DMA transfer direction, valid values are
|
|
* - XAXIDMA_DMA_TO_DEVICE.
|
|
* - XAXIDMA_DEVICE_TO_DMA.
|
|
*
|
|
* @return The bit mask for the interrupts that are currently enabled
|
|
*
|
|
* @note None
|
|
*
|
|
*****************************************************************************/
|
|
#define XAxiDma_IntrGetEnabled(InstancePtr, Direction) \
|
|
XAxiDma_ReadReg((InstancePtr)->RegBase + \
|
|
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET) &\
|
|
XAXIDMA_IRQ_ALL_MASK)
|
|
|
|
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
* This function disables interrupts specified by the Mask. Interrupts that
|
|
* are not in the mask are not affected.
|
|
*
|
|
* @param InstancePtr is the driver instance we are working on
|
|
* @param Mask is the mask for the interrupts to be disabled
|
|
* @param Direction is DMA transfer direction, valid values are
|
|
* - XAXIDMA_DMA_TO_DEVICE.
|
|
* - XAXIDMA_DEVICE_TO_DMA.
|
|
* @return None
|
|
*
|
|
* @note None
|
|
*
|
|
*****************************************************************************/
|
|
#define XAxiDma_IntrDisable(InstancePtr, Mask, Direction) \
|
|
XAxiDma_WriteReg((InstancePtr)->RegBase + \
|
|
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET, \
|
|
(XAxiDma_ReadReg((InstancePtr)->RegBase + \
|
|
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET)) \
|
|
& ~(Mask & XAXIDMA_IRQ_ALL_MASK))
|
|
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
* This function gets the interrupts that are asserted.
|
|
*
|
|
* @param InstancePtr is the driver instance we are working on
|
|
* @param Direction is DMA transfer direction, valid values are
|
|
* - XAXIDMA_DMA_TO_DEVICE.
|
|
* - XAXIDMA_DEVICE_TO_DMA.
|
|
*
|
|
* @return The bit mask for the interrupts asserted.
|
|
*
|
|
* @note None
|
|
*
|
|
*****************************************************************************/
|
|
#define XAxiDma_IntrGetIrq(InstancePtr, Direction) \
|
|
(XAxiDma_ReadReg((InstancePtr)->RegBase + \
|
|
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_SR_OFFSET) &\
|
|
XAXIDMA_IRQ_ALL_MASK)
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
* This function acknowledges the interrupts that are specified in Mask
|
|
*
|
|
* @param InstancePtr is the driver instance we are working on
|
|
* @param Mask is the mask for the interrupts to be acknowledge
|
|
* @param Direction is DMA transfer direction, valid values are
|
|
* - XAXIDMA_DMA_TO_DEVICE.
|
|
* - XAXIDMA_DEVICE_TO_DMA.
|
|
*
|
|
* @return None
|
|
*
|
|
* @note None.
|
|
*
|
|
*****************************************************************************/
|
|
#define XAxiDma_IntrAckIrq(InstancePtr, Mask, Direction) \
|
|
XAxiDma_WriteReg((InstancePtr)->RegBase + \
|
|
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_SR_OFFSET, \
|
|
(Mask) & XAXIDMA_IRQ_ALL_MASK)
|
|
|
|
|
|
|
|
/************************** Function Prototypes ******************************/
|
|
|
|
/*
|
|
* Initialization and control functions in xaxidma.c
|
|
*/
|
|
XAxiDma_Config *XAxiDma_LookupConfig(u32 DeviceId);
|
|
int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config);
|
|
void XAxiDma_Reset(XAxiDma * InstancePtr);
|
|
int XAxiDma_ResetIsDone(XAxiDma * InstancePtr);
|
|
int XAxiDma_Pause(XAxiDma * InstancePtr);
|
|
int XAxiDma_Resume(XAxiDma * InstancePtr);
|
|
u32 XAxiDma_Busy(XAxiDma *InstancePtr,int Direction);
|
|
int XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, u32 BuffAddr, u32 Length,
|
|
int Direction);
|
|
int XAxiDma_SelectKeyHole(XAxiDma *InstancePtr, int Direction, int Select);
|
|
int XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr, int Direction, int Select);
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* end of protection macro */
|