eec760a402
This patch updates the copy right to 2015. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
1010 lines
33 KiB
C
Executable file
1010 lines
33 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xiic_l.c
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*
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* This file contains low-level driver functions that can be used to access the
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* device in normal and dynamic controller mode. The user should refer to the
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* hardware device specification for more details of the device operation.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- --- ------- -----------------------------------------------
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* 1.01b jhl 05/13/02 First release
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* 1.01b jhl 10/14/02 Corrected bug in the receive function, the setup of the
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* interrupt status mask was not being done in the loop such
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* that a read would sometimes fail on the last byte because
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* the transmit error which should have been ignored was
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* being used. This would leave an extra byte in the FIFO
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* and the bus throttled such that the next operation would
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* also fail. Also updated the receive function to not
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* disable the device after the last byte until after the
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* bus transitions to not busy which is more consistent
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* with the expected behavior.
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* 1.01c ecm 12/05/02 new rev
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* 1.02a mta 03/09/06 Implemented Repeated Start in the Low Level Driver.
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* 1.03a mta 04/04/06 Implemented Dynamic IIC core routines.
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* 1.03a ecm 06/15/06 Fixed the hang in low_level_eeprom_test with -O0
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* Added polling loops for BNB to allow the slave to
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* respond correctly. Also added polling loop prior
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* to reset in _Recv.
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* 1.13a wgr 03/22/07 Converted to new coding style.
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* 1.13b ecm 11/29/07 added BB polling loops to the DynSend and DynRecv
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* routines to handle the race condition with BNB in IISR.
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* 2.00a sdm 10/22/09 Converted all register accesses to 32 bit access.
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* Updated to use the HAL APIs/macros.
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* Some of the macros have been renamed to remove _m from
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* the name and Some of the macros have been renamed to be
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* consistent, see the xiic_i.h and xiic_l.h files for
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* further information.
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* 2.02a sdm 10/08/10 Updated to disable the device at the end of the transfer,
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* only when addressed as slave in XIic_Send for CR565373.
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* 2.04a sdm 07/22/11 Removed a compiler warning by adding parenthesis around &
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* at line 479.
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* 2.08a adk 29/07/13 In Low level driver In repeated start condition the
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* Direction of Tx bit must be disabled in Receive
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* condition It Fixes the CR:685759 Changes are done
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* in the function XIic_Recv.
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* </pre>
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*
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****************************************************************************/
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/***************************** Include Files *******************************/
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xiic_l.h"
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/************************** Constant Definitions ***************************/
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/**************************** Type Definitions *****************************/
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/***************** Macros (Inline Functions) Definitions *******************/
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/************************** Function Prototypes ****************************/
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static unsigned RecvData(u32 BaseAddress, u8 *BufferPtr,
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unsigned ByteCount, u8 Option);
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static unsigned SendData(u32 BaseAddress, u8 *BufferPtr,
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unsigned ByteCount, u8 Option);
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static unsigned DynRecvData(u32 BaseAddress, u8 *BufferPtr, u8 ByteCount);
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static unsigned DynSendData(u32 BaseAddress, u8 *BufferPtr,
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u8 ByteCount, u8 Option);
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/************************** Variable Definitions **************************/
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/****************************************************************************/
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/**
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* Receive data as a master on the IIC bus. This function receives the data
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* using polled I/O and blocks until the data has been received. It only
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* supports 7 bit addressing mode of operation. The user is responsible for
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* ensuring the bus is not busy if multiple masters are present on the bus.
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*
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* @param BaseAddress contains the base address of the IIC device.
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* @param Address contains the 7 bit IIC address of the device to send the
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* specified data to.
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* @param BufferPtr points to the data to be sent.
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* @param ByteCount is the number of bytes to be sent.
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* @param Option indicates whether to hold or free the bus after reception
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* of data, XIIC_STOP = end with STOP condition,
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* XIIC_REPEATED_START = don't end with STOP condition.
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*
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* @return The number of bytes received.
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*
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* @note None.
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*
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******************************************************************************/
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unsigned XIic_Recv(u32 BaseAddress, u8 Address,
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u8 *BufferPtr, unsigned ByteCount, u8 Option)
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{
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u32 CntlReg;
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unsigned RemainingByteCount;
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volatile u32 StatusReg;
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/* Tx error is enabled incase the address (7 or 10) has no device to
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* answer with Ack. When only one byte of data, must set NO ACK before
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* address goes out therefore Tx error must not be enabled as it will go
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* off immediately and the Rx full interrupt will be checked. If full,
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* then the one byte was received and the Tx error will be disabled
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* without sending an error callback msg
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*/
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XIic_ClearIisr(BaseAddress,
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XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK |
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XIIC_INTR_ARB_LOST_MASK);
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/* Set receive FIFO occupancy depth for 1 byte (zero based) */
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XIic_WriteReg(BaseAddress, XIIC_RFD_REG_OFFSET, 0);
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/* Check to see if already Master on the Bus.
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* If Repeated Start bit is not set send Start bit by setting MSMS bit
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* else Send the address
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*/
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CntlReg = XIic_ReadReg(BaseAddress, XIIC_CR_REG_OFFSET);
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if ((CntlReg & XIIC_CR_REPEATED_START_MASK) == 0) {
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/* 7 bit slave address, send the address for a read operation
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* and set the state to indicate the address has been sent
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*/
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XIic_Send7BitAddress(BaseAddress, Address,
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XIIC_READ_OPERATION);
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/* MSMS gets set after putting data in FIFO. Start the master
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* receive operation by setting CR Bits MSMS to Master, if the
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* buffer is only one byte, then it should not be acknowledged
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* to indicate the end of data
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*/
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CntlReg = XIIC_CR_MSMS_MASK | XIIC_CR_ENABLE_DEVICE_MASK;
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if (ByteCount == 1) {
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CntlReg |= XIIC_CR_NO_ACK_MASK;
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}
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/* Write out the control register to start receiving data and
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* call the function to receive each byte into the buffer
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*/
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XIic_WriteReg(BaseAddress, XIIC_CR_REG_OFFSET, CntlReg);
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/* Clear the latched interrupt status for the bus not busy bit
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* which must be done while the bus is busy
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*/
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StatusReg = XIic_ReadReg(BaseAddress, XIIC_SR_REG_OFFSET);
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while ((StatusReg & XIIC_SR_BUS_BUSY_MASK) == 0) {
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StatusReg = XIic_ReadReg(BaseAddress,
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XIIC_SR_REG_OFFSET);
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}
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XIic_ClearIisr(BaseAddress, XIIC_INTR_BNB_MASK);
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} else {
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/* Before writing 7bit slave address the Direction of Tx bit
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* must be disabled
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*/
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CntlReg &= ~XIIC_CR_DIR_IS_TX_MASK;
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XIic_WriteReg(BaseAddress, XIIC_CR_REG_OFFSET, CntlReg);
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/* Already owns the Bus indicating that its a Repeated Start
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* call. 7 bit slave address, send the address for a read
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* operation and set the state to indicate the address has been
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* sent
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*/
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XIic_Send7BitAddress(BaseAddress, Address,
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XIIC_READ_OPERATION);
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}
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/* Try to receive the data from the IIC bus */
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RemainingByteCount = RecvData(BaseAddress, BufferPtr,
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ByteCount, Option);
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CntlReg = XIic_ReadReg(BaseAddress, XIIC_CR_REG_OFFSET);
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if ((CntlReg & XIIC_CR_REPEATED_START_MASK) == 0) {
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/* The receive is complete, disable the IIC device if the Option
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* is to release the Bus after Reception of data and return the
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* number of bytes that was received
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*/
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XIic_WriteReg(BaseAddress, XIIC_CR_REG_OFFSET, 0);
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}
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/* Return the number of bytes that was received */
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return ByteCount - RemainingByteCount;
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}
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/******************************************************************************
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*
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* Receive the specified data from the device that has been previously addressed
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* on the IIC bus. This function assumes that the 7 bit address has been sent
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* and it should wait for the transmit of the address to complete.
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*
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* @param BaseAddress contains the base address of the IIC device.
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* @param BufferPtr points to the buffer to hold the data that is
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* received.
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* @param ByteCount is the number of bytes to be received.
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* @param Option indicates whether to hold or free the bus after reception
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* of data, XIIC_STOP = end with STOP condition,
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* XIIC_REPEATED_START = don't end with STOP condition.
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*
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* @return The number of bytes remaining to be received.
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*
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* @note
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*
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* This function does not take advantage of the receive FIFO because it is
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* designed for minimal code space and complexity. It contains loops that
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* that could cause the function not to return if the hardware is not working.
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*
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* This function assumes that the calling function will disable the IIC device
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* after this function returns.
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*
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******************************************************************************/
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static unsigned RecvData(u32 BaseAddress, u8 *BufferPtr,
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unsigned ByteCount, u8 Option)
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{
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u32 CntlReg;
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u32 IntrStatusMask;
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u32 IntrStatus;
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/* Attempt to receive the specified number of bytes on the IIC bus */
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while (ByteCount > 0) {
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/* Setup the mask to use for checking errors because when
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* receiving one byte OR the last byte of a multibyte message an
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* error naturally occurs when the no ack is done to tell the
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* slave the last byte
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*/
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if (ByteCount == 1) {
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IntrStatusMask =
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XIIC_INTR_ARB_LOST_MASK | XIIC_INTR_BNB_MASK;
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} else {
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IntrStatusMask =
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XIIC_INTR_ARB_LOST_MASK |
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XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_BNB_MASK;
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}
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/* Wait for the previous transmit and the 1st receive to
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* complete by checking the interrupt status register of the
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* IPIF
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*/
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while (1) {
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IntrStatus = XIic_ReadIisr(BaseAddress);
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if (IntrStatus & XIIC_INTR_RX_FULL_MASK) {
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break;
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}
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/* Check the transmit error after the receive full
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* because when sending only one byte transmit error
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* will occur because of the no ack to indicate the end
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* of the data
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*/
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if (IntrStatus & IntrStatusMask) {
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return ByteCount;
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}
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}
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CntlReg = XIic_ReadReg(BaseAddress, XIIC_CR_REG_OFFSET);
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/* Special conditions exist for the last two bytes so check for
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* them. Note that the control register must be setup for these
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* conditions before the data byte which was already received is
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* read from the receive FIFO (while the bus is throttled
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*/
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if (ByteCount == 1) {
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if (Option == XIIC_STOP) {
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/* If the Option is to release the bus after the
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* last data byte, it has already been read and
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* no ack has been done, so clear MSMS while
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* leaving the device enabled so it can get off
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* the IIC bus appropriately with a stop
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*/
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XIic_WriteReg(BaseAddress, XIIC_CR_REG_OFFSET,
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XIIC_CR_ENABLE_DEVICE_MASK);
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}
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}
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/* Before the last byte is received, set NOACK to tell the slave
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* IIC device that it is the end, this must be done before
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* reading the byte from the FIFO
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*/
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if (ByteCount == 2) {
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/* Write control reg with NO ACK allowing last byte to
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* have the No ack set to indicate to slave last byte
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* read
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*/
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XIic_WriteReg(BaseAddress, XIIC_CR_REG_OFFSET,
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CntlReg | XIIC_CR_NO_ACK_MASK);
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}
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/* Read in data from the FIFO and unthrottle the bus such that
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* the next byte is read from the IIC bus
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*/
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*BufferPtr++ = (u8) XIic_ReadReg(BaseAddress,
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XIIC_DRR_REG_OFFSET);
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if ((ByteCount == 1) && (Option == XIIC_REPEATED_START)) {
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/* RSTA bit should be set only when the FIFO is
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* completely Empty.
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*/
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XIic_WriteReg(BaseAddress, XIIC_CR_REG_OFFSET,
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XIIC_CR_ENABLE_DEVICE_MASK | XIIC_CR_MSMS_MASK
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| XIIC_CR_REPEATED_START_MASK);
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}
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/* Clear the latched interrupt status so that it will be updated
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* with the new state when it changes, this must be done after
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* the receive register is read
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*/
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XIic_ClearIisr(BaseAddress, XIIC_INTR_RX_FULL_MASK |
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XIIC_INTR_TX_ERROR_MASK |
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XIIC_INTR_ARB_LOST_MASK);
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ByteCount--;
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}
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if (Option == XIIC_STOP) {
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/* If the Option is to release the bus after Reception of data,
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* wait for the bus to transition to not busy before returning,
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* the IIC device cannot be disabled until this occurs. It
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* should transition as the MSMS bit of the control register was
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* cleared before the last byte was read from the FIFO
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*/
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while (1) {
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if (XIic_ReadIisr(BaseAddress) & XIIC_INTR_BNB_MASK) {
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break;
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}
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}
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}
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return ByteCount;
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}
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/****************************************************************************/
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/**
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* Send data as a master on the IIC bus. This function sends the data
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* using polled I/O and blocks until the data has been sent. It only supports
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* 7 bit addressing mode of operation. The user is responsible for ensuring
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* the bus is not busy if multiple masters are present on the bus.
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*
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* @param BaseAddress contains the base address of the IIC device.
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* @param Address contains the 7 bit IIC address of the device to send the
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* specified data to.
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* @param BufferPtr points to the data to be sent.
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* @param ByteCount is the number of bytes to be sent.
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* @param Option indicates whether to hold or free the bus after
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* transmitting the data.
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*
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* @return The number of bytes sent.
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*
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* @note None.
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*
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******************************************************************************/
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unsigned XIic_Send(u32 BaseAddress, u8 Address,
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u8 *BufferPtr, unsigned ByteCount, u8 Option)
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{
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unsigned RemainingByteCount;
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u32 ControlReg;
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volatile u32 StatusReg;
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/* Check to see if already Master on the Bus.
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* If Repeated Start bit is not set send Start bit by setting
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* MSMS bit else Send the address.
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*/
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ControlReg = XIic_ReadReg(BaseAddress, XIIC_CR_REG_OFFSET);
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if ((ControlReg & XIIC_CR_REPEATED_START_MASK) == 0) {
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/*
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* Put the address into the FIFO to be sent and indicate
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* that the operation to be performed on the bus is a
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* write operation
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*/
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XIic_Send7BitAddress(BaseAddress, Address,
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XIIC_WRITE_OPERATION);
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/* Clear the latched interrupt status so that it will
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* be updated with the new state when it changes, this
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* must be done after the address is put in the FIFO
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*/
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XIic_ClearIisr(BaseAddress, XIIC_INTR_TX_EMPTY_MASK |
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XIIC_INTR_TX_ERROR_MASK |
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XIIC_INTR_ARB_LOST_MASK);
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/*
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* MSMS must be set after putting data into transmit FIFO,
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* indicate the direction is transmit, this device is master
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* and enable the IIC device
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*/
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XIic_WriteReg(BaseAddress, XIIC_CR_REG_OFFSET,
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XIIC_CR_MSMS_MASK | XIIC_CR_DIR_IS_TX_MASK |
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XIIC_CR_ENABLE_DEVICE_MASK);
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/*
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* Clear the latched interrupt
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* status for the bus not busy bit which must be done while
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* the bus is busy
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*/
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StatusReg = XIic_ReadReg(BaseAddress, XIIC_SR_REG_OFFSET);
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while ((StatusReg & XIIC_SR_BUS_BUSY_MASK) == 0) {
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StatusReg = XIic_ReadReg(BaseAddress,
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XIIC_SR_REG_OFFSET);
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}
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XIic_ClearIisr(BaseAddress, XIIC_INTR_BNB_MASK);
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}
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else {
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/*
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* Already owns the Bus indicating that its a Repeated Start
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* call. 7 bit slave address, send the address for a write
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* operation and set the state to indicate the address has
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* been sent.
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*/
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XIic_Send7BitAddress(BaseAddress, Address,
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XIIC_WRITE_OPERATION);
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}
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/* Send the specified data to the device on the IIC bus specified by the
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* the address
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*/
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RemainingByteCount = SendData(BaseAddress, BufferPtr,
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ByteCount, Option);
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ControlReg = XIic_ReadReg(BaseAddress, XIIC_CR_REG_OFFSET);
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if ((ControlReg & XIIC_CR_REPEATED_START_MASK) == 0) {
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/*
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* The Transmission is completed, disable the IIC device if
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* the Option is to release the Bus after transmission of data
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* and return the number of bytes that was received. Only wait
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* if master, if addressed as slave just reset to release
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* the bus.
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*/
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if ((ControlReg & XIIC_CR_MSMS_MASK) != 0) {
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XIic_WriteReg(BaseAddress, XIIC_CR_REG_OFFSET,
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(ControlReg & ~XIIC_CR_MSMS_MASK));
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StatusReg = XIic_ReadReg(BaseAddress,
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XIIC_SR_REG_OFFSET);
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while ((StatusReg & XIIC_SR_BUS_BUSY_MASK) != 0) {
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StatusReg = XIic_ReadReg(BaseAddress,
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XIIC_SR_REG_OFFSET);
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}
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}
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|
|
if ((XIic_ReadReg(BaseAddress, XIIC_SR_REG_OFFSET) &
|
|
XIIC_SR_ADDR_AS_SLAVE_MASK) != 0) {
|
|
XIic_WriteReg(BaseAddress, XIIC_CR_REG_OFFSET, 0);
|
|
}
|
|
}
|
|
|
|
return ByteCount - RemainingByteCount;
|
|
}
|
|
|
|
/******************************************************************************
|
|
*
|
|
* Send the specified buffer to the device that has been previously addressed
|
|
* on the IIC bus. This function assumes that the 7 bit address has been sent
|
|
* and it should wait for the transmit of the address to complete.
|
|
*
|
|
* @param BaseAddress contains the base address of the IIC device.
|
|
* @param BufferPtr points to the data to be sent.
|
|
* @param ByteCount is the number of bytes to be sent.
|
|
* @param Option indicates whether to hold or free the bus after
|
|
* transmitting the data.
|
|
*
|
|
* @return The number of bytes remaining to be sent.
|
|
*
|
|
* @note
|
|
*
|
|
* This function does not take advantage of the transmit FIFO because it is
|
|
* designed for minimal code space and complexity. It contains loops that
|
|
* that could cause the function not to return if the hardware is not working.
|
|
*
|
|
******************************************************************************/
|
|
static unsigned SendData(u32 BaseAddress, u8 *BufferPtr,
|
|
unsigned ByteCount, u8 Option)
|
|
{
|
|
u32 IntrStatus;
|
|
|
|
/*
|
|
* Send the specified number of bytes in the specified buffer by polling
|
|
* the device registers and blocking until complete
|
|
*/
|
|
while (ByteCount > 0) {
|
|
/*
|
|
* Wait for the transmit to be empty before sending any more
|
|
* data by polling the interrupt status register
|
|
*/
|
|
while (1) {
|
|
IntrStatus = XIic_ReadIisr(BaseAddress);
|
|
|
|
if (IntrStatus & (XIIC_INTR_TX_ERROR_MASK |
|
|
XIIC_INTR_ARB_LOST_MASK |
|
|
XIIC_INTR_BNB_MASK)) {
|
|
return ByteCount;
|
|
}
|
|
|
|
if (IntrStatus & XIIC_INTR_TX_EMPTY_MASK) {
|
|
break;
|
|
}
|
|
}
|
|
/* If there is more than one byte to send then put the
|
|
* next byte to send into the transmit FIFO
|
|
*/
|
|
if (ByteCount > 1) {
|
|
XIic_WriteReg(BaseAddress, XIIC_DTR_REG_OFFSET,
|
|
*BufferPtr++);
|
|
}
|
|
else {
|
|
if (Option == XIIC_STOP) {
|
|
/*
|
|
* If the Option is to release the bus after
|
|
* the last data byte, Set the stop Option
|
|
* before sending the last byte of data so
|
|
* that the stop Option will be generated
|
|
* immediately following the data. This is
|
|
* done by clearing the MSMS bit in the
|
|
* control register.
|
|
*/
|
|
XIic_WriteReg(BaseAddress, XIIC_CR_REG_OFFSET,
|
|
XIIC_CR_ENABLE_DEVICE_MASK |
|
|
XIIC_CR_DIR_IS_TX_MASK);
|
|
}
|
|
|
|
/*
|
|
* Put the last byte to send in the transmit FIFO
|
|
*/
|
|
XIic_WriteReg(BaseAddress, XIIC_DTR_REG_OFFSET,
|
|
*BufferPtr++);
|
|
|
|
if (Option == XIIC_REPEATED_START) {
|
|
XIic_ClearIisr(BaseAddress,
|
|
XIIC_INTR_TX_EMPTY_MASK);
|
|
/*
|
|
* Wait for the transmit to be empty before
|
|
* setting RSTA bit.
|
|
*/
|
|
while (1) {
|
|
IntrStatus =
|
|
XIic_ReadIisr(BaseAddress);
|
|
if (IntrStatus &
|
|
XIIC_INTR_TX_EMPTY_MASK) {
|
|
/*
|
|
* RSTA bit should be set only
|
|
* when the FIFO is completely
|
|
* Empty.
|
|
*/
|
|
XIic_WriteReg(BaseAddress,
|
|
XIIC_CR_REG_OFFSET,
|
|
XIIC_CR_REPEATED_START_MASK |
|
|
XIIC_CR_ENABLE_DEVICE_MASK |
|
|
XIIC_CR_DIR_IS_TX_MASK |
|
|
XIIC_CR_MSMS_MASK);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Clear the latched interrupt status register and this must be
|
|
* done after the transmit FIFO has been written to or it won't
|
|
* clear
|
|
*/
|
|
XIic_ClearIisr(BaseAddress, XIIC_INTR_TX_EMPTY_MASK);
|
|
|
|
/*
|
|
* Update the byte count to reflect the byte sent and clear
|
|
* the latched interrupt status so it will be updated for the
|
|
* new state
|
|
*/
|
|
ByteCount--;
|
|
}
|
|
|
|
if (Option == XIIC_STOP) {
|
|
/*
|
|
* If the Option is to release the bus after transmission of
|
|
* data, Wait for the bus to transition to not busy before
|
|
* returning, the IIC device cannot be disabled until this
|
|
* occurs. Note that this is different from a receive operation
|
|
* because the stop Option causes the bus to go not busy.
|
|
*/
|
|
while (1) {
|
|
if (XIic_ReadIisr(BaseAddress) &
|
|
XIIC_INTR_BNB_MASK) {
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
return ByteCount;
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
* Receive data as a master on the IIC bus. This function receives the data
|
|
* using polled I/O and blocks until the data has been received. It only
|
|
* supports 7 bit addressing. The user is responsible for ensuring the bus is
|
|
* not busy if multiple masters are present on the bus.
|
|
*
|
|
* @param BaseAddress contains the base address of the IIC Device.
|
|
* @param Address contains the 7 bit IIC Device address of the device to
|
|
* send the specified data to.
|
|
* @param BufferPtr points to the data to be sent.
|
|
* @param ByteCount is the number of bytes to be sent. This value can't be
|
|
* greater than 255 and needs to be greater than 0.
|
|
*
|
|
* @return The number of bytes received.
|
|
*
|
|
* @note Upon entry to this function, the IIC interface needs to be
|
|
* already enabled in the CR register.
|
|
*
|
|
******************************************************************************/
|
|
unsigned XIic_DynRecv(u32 BaseAddress, u8 Address, u8 *BufferPtr, u8 ByteCount)
|
|
{
|
|
unsigned RemainingByteCount;
|
|
u32 StatusRegister;
|
|
|
|
/*
|
|
* Clear the latched interrupt status so that it will be updated with
|
|
* the new state when it changes.
|
|
*/
|
|
XIic_ClearIisr(BaseAddress, XIIC_INTR_TX_EMPTY_MASK |
|
|
XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_ARB_LOST_MASK);
|
|
|
|
/*
|
|
* Send the 7 bit slave address for a read operation and set the state
|
|
* to indicate the address has been sent. Upon writing the address, a
|
|
* start condition is initiated. MSMS is automatically set to master
|
|
* when the address is written to the Fifo. If MSMS was already set,
|
|
* then a re-start is sent prior to the address.
|
|
*/
|
|
XIic_DynSend7BitAddress(BaseAddress, Address, XIIC_READ_OPERATION);
|
|
|
|
/*
|
|
* Wait for the bus to go busy.
|
|
*/
|
|
StatusRegister = XIic_ReadReg(BaseAddress, XIIC_SR_REG_OFFSET);
|
|
|
|
while (( StatusRegister & XIIC_SR_BUS_BUSY_MASK)
|
|
!= XIIC_SR_BUS_BUSY_MASK) {
|
|
StatusRegister = XIic_ReadReg(BaseAddress,
|
|
XIIC_SR_REG_OFFSET);
|
|
}
|
|
|
|
/*
|
|
* Clear the latched interrupt status for the bus not busy bit which
|
|
* must be done while the bus is busy.
|
|
*/
|
|
XIic_ClearIisr(BaseAddress, XIIC_INTR_BNB_MASK);
|
|
|
|
/*
|
|
* Write to the Tx Fifo the dynamic stop control bit with the number of
|
|
* bytes that are to be read over the IIC interface from the presently
|
|
* addressed device.
|
|
*/
|
|
XIic_DynSendStop(BaseAddress, ByteCount);
|
|
|
|
/*
|
|
* Receive the data from the IIC bus.
|
|
*/
|
|
RemainingByteCount = DynRecvData(BaseAddress, BufferPtr, ByteCount);
|
|
|
|
/*
|
|
* The receive is complete. Return the number of bytes that were
|
|
* received.
|
|
*/
|
|
return ByteCount - RemainingByteCount;
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
* Receive the specified data from the device that has been previously addressed
|
|
* on the IIC bus. This function assumes the following:
|
|
* - The Rx Fifo occupancy depth has been set to its max.
|
|
* - Upon entry, the Rx Fifo is empty.
|
|
* - The 7 bit address has been sent.
|
|
* - The dynamic stop and number of bytes to receive has been written to Tx
|
|
* Fifo.
|
|
*
|
|
* @param BaseAddress contains the base address of the IIC Device.
|
|
* @param BufferPtr points to the buffer to hold the data that is
|
|
* received.
|
|
* @param ByteCount is the number of bytes to be received. The range of
|
|
* this value is greater than 0 and not higher than 255.
|
|
*
|
|
* @return The number of bytes remaining to be received.
|
|
*
|
|
* @note This function contains loops that could cause the function not
|
|
* to return if the hardware is not working.
|
|
*
|
|
******************************************************************************/
|
|
static unsigned DynRecvData(u32 BaseAddress, u8 *BufferPtr, u8 ByteCount)
|
|
{
|
|
u32 StatusReg;
|
|
u32 IntrStatus;
|
|
u32 IntrStatusMask;
|
|
|
|
while (ByteCount > 0) {
|
|
|
|
/*
|
|
* Setup the mask to use for checking errors because when
|
|
* receiving one byte OR the last byte of a multibyte message
|
|
* an error naturally occurs when the no ack is done to tell
|
|
* the slave the last byte.
|
|
*/
|
|
if (ByteCount == 1) {
|
|
IntrStatusMask =
|
|
XIIC_INTR_ARB_LOST_MASK | XIIC_INTR_BNB_MASK;
|
|
} else {
|
|
IntrStatusMask =
|
|
XIIC_INTR_ARB_LOST_MASK |
|
|
XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_BNB_MASK;
|
|
}
|
|
|
|
/*
|
|
* Wait for a byte to show up in the Rx Fifo.
|
|
*/
|
|
while (1) {
|
|
IntrStatus = XIic_ReadIisr(BaseAddress);
|
|
StatusReg = XIic_ReadReg(BaseAddress,
|
|
XIIC_SR_REG_OFFSET);
|
|
|
|
if ((StatusReg & XIIC_SR_RX_FIFO_EMPTY_MASK) !=
|
|
XIIC_SR_RX_FIFO_EMPTY_MASK) {
|
|
break;
|
|
}
|
|
/*
|
|
* Check the transmit error after the receive full
|
|
* because when sending only one byte transmit error
|
|
* will occur because of the no ack to indicate the end
|
|
* of the data.
|
|
*/
|
|
if (IntrStatus & IntrStatusMask) {
|
|
return ByteCount;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Read in byte from the Rx Fifo. If the Fifo reached the
|
|
* programmed occupancy depth as programmed in the Rx occupancy
|
|
* reg, this read access will un throttle the bus such that
|
|
* the next byte is read from the IIC bus.
|
|
*/
|
|
*BufferPtr++ = XIic_ReadReg(BaseAddress, XIIC_DRR_REG_OFFSET);
|
|
ByteCount--;
|
|
}
|
|
|
|
return ByteCount;
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
* Send data as a master on the IIC bus. This function sends the data using
|
|
* polled I/O and blocks until the data has been sent. It only supports 7 bit
|
|
* addressing. The user is responsible for ensuring the bus is not busy if
|
|
* multiple masters are present on the bus.
|
|
*
|
|
* @param BaseAddress contains the base address of the IIC Device.
|
|
* @param Address contains the 7 bit IIC address of the device to send the
|
|
* specified data to.
|
|
* @param BufferPtr points to the data to be sent.
|
|
* @param ByteCount is the number of bytes to be sent.
|
|
* @param Option: XIIC_STOP = end with STOP condition,
|
|
* XIIC_REPEATED_START = don't end with STOP condition.
|
|
*
|
|
* @return The number of bytes sent.
|
|
*
|
|
* @note None.
|
|
*
|
|
******************************************************************************/
|
|
unsigned XIic_DynSend(u32 BaseAddress, u16 Address, u8 *BufferPtr,
|
|
u8 ByteCount, u8 Option)
|
|
{
|
|
unsigned RemainingByteCount;
|
|
u32 StatusRegister;
|
|
|
|
/*
|
|
* Clear the latched interrupt status so that it will be updated with
|
|
* the new state when it changes, this must be done after the address
|
|
* is put in the FIFO
|
|
*/
|
|
XIic_ClearIisr(BaseAddress, XIIC_INTR_TX_EMPTY_MASK |
|
|
XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_ARB_LOST_MASK);
|
|
|
|
/*
|
|
* Put the address into the Fifo to be sent and indicate that the
|
|
* operation to be performed on the bus is a write operation. Upon
|
|
* writing the address, a start condition is initiated. MSMS is
|
|
* automatically set to master when the address is written to the Fifo.
|
|
* If MSMS was already set, then a re-start is sent prior to the
|
|
* address.
|
|
*/
|
|
if(!(Address & XIIC_TX_DYN_STOP_MASK)) {
|
|
|
|
XIic_DynSend7BitAddress(BaseAddress, Address,
|
|
XIIC_WRITE_OPERATION);
|
|
} else {
|
|
XIic_DynSendStartStopAddress(BaseAddress, Address,
|
|
XIIC_WRITE_OPERATION);
|
|
}
|
|
|
|
/*
|
|
* Wait for the bus to go busy.
|
|
*/
|
|
StatusRegister = XIic_ReadReg(BaseAddress, XIIC_SR_REG_OFFSET);
|
|
|
|
while (( StatusRegister & XIIC_SR_BUS_BUSY_MASK) !=
|
|
XIIC_SR_BUS_BUSY_MASK) {
|
|
StatusRegister = XIic_ReadReg(BaseAddress,
|
|
XIIC_SR_REG_OFFSET);
|
|
}
|
|
|
|
/*
|
|
* Clear the latched interrupt status for the bus not busy bit which
|
|
* must be done while the bus is busy.
|
|
*/
|
|
XIic_ClearIisr(BaseAddress, XIIC_INTR_BNB_MASK);
|
|
|
|
/*
|
|
* Send the specified data to the device on the IIC bus specified by the
|
|
* the address.
|
|
*/
|
|
RemainingByteCount = DynSendData(BaseAddress, BufferPtr, ByteCount,
|
|
Option);
|
|
|
|
/*
|
|
* The send is complete return the number of bytes that was sent.
|
|
*/
|
|
return ByteCount - RemainingByteCount;
|
|
}
|
|
|
|
/******************************************************************************
|
|
*
|
|
* Send the specified buffer to the device that has been previously addressed
|
|
* on the IIC bus. This function assumes that the 7 bit address has been sent.
|
|
*
|
|
* @param BaseAddress contains the base address of the IIC Device.
|
|
* @param BufferPtr points to the data to be sent.
|
|
* @param ByteCount is the number of bytes to be sent.
|
|
* @param Option: XIIC_STOP = end with STOP condition, XIIC_REPEATED_START
|
|
* = don't end with STOP condition.
|
|
*
|
|
* @return The number of bytes remaining to be sent.
|
|
*
|
|
* @note This function does not take advantage of the transmit Fifo
|
|
* because it is designed for minimal code space and complexity.
|
|
*
|
|
******************************************************************************/
|
|
static unsigned DynSendData(u32 BaseAddress, u8 *BufferPtr,
|
|
u8 ByteCount, u8 Option)
|
|
{
|
|
u32 IntrStatus;
|
|
|
|
while (ByteCount > 0) {
|
|
/*
|
|
* Wait for the transmit to be empty before sending any more
|
|
* data by polling the interrupt status register.
|
|
*/
|
|
while (1) {
|
|
IntrStatus = XIic_ReadIisr(BaseAddress);
|
|
if (IntrStatus & (XIIC_INTR_TX_ERROR_MASK |
|
|
XIIC_INTR_ARB_LOST_MASK |
|
|
XIIC_INTR_BNB_MASK)) {
|
|
/*
|
|
* Error condition (NACK or ARB Lost or BNB
|
|
* Error Has occurred. Clear the Control
|
|
* register to send a STOP condition on the Bus
|
|
* and return the number of bytes still to
|
|
* transmit.
|
|
*/
|
|
XIic_WriteReg(BaseAddress, XIIC_CR_REG_OFFSET,
|
|
0x03);
|
|
XIic_WriteReg(BaseAddress, XIIC_CR_REG_OFFSET,
|
|
0x01);
|
|
|
|
return ByteCount;
|
|
}
|
|
|
|
/*
|
|
* Check for the transmit Fifo to become Empty.
|
|
*/
|
|
if (IntrStatus & XIIC_INTR_TX_EMPTY_MASK) {
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Send data to Tx Fifo. If a stop condition is specified and
|
|
* the last byte is being sent, then set the dynamic stop bit.
|
|
*/
|
|
if ((ByteCount == 1) && (Option == XIIC_STOP)) {
|
|
/*
|
|
* The MSMS will be cleared automatically upon setting
|
|
* dynamic stop.
|
|
*/
|
|
XIic_WriteReg(BaseAddress, XIIC_DTR_REG_OFFSET,
|
|
XIIC_TX_DYN_STOP_MASK | *BufferPtr++);
|
|
} else {
|
|
XIic_WriteReg(BaseAddress, XIIC_DTR_REG_OFFSET,
|
|
*BufferPtr++);
|
|
}
|
|
|
|
/*
|
|
* Update the byte count to reflect the byte sent.
|
|
*/
|
|
ByteCount--;
|
|
}
|
|
|
|
if (Option == XIIC_STOP) {
|
|
/*
|
|
* If the Option is to release the bus after transmission of
|
|
* data, Wait for the bus to transition to not busy before
|
|
* returning, the IIC device cannot be disabled until this
|
|
* occurs.
|
|
*/
|
|
while (1) {
|
|
if (XIic_ReadIisr(BaseAddress) & XIIC_INTR_BNB_MASK) {
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
return ByteCount;
|
|
}
|
|
|
|
/******************************************************************************
|
|
*
|
|
* Initialize the IIC core for Dynamic Functionality.
|
|
*
|
|
* @param BaseAddress contains the base address of the IIC Device.
|
|
*
|
|
* @return XST_SUCCESS if Successful else XST_FAILURE.
|
|
*
|
|
* @note None.
|
|
*
|
|
******************************************************************************/
|
|
int XIic_DynInit(u32 BaseAddress)
|
|
{
|
|
u32 Status;
|
|
|
|
/*
|
|
* Reset IIC Core.
|
|
*/
|
|
XIic_WriteReg(BaseAddress, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
|
|
|
|
/*
|
|
* Set receive Fifo depth to maximum (zero based).
|
|
*/
|
|
XIic_WriteReg(BaseAddress, XIIC_RFD_REG_OFFSET,
|
|
IIC_RX_FIFO_DEPTH - 1);
|
|
|
|
/*
|
|
* Reset Tx Fifo.
|
|
*/
|
|
XIic_WriteReg(BaseAddress, XIIC_CR_REG_OFFSET,
|
|
XIIC_CR_TX_FIFO_RESET_MASK);
|
|
|
|
/*
|
|
* Enable IIC Device, remove Tx Fifo reset & disable general call.
|
|
*/
|
|
XIic_WriteReg(BaseAddress, XIIC_CR_REG_OFFSET,
|
|
XIIC_CR_ENABLE_DEVICE_MASK);
|
|
|
|
/*
|
|
* Read status register and verify IIC Device is in initial state. Only
|
|
* the Tx Fifo and Rx Fifo empty bits should be set.
|
|
*/
|
|
Status = XIic_ReadReg(BaseAddress, XIIC_SR_REG_OFFSET);
|
|
if(Status == (XIIC_SR_RX_FIFO_EMPTY_MASK |
|
|
XIIC_SR_TX_FIFO_EMPTY_MASK)) {
|
|
return XST_SUCCESS;
|
|
}
|
|
|
|
return XST_FAILURE;
|
|
}
|