2a550bf65e
This patch updates the doxygen for the drivers trafgen,ttcps,uartlite,uartns550,uartps to include .h files in the listof files provided in the index.html file. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
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8.7 KiB
HTML
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124 lines
8.7 KiB
HTML
Executable file
<html>
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<meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
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<title>
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Xilinx Driver trafgen v3_2: trafgen v3_2
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</title>
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<link href="doxygen_kalyanidocs/doc/css/driver_api_doxygen.css" rel="stylesheet" type="text/css">
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</head>
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<h3 class="PageHeader">Xilinx Processor IP Library</h3>
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<hl>Software Drivers</hl>
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<hr class="whs1">
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<!-- Generated by Doxygen 1.6.1 -->
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<div class="navigation" id="top">
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<div class="tabs">
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<ul>
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<li class="current"><a href="index.html"><span>Main Page</span></a></li>
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<li><a href="annotated.html"><span>Classes</span></a></li>
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<li><a href="files.html"><span>Files</span></a></li>
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</ul>
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</div>
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</div>
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<div class="contents">
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<h1>trafgen v3_2</h1><p>This file contains the implementation of the AXI Traffic Generator driver. User documentation for the driver functions is contained in this file in the form of comment blocks at the front of each function.</p>
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<p>The AXI Traffic Generator IP is designed to generate AXI4 traffic which can be used to stress different modules/interconnect connected in the system. Different configurable options allow the user to generate a wide variety of traffic based on their requirements. The core is broadly separated into a master and slave block, each of which contains the write block and read block. Other support features are provided by the Control registers and Internal RAMs.</p>
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<p>The commands to be issued by the AXI traffic generator are loaded in a 128-bit wide, 512 deep command RAM through AXI Slave interface. After the core is enabled, control logic issues the write/read commands based on the command settings programmed. The core updates the Status registers and asserts interrupts on the completion of issuing programmed commands.</p>
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<p>The Axi Traffic Genrator has five different modes:</p>
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<ul>
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<li>Advanced Mode: Advanced Mode allows full control over the traffic genration Control registers are provided to you to program the core to genrate different AXI4 transactions.</li>
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</ul>
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<ul>
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<li>Basic Mode: Basic Mode allows basic AXI4 traffic genration with less resource overhead.</li>
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</ul>
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<ul>
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<li>Static Mode: Static Mode allows you to genrate a simple AXI4 traffic with very less resource and minimum processor intervention.In this Mode the core continuously genrates fixed address and fixed length INCR type read and write transfers.</li>
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</ul>
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<ul>
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<li>System Init Mode: System Init Mode is a special Mode where core provides only AXI4-Lite Master write interface.This mode can be used in a system without a processor to initialize the system peripherals with preconfigured values on system reset.</li>
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</ul>
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<ul>
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<li>Streaming Mode: In Streaming Mode the core can be configured to generate traffic based on the register configuration.</li>
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</ul>
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<p><b>Initialization & Configuration</b></p>
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<p>The <a class="el" href="struct_x_traf_gen___config.html">XTrafGen_Config</a> structure is used by the driver to configure itself. This configuration structure is typically created by the tool-chain based on HW build properties.</p>
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<p>To support multiple runtime loading and initialization strategies employed by various operating systems, the driver instance can be initialized in the following way:</p>
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<ul>
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<li>XTrafGen_LookupConfig(DeviceId) - Use the devide identifier to find the static configuration structure defined in <a class="el" href="xtrafgen__g_8c.html">xtrafgen_g.c</a>. This is setup by the tools. For some operating systems the config structure will be initialized by the software and this call is not needed.</li>
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</ul>
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<ul>
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<li>XTrafGen_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a configuration structure provided by the caller. If running in a system with address translation, the provided virtual memory base address replaces the physical address present in the configuration structure.</li>
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</ul>
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<p><b>Command Handling</b></p>
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<p>AXI Traffic Generator core operates based on the commands programmed into Command and Parameter RAMs. The CMDRAM and PARAMRAM is divided into two regions: write and read. Each region can hold 256 entries. Once the core is enabled, the internal control logic issues write/read commands. To handle command programming efficiently, we are maintaining a software list of commands. Following APIs are provided to handle this mechanism:</p>
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<ul>
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<li><a class="el" href="xtrafgen_8c.html#a39eaea669c1ff2df58e54c002b43f854">XTrafGen_AddCommand()</a>: This function prepares the Command Words and Parameter Word from the Command structure passed from the user application. It then adds to a software list of commands.</li>
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</ul>
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<ul>
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<li><a class="el" href="xtrafgen_8c.html#a14377a8884e99ce01c0c76128c939c49">XTrafGen_WriteCmdsToHw()</a>: This function writes the prepared list of Command and Parameter Words prepared to CMDRAM and PARAMRAM.</li>
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</ul>
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<ul>
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<li><a class="el" href="xtrafgen_8c.html#a262d850cbfc5b0495fbc2d84334a1fba">XTrafGen_GetLastValidIndex()</a>: This function gets last Valid Command Index of Write/Read region. The last valid command index is used to set 'my_depend' and 'other_depend' fields of the Command RAM.</li>
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</ul>
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<ul>
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<li><a class="el" href="xtrafgen_8c.html#a539d4976ad3ace9e15d993e2b18143a0">XTrafGen_EraseAllCommands()</a>: This function clears the list of commands maintained in software and also updates the respective RAMs.</li>
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</ul>
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<ul>
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<li>XTrafGen_PrintAllCmds(): This function displays the list of commands.</li>
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</ul>
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<p><b>Master RAM Handling</b></p>
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<p>AXI Traffic Generator uses MSTRAM to</p>
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<ul>
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<li>Take data from this RAM for write transactions</li>
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<li>Store data to this RAM for read transaction User need to call this API to write/read to/from Master RAM,</li>
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</ul>
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<ul>
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<li><a class="el" href="xtrafgen_8c.html#aaea625b89454268bbbe7f93e309141c4">XTrafGen_AccessMasterRam()</a> - This function programs the Master RAM with the data which is used in master logic. The amount of the data is limited by the size of master RAM.</li>
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</ul>
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<p><b>Interrupts</b></p>
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<p>The driver defaults to no interrupts at initialization such that interrupts must be enabled if desired. An interrupt is generated for one of the following conditions:</p>
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<ul>
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<li>Master Logic Completion Interrupt</li>
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<li>Error Interrupt (For Master and Slave Errors)</li>
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</ul>
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<p>The application can control which interrupts are enabled using these functions:</p>
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<ul>
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<li><a class="el" href="xtrafgen_8h.html#a11a588bff0d2c58310d48da4c24126a1">XTrafGen_EnableMasterCmpInterrupt()</a></li>
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<li><a class="el" href="xtrafgen_8h.html#a0a8a195712d5963fa07799d59045e86f">XTrafGen_MasterErrIntrEnable()</a></li>
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<li><a class="el" href="xtrafgen_8h.html#acd4a2d138602873e0614886c7e11b751">XTrafGen_SlaveErrIntrEnable()</a></li>
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</ul>
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<p>The interrupt system has to be set up and if the interrupts are enabled, Traffic Generator notifies the software either about the completion or an error in transfer through interrupts.</p>
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<p><b> Examples </b></p>
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<p>We provided two examples to show how to use the driver API:</p>
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<ul>
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<li>One for interrupt mode (xtrafgen_interrupt_example.c)</li>
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<li>One for polling mode (xtrafgen_polling_example.c)</li>
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</ul>
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<p><b> Asserts </b></p>
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<p>Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.</p>
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<p><b>RTOS Independence</b></p>
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<p>This driver is intended to be RTOS and processor independent. It works with physical addresses only. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver.</p>
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<pre>
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MODIFICATION HISTORY:</pre><pre> Ver Who Date Changes
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----- ---- -------- -------------------------------------------------------
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1.00a srt 01/24/13 First release
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1.01a adk 03/09/13 Updated Driver to Support Streaming and Static Mode
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2.00a adk 16/09/13 Fixed CR:737291
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2.01a adk 21/10/13 Fixed CR:740522 Updated the MasterRam offset as per latest
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IP.This driver is valid only for IP(v2.0) onwards. The
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XTG_MASTER_RAM_OFFSET has been changed from
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0x10000 to 0xc000.
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2.01a adk 15/11/13 Fixed CR:760808 added Macro's for the New bit fields added
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in the latest tarfgen IP(v2.0).
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3.0 adk 12/10/13 Updated as per the New Tcl API's
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3.1 adk 28/04/14 Fixed CR:782131 Incorrect mask value for the
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loopenable bit.
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3.2 adk 05/08/14 Fixed CR:798742 The last word of 8KB Master RAM in
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axi traffic generator can't access and CR:799554
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Some incorrect parameter in axi traffic generator driver.
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</pre> </div>
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<p class="Copyright">
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Copyright © 1995-2014 Xilinx, Inc. All rights reserved.
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</p>
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</body>
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