b0b442a12e
This patch modifies the iicps driver according to MISRAC 2012 and it supports for both Zynq and Alto. Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
380 lines
14 KiB
C
Executable file
380 lines
14 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xiicps_hw.h
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*
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* This header file contains the hardware definition for an IIC device.
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* It includes register definitions and interface functions to read/write
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* the registers.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ------ -------- -----------------------------------------------
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* 1.00a drg/jz 01/30/10 First release
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* 1.04a kpc 11/07/13 Added function prototype.
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* 2.4 sk 11/03/14 Modified the TimeOut Register value to 0xFF
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* </pre>
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*
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******************************************************************************/
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#ifndef XIICPS_HW_H /* prevent circular inclusions */
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#define XIICPS_HW_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xil_io.h"
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/************************** Constant Definitions *****************************/
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/** @name Register Map
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*
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* Register offsets for the IIC.
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* @{
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*/
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#define XIICPS_CR_OFFSET 0x00U /**< 32-bit Control */
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#define XIICPS_SR_OFFSET 0x04U /**< Status */
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#define XIICPS_ADDR_OFFSET 0x08U /**< IIC Address */
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#define XIICPS_DATA_OFFSET 0x0CU /**< IIC FIFO Data */
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#define XIICPS_ISR_OFFSET 0x10U /**< Interrupt Status */
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#define XIICPS_TRANS_SIZE_OFFSET 0x14U /**< Transfer Size */
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#define XIICPS_SLV_PAUSE_OFFSET 0x18U /**< Slave monitor pause */
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#define XIICPS_TIME_OUT_OFFSET 0x1CU /**< Time Out */
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#define XIICPS_IMR_OFFSET 0x20U /**< Interrupt Enabled Mask */
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#define XIICPS_IER_OFFSET 0x24U /**< Interrupt Enable */
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#define XIICPS_IDR_OFFSET 0x28U /**< Interrupt Disable */
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/* @} */
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/** @name Control Register
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*
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* This register contains various control bits that
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* affects the operation of the IIC controller. Read/Write.
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* @{
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*/
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#define XIICPS_CR_DIV_A_MASK 0x0000C000U /**< Clock Divisor A */
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#define XIICPS_CR_DIV_A_SHIFT 14U /**< Clock Divisor A shift */
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#define XIICPS_DIV_A_MAX 4U /**< Maximum value of Divisor A */
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#define XIICPS_CR_DIV_B_MASK 0x00003F00U /**< Clock Divisor B */
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#define XIICPS_CR_DIV_B_SHIFT 8U /**< Clock Divisor B shift */
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#define XIICPS_CR_CLR_FIFO_MASK 0x00000040U /**< Clear FIFO, auto clears*/
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#define XIICPS_CR_SLVMON_MASK 0x00000020U /**< Slave monitor mode */
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#define XIICPS_CR_HOLD_MASK 0x00000010U /**< Hold bus 1=Hold scl,
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0=terminate transfer */
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#define XIICPS_CR_ACKEN_MASK 0x00000008U /**< Enable TX of ACK when
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Master receiver*/
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#define XIICPS_CR_NEA_MASK 0x00000004U /**< Addressing Mode 1=7 bit,
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0=10 bit */
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#define XIICPS_CR_MS_MASK 0x00000002U /**< Master mode bit 1=Master,
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0=Slave */
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#define XIICPS_CR_RD_WR_MASK 0x00000001U /**< Read or Write Master
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transfer 0=Transmitter,
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1=Receiver*/
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#define XIICPS_CR_RESET_VALUE 0U /**< Reset value of the Control
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register */
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/* @} */
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/** @name IIC Status Register
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*
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* This register is used to indicate status of the IIC controller. Read only
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* @{
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*/
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#define XIICPS_SR_BA_MASK 0x00000100U /**< Bus Active Mask */
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#define XIICPS_SR_RXOVF_MASK 0x00000080U /**< Receiver Overflow Mask */
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#define XIICPS_SR_TXDV_MASK 0x00000040U /**< Transmit Data Valid Mask */
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#define XIICPS_SR_RXDV_MASK 0x00000020U /**< Receiver Data Valid Mask */
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#define XIICPS_SR_RXRW_MASK 0x00000008U /**< Receive read/write Mask */
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/* @} */
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/** @name IIC Address Register
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*
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* Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].
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* A write access to this register always initiates a transfer if the IIC is in
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* master mode. Read/Write
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* @{
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*/
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#define XIICPS_ADDR_MASK 0x000003FF /**< IIC Address Mask */
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/* @} */
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/** @name IIC Data Register
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*
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* When written to, the data register sets data to transmit. When read from, the
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* data register reads the last received byte of data. Read/Write
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* @{
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*/
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#define XIICPS_DATA_MASK 0x000000FF /**< IIC Data Mask */
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/* @} */
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/** @name IIC Interrupt Registers
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*
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* <b>IIC Interrupt Status Register</b>
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*
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* This register holds the interrupt status flags for the IIC controller. Some
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* of the flags are level triggered
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* - i.e. are set as long as the interrupt condition exists. Other flags are
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* edge triggered, which means they are set one the interrupt condition occurs
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* then remain set until they are cleared by software.
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* The interrupts are cleared by writing a one to the interrupt bit position
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* in the Interrupt Status Register. Read/Write.
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*
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* <b>IIC Interrupt Enable Register</b>
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*
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* This register is used to enable interrupt sources for the IIC controller.
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* Writing a '1' to a bit in this register clears the corresponding bit in the
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* IIC Interrupt Mask register. Write only.
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*
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* <b>IIC Interrupt Disable Register </b>
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*
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* This register is used to disable interrupt sources for the IIC controller.
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* Writing a '1' to a bit in this register sets the corresponding bit in the
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* IIC Interrupt Mask register. Write only.
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*
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* <b>IIC Interrupt Mask Register</b>
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*
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* This register shows the enabled/disabled status of each IIC controller
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* interrupt source. A bit set to 1 will ignore the corresponding interrupt in
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* the status register. A bit set to 0 means the interrupt is enabled.
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* All mask bits are set and all interrupts are disabled after reset. Read only.
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*
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* All four registers have the same bit definitions. They are only defined once
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* for each of the Interrupt Enable Register, Interrupt Disable Register,
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* Interrupt Mask Register, and Interrupt Status Register
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* @{
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*/
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#define XIICPS_IXR_ARB_LOST_MASK 0x00000200U /**< Arbitration Lost Interrupt
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mask */
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#define XIICPS_IXR_RX_UNF_MASK 0x00000080U /**< FIFO Recieve Underflow
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Interrupt mask */
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#define XIICPS_IXR_TX_OVR_MASK 0x00000040U /**< Transmit Overflow
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Interrupt mask */
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#define XIICPS_IXR_RX_OVR_MASK 0x00000020U /**< Receive Overflow Interrupt
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mask */
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#define XIICPS_IXR_SLV_RDY_MASK 0x00000010U /**< Monitored Slave Ready
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Interrupt mask */
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#define XIICPS_IXR_TO_MASK 0x00000008U /**< Transfer Time Out
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Interrupt mask */
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#define XIICPS_IXR_NACK_MASK 0x00000004U /**< NACK Interrupt mask */
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#define XIICPS_IXR_DATA_MASK 0x00000002U /**< Data Interrupt mask */
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#define XIICPS_IXR_COMP_MASK 0x00000001U /**< Transfer Complete
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Interrupt mask */
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#define XIICPS_IXR_DEFAULT_MASK 0x000002FFU /**< Default ISR Mask */
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#define XIICPS_IXR_ALL_INTR_MASK 0x000002FFU /**< All ISR Mask */
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/* @} */
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/** @name IIC Transfer Size Register
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*
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* The register's meaning varies according to the operating mode as follows:
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* - Master transmitter mode: number of data bytes still not transmitted minus
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* one
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* - Master receiver mode: number of data bytes that are still expected to be
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* received
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* - Slave transmitter mode: number of bytes remaining in the FIFO after the
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* master terminates the transfer
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* - Slave receiver mode: number of valid data bytes in the FIFO
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*
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* This register is cleared if CLR_FIFO bit in the control register is set.
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* Read/Write
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* @{
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*/
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#define XIICPS_TRANS_SIZE_MASK 0x0000003F /**< IIC Transfer Size Mask */
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#define XIICPS_FIFO_DEPTH 16 /**< Number of bytes in the FIFO */
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#define XIICPS_DATA_INTR_DEPTH 14 /**< Number of bytes at DATA intr */
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/* @} */
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/** @name IIC Slave Monitor Pause Register
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*
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* This register is associated with the slave monitor mode of the I2C interface.
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* It is meaningful only when the module is in master mode and bit SLVMON in the
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* control register is set.
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*
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* This register defines the pause interval between consecutive attempts to
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* address the slave once a write to an I2C address register is done by the
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* host. It represents the number of sclk cycles minus one between two attempts.
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*
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* The reset value of the register is 0, which results in the master repeatedly
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* trying to access the slave immediately after unsuccessful attempt.
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* Read/Write
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* @{
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*/
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#define XIICPS_SLV_PAUSE_MASK 0x0000000F /**< Slave monitor pause mask */
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/* @} */
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/** @name IIC Time Out Register
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*
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* The value of time out register represents the time out interval in number of
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* sclk cycles minus one.
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*
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* When the accessed slave holds the sclk line low for longer than the time out
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* period, thus prohibiting the I2C interface in master mode to complete the
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* current transfer, an interrupt is generated and TO interrupt flag is set.
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*
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* The reset value of the register is 0x1f.
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* Read/Write
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* @{
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*/
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#define XIICPS_TIME_OUT_MASK 0x000000FFU /**< IIC Time Out mask */
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#define XIICPS_TO_RESET_VALUE 0x000000FFU /**< IIC Time Out reset value */
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/* @} */
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define XIicPs_In32 Xil_In32
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#define XIicPs_Out32 Xil_Out32
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/****************************************************************************/
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/**
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* Read an IIC register.
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*
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* @param BaseAddress contains the base address of the device.
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* @param RegOffset contains the offset from the 1st register of the
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* device to select the specific register.
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*
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* @return The value read from the register.
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*
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* @note C-Style signature:
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* u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset)
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*
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******************************************************************************/
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#define XIicPs_ReadReg(BaseAddress, RegOffset) \
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XIicPs_In32((BaseAddress) + (u32)(RegOffset))
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/***************************************************************************/
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/**
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* Write an IIC register.
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*
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* @param BaseAddress contains the base address of the device.
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* @param RegOffset contains the offset from the 1st register of the
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* device to select the specific register.
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* @param RegisterValue is the value to be written to the register.
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*
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* @return None.
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*
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* @note C-Style signature:
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* void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)
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*
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******************************************************************************/
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#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
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XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
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/***************************************************************************/
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/**
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* Read the interrupt enable register.
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*
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* @param BaseAddress contains the base address of the device.
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*
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* @return Current bit mask that represents currently enabled interrupts.
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*
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* @note C-Style signature:
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* u32 XIicPs_ReadIER(u32 BaseAddress)
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*
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******************************************************************************/
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#define XIicPs_ReadIER(BaseAddress) \
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XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET)
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/***************************************************************************/
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/**
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* Write to the interrupt enable register.
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*
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* @param BaseAddress contains the base address of the device.
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*
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* @param IntrMask is the interrupts to be enabled.
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*
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* @return None.
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*
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* @note C-Style signature:
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* void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask)
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*
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******************************************************************************/
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#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \
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XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
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/***************************************************************************/
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/**
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* Disable all interrupts.
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*
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* @param BaseAddress contains the base address of the device.
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*
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* @return None.
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*
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* @note C-Style signature:
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* void XIicPs_DisableAllInterrupts(u32 BaseAddress)
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*
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******************************************************************************/
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#define XIicPs_DisableAllInterrupts(BaseAddress) \
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XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
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XIICPS_IXR_ALL_INTR_MASK)
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/***************************************************************************/
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/**
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* Disable selected interrupts.
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*
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* @param BaseAddress contains the base address of the device.
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*
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* @param IntrMask is the interrupts to be disabled.
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*
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* @return None.
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*
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* @note C-Style signature:
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* void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask)
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*
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******************************************************************************/
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#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \
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XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
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(IntrMask))
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/************************** Variable Definitions *****************************/
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/************************** Function Prototypes ******************************/
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/*
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* Perform reset operation to the I2c interface
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*/
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void XIicPs_ResetHw(u32 BaseAddress);
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#ifdef __cplusplus
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}
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#endif
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#endif /* end of protection macro */
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