360 lines
10 KiB
C
360 lines
10 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xrtcpsu_hw.h
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* @addtogroup rtcpsu_v1_0
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* @{
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*
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* This header file contains the identifiers and basic driver functions (or
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* macros) that can be used to access the device. Other driver functions
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* are defined in xrtcpsu.h.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ----- -------- -----------------------------------------------
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* 1.00a kvn 04/21/15 First release
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*
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* </pre>
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*
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******************************************************************************/
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#ifndef XRTC_HW_H_ /* prevent circular inclusions */
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#define XRTC_HW_H_ /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xil_io.h"
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/************************** Constant Definitions *****************************/
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/**
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* Xrtc Base Address
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*/
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#define XRTC_BASEADDR 0xFFA60000U
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/**
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* Register: XrtcSetTimeWr
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*/
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#define XRTC_SET_TIME_WR_OFFSET 0x00000000U
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#define XRTC_SET_TIME_WR_RSTVAL 0x00000000U
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#define XRTC_SET_TIME_WR_VAL_SHIFT 0U
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#define XRTC_SET_TIME_WR_VAL_WIDTH 32U
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#define XRTC_SET_TIME_WR_VAL_MASK 0xffffffffU
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#define XRTC_SET_TIME_WR_VAL_DEFVAL 0x0U
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/**
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* Register: XrtcSetTimeRd
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*/
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#define XRTC_SET_TIME_RD_OFFSET 0x00000004U
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#define XRTC_SET_TIME_RD_RSTVAL 0x00000000U
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#define XRTC_SET_TIME_RD_VAL_SHIFT 0U
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#define XRTC_SET_TIME_RD_VAL_WIDTH 32U
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#define XRTC_SET_TIME_RD_VAL_MASK 0xffffffffU
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#define XRTC_SET_TIME_RD_VAL_DEFVAL 0x0U
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/**
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* Register: XrtcCalibWr
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*/
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#define XRTC_CALIB_WR_OFFSET 0x00000008U
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#define XRTC_CALIB_WR_RSTVAL 0x00000000U
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#define XRTC_CALIB_WR_FRACTN_EN_SHIFT 20U
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#define XRTC_CALIB_WR_FRACTN_EN_WIDTH 1U
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#define XRTC_CALIB_WR_FRACTN_EN_MASK 0x00100000U
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#define XRTC_CALIB_WR_FRACTN_EN_DEFVAL 0x0U
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#define XRTC_CALIB_WR_FRACTN_DATA_SHIFT 16U
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#define XRTC_CALIB_WR_FRACTN_DATA_WIDTH 4U
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#define XRTC_CALIB_WR_FRACTN_DATA_MASK 0x000f0000U
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#define XRTC_CALIB_WR_FRACTN_DATA_DEFVAL 0x0U
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#define XRTC_CALIB_WR_MAX_TCK_SHIFT 0U
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#define XRTC_CALIB_WR_MAX_TCK_WIDTH 16U
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#define XRTC_CALIB_WR_MAX_TCK_MASK 0x0000ffffU
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#define XRTC_CALIB_WR_MAX_TCK_DEFVAL 0x0U
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/**
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* Register: XrtcCalibRd
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*/
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#define XRTC_CALIB_RD_OFFSET 0x0000000CU
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#define XRTC_CALIB_RD_RSTVAL 0x00000000U
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#define XRTC_CALIB_RD_FRACTN_EN_SHIFT 20U
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#define XRTC_CALIB_RD_FRACTN_EN_WIDTH 1U
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#define XRTC_CALIB_RD_FRACTN_EN_MASK 0x00100000U
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#define XRTC_CALIB_RD_FRACTN_EN_DEFVAL 0x0U
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#define XRTC_CALIB_RD_FRACTN_DATA_SHIFT 16U
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#define XRTC_CALIB_RD_FRACTN_DATA_WIDTH 4U
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#define XRTC_CALIB_RD_FRACTN_DATA_MASK 0x000f0000U
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#define XRTC_CALIB_RD_FRACTN_DATA_DEFVAL 0x0U
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#define XRTC_CALIB_RD_MAX_TCK_SHIFT 0U
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#define XRTC_CALIB_RD_MAX_TCK_WIDTH 16U
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#define XRTC_CALIB_RD_MAX_TCK_MASK 0x0000ffffU
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#define XRTC_CALIB_RD_MAX_TCK_DEFVAL 0x0U
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/**
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* Register: XrtcCurTime
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*/
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#define XRTC_CUR_TIME_OFFSET 0x00000010U
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#define XRTC_CUR_TIME_RSTVAL 0x00000000U
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#define XRTC_CUR_TIME_VAL_SHIFT 0U
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#define XRTC_CUR_TIME_VAL_WIDTH 32U
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#define XRTC_CUR_TIME_VAL_MASK 0xffffffffU
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#define XRTC_CUR_TIME_VAL_DEFVAL 0x0U
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/**
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* Register: XrtcCurTck
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*/
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#define XRTC_CUR_TCK_OFFSET 0x00000014U
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#define XRTC_CUR_TCK_RSTVAL 0x00000000U
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#define XRTC_CUR_TCK_VAL_SHIFT 0U
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#define XRTC_CUR_TCK_VAL_WIDTH 16U
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#define XRTC_CUR_TCK_VAL_MASK 0x0000ffffU
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#define XRTC_CUR_TCK_VAL_DEFVAL 0x0U
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/**
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* Register: XrtcAlrm
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*/
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#define XRTC_ALRM_OFFSET 0x00000018U
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#define XRTC_ALRM_RSTVAL 0x00000000U
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#define XRTC_ALRM_VAL_SHIFT 0U
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#define XRTC_ALRM_VAL_WIDTH 32U
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#define XRTC_ALRM_VAL_MASK 0xffffffffU
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#define XRTC_ALRM_VAL_DEFVAL 0x0U
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/**
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* Register: XrtcIntSts
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*/
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#define XRTC_INT_STS_OFFSET 0x00000020U
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#define XRTC_INT_STS_RSTVAL 0x00000000U
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#define XRTC_INT_STS_ALRM_SHIFT 1U
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#define XRTC_INT_STS_ALRM_WIDTH 1U
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#define XRTC_INT_STS_ALRM_MASK 0x00000002U
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#define XRTC_INT_STS_ALRM_DEFVAL 0x0U
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#define XRTC_INT_STS_SECS_SHIFT 0U
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#define XRTC_INT_STS_SECS_WIDTH 1U
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#define XRTC_INT_STS_SECS_MASK 0x00000001U
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#define XRTC_INT_STS_SECS_DEFVAL 0x0U
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/**
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* Register: XrtcIntMsk
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*/
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#define XRTC_INT_MSK_OFFSET 0x00000024U
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#define XRTC_INT_MSK_RSTVAL 0x00000003U
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#define XRTC_INT_MSK_ALRM_SHIFT 1U
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#define XRTC_INT_MSK_ALRM_WIDTH 1U
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#define XRTC_INT_MSK_ALRM_MASK 0x00000002U
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#define XRTC_INT_MSK_ALRM_DEFVAL 0x1U
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#define XRTC_INT_MSK_SECS_SHIFT 0U
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#define XRTC_INT_MSK_SECS_WIDTH 1U
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#define XRTC_INT_MSK_SECS_MASK 0x00000001U
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#define XRTC_INT_MSK_SECS_DEFVAL 0x1U
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/**
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* Register: XrtcIntEn
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*/
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#define XRTC_INT_EN_OFFSET 0x00000028U
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#define XRTC_INT_EN_RSTVAL 0x00000000U
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#define XRTC_INT_EN_ALRM_SHIFT 1U
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#define XRTC_INT_EN_ALRM_WIDTH 1U
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#define XRTC_INT_EN_ALRM_MASK 0x00000002U
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#define XRTC_INT_EN_ALRM_DEFVAL 0x0U
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#define XRTC_INT_EN_SECS_SHIFT 0U
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#define XRTC_INT_EN_SECS_WIDTH 1U
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#define XRTC_INT_EN_SECS_MASK 0x00000001U
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#define XRTC_INT_EN_SECS_DEFVAL 0x0U
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/**
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* Register: XrtcIntDis
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*/
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#define XRTC_INT_DIS_OFFSET 0x0000002CU
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#define XRTC_INT_DIS_RSTVAL 0x00000000U
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#define XRTC_INT_DIS_ALRM_SHIFT 1U
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#define XRTC_INT_DIS_ALRM_WIDTH 1U
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#define XRTC_INT_DIS_ALRM_MASK 0x00000002U
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#define XRTC_INT_DIS_ALRM_DEFVAL 0x0U
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#define XRTC_INT_DIS_SECS_SHIFT 0U
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#define XRTC_INT_DIS_SECS_WIDTH 1U
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#define XRTC_INT_DIS_SECS_MASK 0x00000001U
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#define XRTC_INT_DIS_SECS_DEFVAL 0x0U
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/**
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* Register: XrtcAddErr
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*/
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#define XRTC_ADD_ERR_OFFSET 0x00000030U
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#define XRTC_ADD_ERR_RSTVAL 0x00000000U
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#define XRTC_ADD_ERR_STS_SHIFT 0U
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#define XRTC_ADD_ERR_STS_WIDTH 1U
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#define XRTC_ADD_ERR_STS_MASK 0x00000001U
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#define XRTC_ADD_ERR_STS_DEFVAL 0x0U
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/**
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* Register: XrtcAddErrIntMsk
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*/
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#define XRTC_ADD_ERR_INT_MSK_OFFSET 0x00000034U
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#define XRTC_ADD_ERR_INT_MSK_RSTVAL 0x00000001U
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#define XRTC_ADD_ERR_INT_MSK_SHIFT 0U
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#define XRTC_ADD_ERR_INT_MSK_WIDTH 1U
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#define XRTC_ADD_ERR_INT_MSK_MASK 0x00000001U
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#define XRTC_ADD_ERR_INT_MSK_DEFVAL 0x1U
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/**
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* Register: XrtcAddErrIntEn
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*/
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#define XRTC_ADD_ERR_INT_EN_OFFSET 0x00000038U
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#define XRTC_ADD_ERR_INT_EN_RSTVAL 0x00000000U
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#define XRTC_ADD_ERR_INT_EN_MSK_SHIFT 0U
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#define XRTC_ADD_ERR_INT_EN_MSK_WIDTH 1U
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#define XRTC_ADD_ERR_INT_EN_MSK_MASK 0x00000001U
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#define XRTC_ADD_ERR_INT_EN_MSK_DEFVAL 0x0U
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/**
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* Register: XrtcAddErrIntDis
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*/
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#define XRTC_ADD_ERR_INT_DIS_OFFSET 0x0000003CU
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#define XRTC_ADD_ERR_INT_DIS_RSTVAL 0x00000000U
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#define XRTC_ADD_ERR_INT_DIS_MSK_SHIFT 0U
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#define XRTC_ADD_ERR_INT_DIS_MSK_WIDTH 1U
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#define XRTC_ADD_ERR_INT_DIS_MSK_MASK 0x00000001U
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#define XRTC_ADD_ERR_INT_DIS_MSK_DEFVAL 0x0U
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/**
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* Register: XrtcCtl
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*/
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#define XRTC_CTL_OFFSET 0x00000040U
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#define XRTC_CTL_RSTVAL 0x01000000U
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#define XRTC_CTL_BATTERY_DIS_SHIFT 31U
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#define XRTC_CTL_BATTERY_DIS_WIDTH 1U
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#define XRTC_CTL_BATTERY_DIS_MASK 0x80000000U
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#define XRTC_CTL_BATTERY_DIS_DEFVAL 0x0U
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#define XRTC_CTL_OSC_SHIFT 24U
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#define XRTC_CTL_OSC_WIDTH 4U
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#define XRTC_CTL_OSC_MASK 0x0f000000U
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#define XRTC_CTL_OSC_DEFVAL 0x1U
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#define XRTC_CTL_SLVERR_EN_SHIFT 0U
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#define XRTC_CTL_SLVERR_EN_WIDTH 1U
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#define XRTC_CTL_SLVERR_EN_MASK 0x00000001U
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#define XRTC_CTL_SLVERR_EN_DEFVAL 0x0U
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/**
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* Register: XrtcSftyChk
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*/
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#define XRTC_SFTY_CHK_OFFSET 0x00000050U
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#define XRTC_SFTY_CHK_RSTVAL 0x00000000U
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#define XRTC_SFTY_CHK_REG_SHIFT 0U
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#define XRTC_SFTY_CHK_REG_WIDTH 32U
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#define XRTC_SFTY_CHK_REG_MASK 0xffffffffU
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#define XRTC_SFTY_CHK_REG_DEFVAL 0x0U
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/**
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* Register: XrtcEco
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*/
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#define XRTC_ECO_OFFSET 0x00000060U
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#define XRTC_ECO_RSTVAL 0x00000000U
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#define XRTC_ECO_REG_SHIFT 0U
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#define XRTC_ECO_REG_WIDTH 32U
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#define XRTC_ECO_REG_MASK 0xffffffffU
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#define XRTC_ECO_REG_DEFVAL 0x0U
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/***************** Macros (Inline Functions) Definitions *********************/
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/****************************************************************************/
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/**
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*
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* This macro reads the given register.
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*
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* @param RegisterAddr is the register address in the address
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* space of the RTC device.
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*
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* @return The 32-bit value of the register
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*
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* @note None.
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*
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*****************************************************************************/
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#define XRtcPsu_ReadReg(RegisterAddr) Xil_In32(RegisterAddr)
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/****************************************************************************/
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/**
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*
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* This macro writes the given register.
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*
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* @param RegisterAddr is the register address in the address
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* space of the RTC device.
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* @param Data is the 32-bit value to write to the register.
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*
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* @return None.
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*
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* @note None.
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*
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*****************************************************************************/
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#define XRtcPsu_WriteReg(RegisterAddr, Data) Xil_Out32(RegisterAddr, (u32)(Data))
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#ifdef __cplusplus
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}
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#endif
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#endif /* XRTC_HW_H_ */
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/** @} */
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