2ba225fa69
Change CR_RESET_STATE defintion to include required bits to be set and reset. When writing to the configuration register, read the register and OR the required value to leave the reserved bits untouched. Changes done in XQspiPs_Reset function and HW reset function. The default value written was expanded to include setting hold bit and using manual chip select (This is recommended and already explicitly followed in all the examples). Removed check for register values in selftest because a reset is done in just the previous step where default values are already written. Signed-off-by: Harini Katakam <harinik@xilinx.com> Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
386 lines
14 KiB
C
Executable file
386 lines
14 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xqspips_hw.h
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*
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* This header file contains the identifiers and basic HW access driver
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* functions (or macros) that can be used to access the device. Other driver
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* functions are defined in xqspips.h.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- --- -------- -----------------------------------------------
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* 1.00 sdm 11/25/10 First release
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* 2.00a ka 07/25/12 Added a few register defines for CR 670297
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* and removed some defines of reserved fields for
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* CR 671468
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* Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
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* bit in Configuration register.
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* 2.01a sg 02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
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* which need write to clear. Removed Read zeros mask from
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* LQSPI Config register.
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* 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and
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* linear mode initialization for boot. Added related
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* constant definitions.
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* 3.1 hk 06/19/14 Changed definition of XQSPIPS_CR_RESET_STATE to set/reset
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* required bits leaving reserved bits untouched. CR# 796813.
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*
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*
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* </pre>
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*
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******************************************************************************/
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#ifndef XQSPIPS_HW_H /* prevent circular inclusions */
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#define XQSPIPS_HW_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xil_io.h"
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#include "xparameters.h"
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/************************** Constant Definitions *****************************/
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/** @name Register Map
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*
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* Register offsets from the base address of an QSPI device.
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* @{
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*/
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#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */
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#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */
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#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */
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#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */
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#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */
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#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */
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#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */
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#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */
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#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */
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#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */
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#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */
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#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */
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#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */
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#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */
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#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */
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#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */
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#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */
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#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */
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#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */
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#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */
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/* @} */
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/** @name Configuration Register
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*
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* This register contains various control bits that
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* affect the operation of the QSPI device. Read/Write.
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* @{
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*/
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#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */
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#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */
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#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */
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#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
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Enable */
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#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */
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#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */
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#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */
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#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be
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transferred */
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#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */
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#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */
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#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */
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#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */
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#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */
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#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */
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#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */
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#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */
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/* Deselect the Slave select line and set the transfer size to 32 at reset */
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#define XQSPIPS_CR_RESET_STATE ((XQSPIPS_CR_IFMODE_MASK | \
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XQSPIPS_CR_SSCTRL_MASK | \
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XQSPIPS_CR_DATA_SZ_MASK | \
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XQSPIPS_CR_MSTREN_MASK | \
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XQSPIPS_CR_SSFORCE_MASK | \
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XQSPIPS_CR_HOLD_B_MASK) & \
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(~(XQSPIPS_CR_CPOL_MASK | \
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XQSPIPS_CR_CPHA_MASK | \
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XQSPIPS_CR_PRESC_MASK | \
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XQSPIPS_CR_MANSTRTEN_MASK | \
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XQSPIPS_CR_MANSTRT_MASK | \
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XQSPIPS_CR_ENDIAN_MASK | \
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XQSPIPS_CR_REF_CLK_MASK)))
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/* @} */
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/** @name QSPI Interrupt Registers
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*
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* <b>QSPI Status Register</b>
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*
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* This register holds the interrupt status flags for an QSPI device. Some
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* of the flags are level triggered, which means that they are set as long
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* as the interrupt condition exists. Other flags are edge triggered,
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* which means they are set once the interrupt condition occurs and remain
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* set until they are cleared by software. The interrupts are cleared by
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* writing a '1' to the interrupt bit position in the Status Register.
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* Read/Write.
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*
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* <b>QSPI Interrupt Enable Register</b>
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*
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* This register is used to enable chosen interrupts for an QSPI device.
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* Writing a '1' to a bit in this register sets the corresponding bit in the
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* QSPI Interrupt Mask register. Write only.
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*
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* <b>QSPI Interrupt Disable Register </b>
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*
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* This register is used to disable chosen interrupts for an QSPI device.
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* Writing a '1' to a bit in this register clears the corresponding bit in the
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* QSPI Interrupt Mask register. Write only.
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*
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* <b>QSPI Interrupt Mask Register</b>
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*
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* This register shows the enabled/disabled interrupts of an QSPI device.
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* Read only.
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*
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* All four registers have the same bit definitions. They are only defined once
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* for each of the Interrupt Enable Register, Interrupt Disable Register,
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* Interrupt Mask Register, and Channel Interrupt Status Register
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* @{
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*/
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#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */
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#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */
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#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */
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#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */
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#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */
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#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */
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#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts
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mask */
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#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which
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need write to clear */
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#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */
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#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */
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/* @} */
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/** @name Enable Register
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*
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* This register is used to enable or disable an QSPI device.
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* Read/Write
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* @{
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*/
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#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */
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/* @} */
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/** @name Delay Register
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*
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* This register is used to program timing delays in
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* slave mode. Read/Write
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* @{
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*/
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#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select
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between two words mask */
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#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select
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between two words shift */
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#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers
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mask */
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#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */
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#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */
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#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */
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#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */
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/* @} */
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/** @name Slave Idle Count Registers
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*
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* This register defines the number of pclk cycles the slave waits for a the
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* QSPI clock to become stable in quiescent state before it can detect the start
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* of the next transfer in CPHA = 1 mode.
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* Read/Write
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*
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* @{
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*/
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#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */
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/* @} */
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/** @name Transmit FIFO Watermark Register
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*
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* This register defines the watermark setting for the Transmit FIFO.
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*
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* @{
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*/
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#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */
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#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark
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* register reset value */
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/* @} */
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/** @name Receive FIFO Watermark Register
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*
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* This register defines the watermark setting for the Receive FIFO.
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*
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* @{
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*/
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#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */
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#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark
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* register reset value */
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/* @} */
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/** @name FIFO Depth
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*
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* This macro provides the depth of transmit FIFO and receive FIFO.
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*
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* @{
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*/
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#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */
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/* @} */
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/** @name Linear QSPI Configuration Register
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*
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* This register contains various control bits that
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* affect the operation of the Linear QSPI controller. Read/Write.
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*
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* @{
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*/
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#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */
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#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */
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#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Seperate memory bus */
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#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */
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#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */
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#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */
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#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O
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or quad I/O */
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#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes
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between addr and return
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read data */
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#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */
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#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */
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/* @} */
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/** @name Linear QSPI Status Register
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*
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* This register contains various status bits of the Linear QSPI controller.
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* Read/Write.
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*
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* @{
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*/
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#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error
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received */
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#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command
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received */
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/* @} */
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/** @name Loopback Delay Adjust Register
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*
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* This register contains various bit masks of Loopback Delay Adjust Register.
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*
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* @{
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*/
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#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
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/* @} */
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define XQspiPs_In32 Xil_In32
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#define XQspiPs_Out32 Xil_Out32
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/****************************************************************************/
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/**
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* Read a register.
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*
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* @param BaseAddress contains the base address of the device.
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* @param RegOffset contains the offset from the 1st register of the
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* device to the target register.
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*
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* @return The value read from the register.
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*
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* @note C-Style signature:
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* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
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*
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******************************************************************************/
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#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
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XQspiPs_In32((BaseAddress) + (RegOffset))
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/***************************************************************************/
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/**
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* Write to a register.
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*
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* @param BaseAddress contains the base address of the device.
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* @param RegOffset contains the offset from the 1st register of the
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* device to target register.
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* @param RegisterValue is the value to be written to the register.
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*
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* @return None.
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*
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* @note C-Style signature:
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* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
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* u32 RegisterValue)
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*
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******************************************************************************/
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#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
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XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
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/************************** Function Prototypes ******************************/
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/*
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* Functions implemented in xqspips_hw.c
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*/
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void XQspiPs_ResetHw(u32 BaseAddress);
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void XQspiPs_LinearInit(u32 BaseAddress);
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/************************** Variable Definitions *****************************/
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#ifdef __cplusplus
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}
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#endif
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#endif /* end of protection macro */
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