38d86a8508
This Patch modifies the TimeOut Register value,although timeout interrupt is not used, this register is changed to set to the maximum allowed HW timeout value. Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
108 lines
4.4 KiB
C
Executable file
108 lines
4.4 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xiicps_hw.c
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*
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* Contains implementation of required functions for providing the reset sequence
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* to the i2c interface
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*
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* <pre> MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------------
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* 1.04a kpc 11/07/13 First release
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* 2.4 sk 11/03/14 Modified TimeOut Register value to 0xFF
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*
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* </pre>
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "xiicps_hw.h"
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Function Prototypes ******************************/
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/************************** Variable Definitions *****************************/
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/*****************************************************************************/
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/**
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* This function perform the reset sequence to the given I2c interface by
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* configuring the appropriate control bits in the I2c specifc registers
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* the i2cps reset squence involves the following steps
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* Disable all the interuupts
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* Clear the status
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* Clear FIFO's and disable hold bit
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* Clear the line status
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* Update relevant config registers with reset values
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*
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* @param BaseAddress of the interface
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*
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* @return N/A
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*
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* @note
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* This function will not modify the slcr registers that are relavant for
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* I2c controller
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******************************************************************************/
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void XIicPs_ResetHw(u32 BaseAddress)
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{
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u32 RegVal;
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/* Disable all the interrupts */
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XIicPs_WriteReg(BaseAddress, XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
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/* Clear the interrupt status */
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RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_ISR_OFFSET);
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XIicPs_WriteReg(BaseAddress, XIICPS_ISR_OFFSET, RegVal);
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/* Clear the hold bit,master enable bit and ack bit */
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RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_CR_OFFSET);
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RegVal &= ~(XIICPS_CR_HOLD_MASK|XIICPS_CR_MS_MASK|XIICPS_CR_ACKEN_MASK);
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/* Clear the fifos */
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RegVal |= XIICPS_CR_CLR_FIFO_MASK;
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XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, RegVal);
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/* Clear the timeout register */
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XIicPs_WriteReg(BaseAddress, XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
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/* Clear the transfer size register */
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XIicPs_WriteReg(BaseAddress, XIICPS_TRANS_SIZE_OFFSET, 0x0);
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/* Clear the status register */
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RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_SR_OFFSET);
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XIicPs_WriteReg(BaseAddress, XIICPS_SR_OFFSET, RegVal);
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/* Update the configuraqtion register with reset value */
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XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, 0x0);
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}
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